Vitis DSP Library

The Vitis™ digital signal processing library (DSPLib) provides an implementation of different L1/L2/L3 primitives for digital signal processing.

The DSPLib contains PL and AI Engine solutions. For documentation on AI Engine solutions, see Introduction.

The current PL library consists of an implementation of a Discrete Fourier Transform using a Fast Fourier Transform algorithm for acceleration on Xilinx® FPGAs. The library is planned to provide three types of implementations namely L1 primitives, L2 kernels, and L3 software APIs. Those implementations are organized in their corresponding directories L1, L2, and L3.

The L1 primitives can be leveraged by developers working on harware design implementation or designing hardware kernels for acceleration. They are particularly suitable for hardware designers. The L2 kernels are HLS-based predesigned kernels that can be directly used for FPGA acceleration of different applications on integration with the Xilinx Runtime (XRT). The L3 provides software APIs in C, C++, and Python which allow software developers to offload FFT calculation to FPGAs for acceleration. Before an FPGA can perform the FFT computation, the FPGA needs to be configured with a particular image called an overlay.

Since all the kernel code is developed with the permissive Apache 2.0 license, advanced users can easily tailor, optimize, or combine them for their own needs. Demos and usage examples of different level implementations are also provided for reference.

Library Overview

• Requirements
  • Software Platform
  • PCIE Accelerator Card
• License
• Trademark Notice
• Release Note
  • 2021.1
  • 2020.2
  • 2020.1

L1 PL DSP Library User Guide

• 1-Dimensional(Line) SSR FFT L1 FPGA Module
  • Overview
  • Multi-Instance Support
  • Data Type Support for Synthesis
    • Fixed Point
    • Floating Point
  • Managing Bit Growth in SSR FFT Stages
    • SSR_FFT_GROW_TO_MAX_WIDTH
    • SSR_FFT_SCALE
    • SSR_FFT_NO_SCALE
  • Configurations for Fixed Point Implementation (Recommended Flow)
    • Start With Floating Point Model
    • Fixed Point Modeling and Implementation
      • Fixed Point Model
      • Selecting Bit Widths for Inputs
      • Twiddle Factor or Sine/Cosine Lookup Table Quantization
      • Choosing the Best Scaling Mode
      • SSR_FFT_NO_SCALING
      • SSR_FFT_GROW_TO_MAX_WIDTH
      • SSR_FFT_SCALE
  • 1-D SSR FFT Library Usage
    • Fixed Point 1-D SSR FFT Usage
    • Floating Point 1-D SSR FFT Usage
    • 1-D SSR FFT Input Array Reading and Writing Considerations
    • 1-D SSR FFT Usage in Dataflow Region, Streaming/Non-Streaming Connections
      • Streaming Connection
      • Non-Streaming Connection
  • 1-D FFT Examples
    • 1-D Fixed Point SSR FFT Example
      • Compiling and Building Example HLS Project
    • 1-D Floating Point SSR FFT Example
      • Compiling and Building Example HLS Project
    • 1-D SSR FFT Tests
      • Launching an Individual Test
• 2-Dimensional(Matrix) SSR FFT L1 FPGA Module
  • Overview
  • Block Level Interface
  • 2-D SSR FFT Architecture
  • Supported Data Types
  • L1 API for 2-D SSR FFT
    • Template Parameters
    • Constraints on the Choice of Template Parameters
  • Library Usage
    • Fixed Point 2-D SSR FFT L1 Module Usage
    • Floating Point 2-D SSR FFT L1 Module Usage
  • 2-D SSR FFT Examples
    • 2-D Fixed Point Example
      • Top Level Definition and main Function
      • Compiling and Building Example HLS Project
    • 2-D Floating Point Example
      • Top Level Definition and main Function
      • Compiling and Building Example HLS Project
    • 2-D SSR FFT Tests
      • Launching an Individual Test

L2 DSP Library User Guide

• Introduction
  • Navigating Content by Design Process
  • Organization
  • Using Library Elements within User Defined Graphs
  • Known Issues
  • Vitis Tutorials
• DSP Library Functions
  • Filters
    • Conventions for Filters
  • FFT/iFFT
  • Matrix Multiply
  • Widgets
    • Widget API Cast
    • Widget Real to Complex
  • Compiling and Simulating Using the Makefile
    • L2 Library Element Unit Test
    • L2 Library Element Configuration Parameters
      • L2 FIR configuration parameters
      • L2 FFT configuration parameters
      • L2 Matrix Multiply Configuration Parameters
      • L2 Widgets Configuration Parameters
• Using the Examples
  • Compiling and Simulating Using the Example Design
  • Using the Vitis Unified Software Platform to Run an Example Design
    • Steps for Creating the Example Project in the Vitis IDE
  • Example Graph Coding
    • test.h
    • test.cpp
• Benchmark/QoR
  • Filters
  • FFT
  • Matrix Multiply
  • Widgets