The row number and column number of matrix are assigned as input arguments. The matrix is then generated randomly.


For representing the resource utilization in each benchmark, we separate the overall utilization into 2 parts, where P stands for the resource usage in platform, that is those instantiated in static region of the FPGA card, as well as K represents those used in kernels (dynamic region). The input is matrix, and the target device is set to Alveo U250.

Table 1 Performance for processing solver on FPGA
Architecture Matrix_Size Unroll Latency(s) Timing LUT(P/K) BRAM(P/K) URAM(P/K) DSP(P/K)
GESVDJ (U250) 512x512 16 25.94 300MHz 108.1K/21.1K 178/127 0/20 4/2
GESVJ (U250) 512x512 8 1.811 280MHz 101.7K/101.5K 165/387 0/112 4/3
GTSV (U250) 512x512 16 3.484 275MHz 101.7K/160.5K 165/523.5 0/110 4/6

These are details for benchmark result and usage steps.

Test Overview

Here are benchmarks of the Vitis Solver Library using the Vitis environment.

Vitis Solver Library

  • Download code

These solver benchmarks can be downloaded from vitis libraries master branch.

git clone
cd Vitis_Libraries
git checkout master
cd solver
  • Setup environment

Specifying the corresponding Vitis, XRT, and path to the platform repository by running following commands.

source /opt/xilinx/Vitis/2021.1/
source /opt/xilinx/xrt/
export PLATFORM_REPO_PATHS=/opt/xilinx/platforms