System Requirements

Host System Hardware

• Hardware Debug Connection

  • Xilinx Platform Cable USB II

  • Xilinx SmartLynq Data Cable

  • Xilinx SmartLynq+ Module

Host System Software

• Operating System: please refer to Vivado Design Suite User Guide

• 2022.1 or newer Xilinx Hardware Server hw_server

• 2022.1 or newer Xilinx ChipScope Server cs_server

• Python 3.8 or newer

• ChipScoPy Python Package

• ChipScoPy Examples

Note

Please see ChipScoPy Installation for a complete guide to installation.

Supported Versal-Based Boards

The example designs distributed with ChipScoPy are supported for these hardware boards:

• VCK190 (Versal AI Core Series Evaluation Board):

  • Versal VC1902 Device

  • VCK190 product page

• VMK180 (Versal Prime Series Evaluation Board):

  • Versal VM1802 Device

  • VMK180 product page

User Designs

ChipScoPy supports user-generated designs targeting any Versal series device. To interact with a user design, first supply the PDI and LTX files to the programming and discovery routines.

The standard design flow will produce these output products for user-generated projects.

Vivado Design Flow

Note

Certain examples may also require the “hardware hand-off” file or <project_name>.hwh from the user-generated project.