Enumerations¶
enum cmpt_desc_sz_t¶
Overview
Descriptor sizes
// enum values CMPT_DESC_SZ_8B = 0 CMPT_DESC_SZ_16B CMPT_DESC_SZ_32B CMPT_DESC_SZ_64B
Enum values
Value Description
CMPT_DESC_SZ_8B
completion size 8B
CMPT_DESC_SZ_16B
completion size 16B
CMPT_DESC_SZ_32B
completion size 32B
CMPT_DESC_SZ_64B
completion size 64B
enum desc_sz_t¶
Overview
Descriptor sizes
// enum values DESC_SZ_8B = 0 DESC_SZ_16B DESC_SZ_32B DESC_SZ_64B
Enum values
Value Description
DESC_SZ_8B
descriptor size 8B
DESC_SZ_16B
descriptor size 16B
DESC_SZ_32B
descriptor size 32B
DESC_SZ_64B
descriptor size 64B
enum intr_ring_size_sel¶
Overview
Qdma interrupt ring size selection
Each interrupt vector can be associated with 1 or more interrupt rings. The software can choose 8 different interrupt ring sizes. The ring size for each vector is programmed during interrupt context programming
// enum values INTR_RING_SZ_4KB = 0 INTR_RING_SZ_8KB INTR_RING_SZ_12KB INTR_RING_SZ_16KB INTR_RING_SZ_20KB INTR_RING_SZ_24KB INTR_RING_SZ_28KB INTR_RING_SZ_32KB
Enum values
Value Description
INTR_RING_SZ_4KB
accommodates 512 entries
INTR_RING_SZ_8KB
accommodates 1024 entries
INTR_RING_SZ_12KB
accommodates 1536 entries
INTR_RING_SZ_16KB
accommodates 2048 entries
INTR_RING_SZ_20KB
accommodates 2560 entries
INTR_RING_SZ_24KB
accommodates 3072 entries
INTR_RING_SZ_28KB
accommodates 3584 entries
INTR_RING_SZ_32KB
accommodates 4096 entries
enum q_state_t¶
Overview
Queue can be in one of the following states
// enum values Q_STATE_DISABLED = 0 Q_STATE_ENABLED Q_STATE_ONLINE
Enum values
Parameters: Parameters: Parameters:Value Description
Q_STATE_DISABLED
Q_STATE_DISABLED
Queue is not taken
Q_STATE_ENABLED
Q_STATE_ENABLED
Assigned/taken. Partial config is done
Q_STATE_ONLINE
Q_STATE_ONLINE
Resource/context is initialized for the queue and is available for data consumption
enum qdma_dev_qmax_state¶
Overview
Qdma function states
Each PF/VF device can be configured with 0 or more number of queues. When the queue is not assigned to any function, function is in unfonfigured state. Sysfs interface enables the users to configure the number of queues to different functions. Upon adding the queues, function moves to user configured state.
// enum values QMAX_CFG_UNCONFIGURED QMAX_CFG_INITIAL QMAX_CFG_USER
Enum values
Parameters: Parameters: Parameters:Value Description
QMAX_CFG_UNCONFIGURED
QMAX_CFG_UNCONFIGURED
queue max not configured
QMAX_CFG_INITIAL
QMAX_CFG_INITIAL
queue max configured with initial default values
QMAX_CFG_USER
QMAX_CFG_USER
queue max configured from sysfs as per user choice
enum qdma_drv_mode¶
Overview
PF/VF qdma driver modes
QDMA PF/VF drivers can be loaded in one of these modes. Mode options is exposed as a user configurable module parameter
// enum values AUTO_MODE POLL_MODE DIRECT_INTR_MODE INDIRECT_INTR_MODE LEGACY_INTR_MODE
Enum values
Parameters: Parameters: Parameters: Parameters: Parameters:Value Description
AUTO_MODE
AUTO_MODE
Auto mode is mix of Poll and Interrupt Aggregation mode. Driver polls for the write back status updates. Interrupt aggregation is used for processing the completion ring
POLL_MODE
POLL_MODE
In Poll Mode, Software polls for the write back completions (Status Descriptor Write Back)
DIRECT_INTR_MODE
DIRECT_INTR_MODE
Direct Interrupt mode, each queue is assigned to one of the available interrupt vectors in a round robin fashion to service the requests. Interrupt is raised by the HW upon receiving the completions and software reads the completion status.
INDIRECT_INTR_MODE
INDIRECT_INTR_MODE
In Indirect Interrupt mode or Interrupt Aggregation mode, each vector has an associated Interrupt Aggregation Ring. The QID and status of queues requiring service are written into the Interrupt Aggregation Ring. When a PCIe MSI-X interrupt is received by the Host, the software reads the Interrupt Aggregation Ring to determine which queue needs service. Mapping of queues to vectors is programmable
LEGACY_INTR_MODE
LEGACY_INTR_MODE
Driver is inserted in legacy interrupt mode Software serves status updates upon receiving the legacy interrupt
enum qdma_q_dir¶
Overview
Direction of the queue
// enum values QDMA_Q_DIR_H2C QDMA_Q_DIR_C2H
Enum values
Value Description
QDMA_Q_DIR_H2C
host to card
QDMA_Q_DIR_C2H
card to host
enum qdma_q_mode¶
Overview
Per queue DMA AXI Interface option
// enum values QDMA_Q_MODE_MM QDMA_Q_MODE_ST
Enum values
Value Description
QDMA_Q_MODE_MM
AXI Memory Mapped Mode
QDMA_Q_MODE_ST
AXI Stream Mode
enum queue_type_t¶
Overview
Queue direction types
// enum values Q_H2C Q_C2H Q_CMPT Q_H2C_C2H
Enum values
Value Description
Q_H2C
host to card
Q_C2H
card to host
Q_CMPT
cmpt queue
Q_H2C_C2H
Both H2C and C2H directions
enum tigger_mode_t¶
Overview
Trigger modes
// enum values TRIG_MODE_DISABLE TRIG_MODE_ANY TRIG_MODE_COUNTER TRIG_MODE_USER TRIG_MODE_TIMER TRIG_MODE_COMBO
Enum values
Value Description
TRIG_MODE_DISABLE
disable trigger mode
TRIG_MODE_ANY
any trigger mode
TRIG_MODE_COUNTER
counter trigger mode
TRIG_MODE_USER
trigger mode of user choice
TRIG_MODE_TIMER
timer trigger mode
TRIG_MODE_COMBO
timer and counter combo trigger mode