Overview

This header file contains macros that can be used to access the device.

Note: None.

MODIFICATION HISTORY:

Ver Who Date Changes

1.0 aad 02/24/17 Initial Release 1.0 mh 06/24/17 Added Clock related register information 2.0 aad 10/07/17 Removed Macros related to Video and Audio Src

Macros
#define	XAVBUF_BASEADDR 0xFD4A0000
	Address mapping for the DisplayPort TX core. More...

#define	XAVBUF_V_BLEND_BG_CLR_0 0X0000A000

#define	XAVBUF_V_BLEND_BG_CLR_1 0X0000A004

#define	XAVBUF_V_BLEND_BG_CLR_2 0X0000A008

#define	XAVBUF_V_BLEND_SET_GLOBAL_ALPHA_REG 0X0000A00C

#define	XAVBUF_V_BLEND_OUTPUT_VID_FORMAT 0X0000A014

#define	XAVBUF_V_BLEND_LAYER0_CONTROL 0X0000A018

#define	XAVBUF_V_BLEND_LAYER1_CONTROL 0X0000A01C

#define	XAVBUF_V_BLEND_RGB2YCBCR_COEFF0 0X0000A020

#define	XAVBUF_V_BLEND_RGB2YCBCR_COEFF1 0X0000A024

#define	XAVBUF_V_BLEND_RGB2YCBCR_COEFF2 0X0000A028

#define	XAVBUF_V_BLEND_RGB2YCBCR_COEFF3 0X0000A02C

#define	XAVBUF_V_BLEND_RGB2YCBCR_COEFF4 0X0000A030

#define	XAVBUF_V_BLEND_RGB2YCBCR_COEFF5 0X0000A034

#define	XAVBUF_V_BLEND_RGB2YCBCR_COEFF6 0X0000A038

#define	XAVBUF_V_BLEND_RGB2YCBCR_COEFF7 0X0000A03C

#define	XAVBUF_V_BLEND_RGB2YCBCR_COEFF8 0X0000A040

#define	XAVBUF_V_BLEND_IN1CSC_COEFF0 0X0000A044

#define	XAVBUF_V_BLEND_IN1CSC_COEFF1 0X0000A048

#define	XAVBUF_V_BLEND_IN1CSC_COEFF2 0X0000A04C

#define	XAVBUF_V_BLEND_IN1CSC_COEFF3 0X0000A050

#define	XAVBUF_V_BLEND_IN1CSC_COEFF4 0X0000A054

#define	XAVBUF_V_BLEND_IN1CSC_COEFF5 0X0000A058

#define	XAVBUF_V_BLEND_IN1CSC_COEFF6 0X0000A05C

#define	XAVBUF_V_BLEND_IN1CSC_COEFF7 0X0000A060

#define	XAVBUF_V_BLEND_IN1CSC_COEFF8 0X0000A064

#define	XAVBUF_V_BLEND_LUMA_IN1CSC_OFFSET 0X0000A068

#define	XAVBUF_V_BLEND_CR_IN1CSC_OFFSET 0X0000A06C

#define	XAVBUF_V_BLEND_CB_IN1CSC_OFFSET 0X0000A070

#define	XAVBUF_V_BLEND_LUMA_OUTCSC_OFFSET 0X0000A074

#define	XAVBUF_V_BLEND_CR_OUTCSC_OFFSET 0X0000A078

#define	XAVBUF_V_BLEND_CB_OUTCSC_OFFSET 0X0000A07C

#define	XAVBUF_V_BLEND_IN2CSC_COEFF0 0X0000A080

#define	XAVBUF_V_BLEND_IN2CSC_COEFF1 0X0000A084

#define	XAVBUF_V_BLEND_IN2CSC_COEFF2 0X0000A088

#define	XAVBUF_V_BLEND_IN2CSC_COEFF3 0X0000A08C

#define	XAVBUF_V_BLEND_IN2CSC_COEFF4 0X0000A090

#define	XAVBUF_V_BLEND_IN2CSC_COEFF5 0X0000A094

#define	XAVBUF_V_BLEND_IN2CSC_COEFF6 0X0000A098

#define	XAVBUF_V_BLEND_IN2CSC_COEFF7 0X0000A09C

#define	XAVBUF_V_BLEND_IN2CSC_COEFF8 0X0000A0A0

#define	XAVBUF_V_BLEND_LUMA_IN2CSC_OFFSET 0X0000A0A4

#define	XAVBUF_V_BLEND_CR_IN2CSC_OFFSET 0X0000A0A8

#define	XAVBUF_V_BLEND_CB_IN2CSC_OFFSET 0X0000A0AC

#define	XAVBUF_V_BLEND_CHROMA_KEY_ENABLE 0X0000A1D0

#define	XAVBUF_V_BLEND_CHROMA_KEY_COMP1 0X0000A1D4

#define	XAVBUF_V_BLEND_CHROMA_KEY_COMP2 0X0000A1D8

#define	XAVBUF_V_BLEND_CHROMA_KEY_COMP3 0X0000A1DC

#define	XAVBUF_BUF_FORMAT 0X0000B000

#define	XAVBUF_BUF_NON_LIVE_LATENCY 0X0000B008

#define	XAVBUF_CHBUF0 0X0000B010

#define	XAVBUF_CHBUF1 0X0000B014

#define	XAVBUF_CHBUF2 0X0000B018

#define	XAVBUF_CHBUF3 0X0000B01C

#define	XAVBUF_CHBUF4 0X0000B020

#define	XAVBUF_CHBUF5 0X0000B024

#define	XAVBUF_BUF_STC_CONTROL 0X0000B02C

#define	XAVBUF_BUF_STC_INIT_VALUE0 0X0000B030

#define	XAVBUF_BUF_STC_INIT_VALUE1 0X0000B034

#define	XAVBUF_BUF_STC_ADJ 0X0000B038

#define	XAVBUF_BUF_STC_VID_VSYNC_TS_REG0 0X0000B03C

#define	XAVBUF_BUF_STC_VID_VSYNC_TS_REG1 0X0000B040

#define	XAVBUF_BUF_STC_EXT_VSYNC_TS_REG0 0X0000B044

#define	XAVBUF_BUF_STC_EXT_VSYNC_TS_REG1 0X0000B048

#define	XAVBUF_BUF_STC_CUSTOM_EVENT_TS_REG0 0X0000B04C

#define	XAVBUF_BUF_STC_CUSTOM_EVENT_TS_REG1 0X0000B050

#define	XAVBUF_BUF_STC_CUSTOM_EVENT2_TS_REG0 0X0000B054

#define	XAVBUF_BUF_STC_CUSTOM_EVENT2_TS_REG1 0X0000B058

#define	XAVBUF_BUF_STC_SNAPSHOT0 0X0000B060

#define	XAVBUF_BUF_STC_SNAPSHOT1 0X0000B064

#define	XAVBUF_BUF_OUTPUT_AUD_VID_SELECT 0X0000B070

#define	XAVBUF_BUF_HCOUNT_VCOUNT_INT0 0X0000B074

#define	XAVBUF_BUF_HCOUNT_VCOUNT_INT1 0X0000B078

#define	XAVBUF_BUF_DITHER_CFG 0X0000B07C

#define	XAVBUF_DITHER_CFG_SEED0 0X0000B080

#define	XAVBUF_DITHER_CFG_SEED1 0X0000B084

#define	XAVBUF_DITHER_CFG_SEED2 0X0000B088

#define	XAVBUF_DITHER_CFG_MAX 0X0000B08C

#define	XAVBUF_DITHER_CFG_MIN 0X0000B090

#define	XAVBUF_PATTERN_GEN_SELECT 0X0000B100

#define	XAVBUF_AUD_PATTERN_SELECT1 0X0000B104

#define	XAVBUF_AUD_PATTERN_SELECT2 0X0000B108

#define	XAVBUF_BUF_AUD_VID_CLK_SOURCE 0X0000B120

#define	XAVBUF_BUF_SRST_REG 0X0000B124

#define	XAVBUF_BUF_AUD_RDY_INTERVAL 0X0000B128

#define	XAVBUF_BUF_AUD_CH_CFG 0X0000B12C

#define	XAVBUF_BUF_GRAPHICS_COMP0_SCALE_FACTOR 0X0000B200

#define	XAVBUF_BUF_GRAPHICS_COMP1_SCALE_FACTOR 0X0000B204

#define	XAVBUF_BUF_GRAPHICS_COMP2_SCALE_FACTOR 0X0000B208

#define	XAVBUF_BUF_VID_COMP0_SCALE_FACTOR 0X0000B20C

#define	XAVBUF_BUF_VID_COMP1_SCALE_FACTOR 0X0000B210

#define	XAVBUF_BUF_VID_COMP2_SCALE_FACTOR 0X0000B214

#define	XAVBUF_BUF_LIVE_VID_COMP0_SF 0X0000B218

#define	XAVBUF_BUF_LIVE_VID_COMP1_SF 0X0000B21C

#define	XAVBUF_BUF_LIVE_VID_COMP2_SF 0X0000B220

#define	XAVBUF_BUF_LIVE_VID_CFG 0X0000B224

#define	XAVBUF_BUF_LIVE_GFX_COMP0_SF 0X0000B228

#define	XAVBUF_BUF_LIVE_GFX_COMP1_SF 0X0000B22C

#define	XAVBUF_BUF_LIVE_GFX_COMP2_SF 0X0000B230

#define	XAVBUF_BUF_LIVE_GFX_CFG 0X0000B234

#define	XAVBUF_AUD_MIXER_VOLUME_CONTROL 0X0000C000

#define	XAVBUF_AUD_MIXER_META_DATA 0X0000C004

#define	XAVBUF_AUD_CH_STATUS_REG0 0X0000C008

#define	XAVBUF_AUD_CH_STATUS_REG1 0X0000C00C

#define	XAVBUF_AUD_CH_STATUS_REG2 0X0000C010

#define	XAVBUF_AUD_CH_STATUS_REG3 0X0000C014

#define	XAVBUF_AUD_CH_STATUS_REG4 0X0000C018

#define	XAVBUF_AUD_CH_STATUS_REG5 0X0000C01C

#define	XAVBUF_AUD_CH_A_DATA_REG0 0X0000C020

#define	XAVBUF_AUD_CH_A_DATA_REG1 0X0000C024

#define	XAVBUF_AUD_CH_A_DATA_REG2 0X0000C028

#define	XAVBUF_AUD_CH_A_DATA_REG3 0X0000C02C

#define	XAVBUF_AUD_CH_A_DATA_REG4 0X0000C030

#define	XAVBUF_AUD_CH_A_DATA_REG5 0X0000C034

#define	XAVBUF_AUD_CH_B_DATA_REG0 0X0000C038

#define	XAVBUF_AUD_CH_B_DATA_REG1 0X0000C03C

#define	XAVBUF_AUD_CH_B_DATA_REG2 0X0000C040

#define	XAVBUF_AUD_CH_B_DATA_REG3 0X0000C044

#define	XAVBUF_AUD_CH_B_DATA_REG4 0X0000C048

#define	XAVBUF_AUD_CH_B_DATA_REG5 0X0000C04C

#define	XAVBUF_AUD_SOFT_RST 0X0000CC00

#define	XAVBUF_PATGEN_CRC_R 0X0000CC10

#define	XAVBUF_PATGEN_CRC_G 0X0000CC14

#define	XAVBUF_PATGEN_CRC_B 0X0000CC18

#define	XAVBUF_CLK_FPD_BASEADDR 0XFD1A0000
	Address mapping for PLL (CRF and CRL) More...

#define	XAVBUF_PLL_CTRL 0X00000020
	The following constants define values to manipulate the bits of the VPLL control register. More...

#define	XAVBUF_PLL_CFG 0X00000024
	The following constants define values to manipulate the bits of the PLL config register. More...

#define	XAVBUF_PLL_FRAC_CFG 0X00000028
	The following constants define values to manipulate the bits of the VPLL fractional config register. More...

#define	XAVBUF_PLL_STATUS 0X00000044
	The following constants define values to manipulate the bits of the PLL STATUS register. More...

#define	XAVBUF_VIDEO_REF_CTRL 0X00000070
	The following constants define values to manipulate the bits of the VIDEO reference control register. More...

#define	XAVBUF_AUDIO_REF_CTRL 0X00000074
	The following constants define values to manipulate the bits of the AUDIO reference control register. More...

#define	XAVBUF_DOMAIN_SWITCH_CTRL 0X00000044
	The following constants define values to manipulate the bits of the Domain Switch register. More...

#define	XAVBUF_Pss_Ref_Clk 0
	The following constants define values to Reference clock. More...

#define	XAVBUF_ENABLE_BIT 1
	The following constants define values to manipulate the bits of any register. More...

#define	XAVBUF_VPLL_SRC_SEL 0
	The following constants define values available PLL source to Audio and Video. More...

#define	XAVBuf_ReadReg(BaseAddress, RegOffset) XAVBuf_In32((BaseAddress) + (RegOffset))
	This is a low-level function that reads from the specified register. More...

#define	XAVBuf_WriteReg(BaseAddress, RegOffset, Data) XAVBuf_Out32((BaseAddress) + (RegOffset), (Data))
	This is a low-level function that writes to the specified register. More...

Register access macro definitions.
#define	XAVBuf_In32 Xil_In32

#define	XAVBuf_Out32 Xil_Out32

Macro Definition Documentation

#define XAVBUF_AUD_CH_A_DATA_REG0 0X0000C020

Register: XAVBUF_AUD_CH_A_DATA_REG0

#define XAVBUF_AUD_CH_A_DATA_REG1 0X0000C024

Register: XAVBUF_AUD_CH_A_DATA_REG1

#define XAVBUF_AUD_CH_A_DATA_REG2 0X0000C028

Register: XAVBUF_AUD_CH_A_DATA_REG2

#define XAVBUF_AUD_CH_A_DATA_REG3 0X0000C02C

Register: XAVBUF_AUD_CH_A_DATA_REG3

#define XAVBUF_AUD_CH_A_DATA_REG4 0X0000C030

Register: XAVBUF_AUD_CH_A_DATA_REG4

#define XAVBUF_AUD_CH_A_DATA_REG5 0X0000C034

Register: XAVBUF_AUD_CH_A_DATA_REG5

#define XAVBUF_AUD_CH_B_DATA_REG0 0X0000C038

Register: XAVBUF_AUD_CH_B_DATA_REG0

#define XAVBUF_AUD_CH_B_DATA_REG1 0X0000C03C

Register: XAVBUF_AUD_CH_B_DATA_REG1

#define XAVBUF_AUD_CH_B_DATA_REG2 0X0000C040

Register: XAVBUF_AUD_CH_B_DATA_REG2

#define XAVBUF_AUD_CH_B_DATA_REG3 0X0000C044

Register: XAVBUF_AUD_CH_B_DATA_REG3

#define XAVBUF_AUD_CH_B_DATA_REG4 0X0000C048

Register: XAVBUF_AUD_CH_B_DATA_REG4

#define XAVBUF_AUD_CH_B_DATA_REG5 0X0000C04C

Register: XAVBUF_AUD_CH_B_DATA_REG5

#define XAVBUF_AUD_CH_STATUS_REG0 0X0000C008

Register: XAVBUF_AUD_CH_STATUS_REG0

#define XAVBUF_AUD_CH_STATUS_REG1 0X0000C00C

Register: XAVBUF_AUD_CH_STATUS_REG1

#define XAVBUF_AUD_CH_STATUS_REG2 0X0000C010

Register: XAVBUF_AUD_CH_STATUS_REG2

#define XAVBUF_AUD_CH_STATUS_REG3 0X0000C014

Register: XAVBUF_AUD_CH_STATUS_REG3

#define XAVBUF_AUD_CH_STATUS_REG4 0X0000C018

Register: XAVBUF_AUD_CH_STATUS_REG4

#define XAVBUF_AUD_CH_STATUS_REG5 0X0000C01C

Register: XAVBUF_AUD_CH_STATUS_REG5

#define XAVBUF_AUD_MIXER_META_DATA 0X0000C004

Register: XAVBUF_AUD_MIXER_META_DATA

#define XAVBUF_AUD_MIXER_VOLUME_CONTROL 0X0000C000

Register: XAVBUF_AUD_MIXER_VOLUME_CONTROL

Referenced by XAVBuf_AudioMixerVolumeControl().

#define XAVBUF_AUD_PATTERN_SELECT1 0X0000B104

Register: XAVBUF_AUD_PATTERN_SELECT1

#define XAVBUF_AUD_PATTERN_SELECT2 0X0000B108

Register: XAVBUF_AUD_PATTERN_SELECT2

#define XAVBUF_AUD_SOFT_RST 0X0000CC00

Register: XAVBUF_AUD_SOFT_RST

Referenced by XABuf_LineResetDisable(), XAVBuf_AudioSoftReset(), and XAVBuf_Initialize().

#define XAVBUF_AUDIO_REF_CTRL 0X00000074

The following constants define values to manipulate the bits of the AUDIO reference control register.

Referenced by XAVBuf_SetAudioClock().

#define XAVBUF_BASEADDR 0xFD4A0000

Address mapping for the DisplayPort TX core.

#define XAVBUF_BUF_AUD_CH_CFG 0X0000B12C

Register: XAVBUF_BUF_AUD_CH_CFG

#define XAVBUF_BUF_AUD_RDY_INTERVAL 0X0000B128

Register: XAVBUF_BUF_AUD_RDY_INTERVAL

#define XAVBUF_BUF_AUD_VID_CLK_SOURCE 0X0000B120

Register: XAVBUF_BUF_AUD_VID_CLK_SOURCE

Referenced by XAVBuf_SetAudioVideoClkSrc().

#define XAVBUF_BUF_DITHER_CFG 0X0000B07C

Register: XAVBUF_BUF_DITHER_CFG

#define XAVBUF_BUF_FORMAT 0X0000B000

Register: XAVBUF_BUF_FORMAT

#define XAVBUF_BUF_GRAPHICS_COMP0_SCALE_FACTOR 0X0000B200

Register: XAVBUF_BUF_GRAPHICS_COMP0_SCALE_FACTOR

#define XAVBUF_BUF_GRAPHICS_COMP1_SCALE_FACTOR 0X0000B204

Register: XAVBUF_BUF_GRAPHICS_COMP1_SCALE_FACTOR

#define XAVBUF_BUF_GRAPHICS_COMP2_SCALE_FACTOR 0X0000B208

Register: XAVBUF_BUF_GRAPHICS_COMP2_SCALE_FACTOR

#define XAVBUF_BUF_HCOUNT_VCOUNT_INT0 0X0000B074

Register: XAVBUF_BUF_HCOUNT_VCOUNT_INT0

#define XAVBUF_BUF_HCOUNT_VCOUNT_INT1 0X0000B078

Register: XAVBUF_BUF_HCOUNT_VCOUNT_INT1

#define XAVBUF_BUF_LIVE_GFX_CFG 0X0000B234

Register: XAVBUF_BUF_LIVE_GFX_CFG

#define XAVBUF_BUF_LIVE_GFX_COMP0_SF 0X0000B228

Register: XAVBUF_BUF_LIVE_GFX_COMP0_SF

#define XAVBUF_BUF_LIVE_GFX_COMP1_SF 0X0000B22C

Register: XAVBUF_BUF_LIVE_GFX_COMP1_SF

#define XAVBUF_BUF_LIVE_GFX_COMP2_SF 0X0000B230

Register: XAVBUF_BUF_LIVE_GFX_COMP2_SF

#define XAVBUF_BUF_LIVE_VID_CFG 0X0000B224

Register: XAVBUF_BUF_LIVE_VID_CFG

#define XAVBUF_BUF_LIVE_VID_COMP0_SF 0X0000B218

Register: XAVBUF_BUF_LIVE_VID_COMP0_SF

#define XAVBUF_BUF_LIVE_VID_COMP1_SF 0X0000B21C

Register: XAVBUF_BUF_LIVE_VID_COMP1_SF

#define XAVBUF_BUF_LIVE_VID_COMP2_SF 0X0000B220

Register: XAVBUF_BUF_LIVE_VID_COMP2_SF

#define XAVBUF_BUF_NON_LIVE_LATENCY 0X0000B008

Register: XAVBUF_BUF_NON_LIVE_LATENCY

#define XAVBUF_BUF_OUTPUT_AUD_VID_SELECT 0X0000B070

Register: XAVBUF_BUF_OUTPUT_AUD_VID_SELECT

Referenced by XAVBuf_InputAudioSelect(), and XAVBuf_InputVideoSelect().

#define XAVBUF_BUF_SRST_REG 0X0000B124

Register: XAVBUF_BUF_SRST_REG

Referenced by XAVBuf_SoftReset().

#define XAVBUF_BUF_STC_ADJ 0X0000B038

Register: XAVBUF_BUF_STC_ADJ

#define XAVBUF_BUF_STC_CONTROL 0X0000B02C

Register: XAVBUF_BUF_STC_CONTROL

#define XAVBUF_BUF_STC_CUSTOM_EVENT2_TS_REG0 0X0000B054

Register: XAVBUF_BUF_STC_CUSTOM_EVENT2_TS_REG0

#define XAVBUF_BUF_STC_CUSTOM_EVENT2_TS_REG1 0X0000B058

Register: XAVBUF_BUF_STC_CUSTOM_EVENT2_TS_REG1

#define XAVBUF_BUF_STC_CUSTOM_EVENT_TS_REG0 0X0000B04C

Register: XAVBUF_BUF_STC_CUSTOM_EVENT_TS_REG0

#define XAVBUF_BUF_STC_CUSTOM_EVENT_TS_REG1 0X0000B050

Register: XAVBUF_BUF_STC_CUSTOM_EVENT_TS_REG1

#define XAVBUF_BUF_STC_EXT_VSYNC_TS_REG0 0X0000B044

Register: XAVBUF_BUF_STC_EXT_VSYNC_TS_REG0

#define XAVBUF_BUF_STC_EXT_VSYNC_TS_REG1 0X0000B048

Register: XAVBUF_BUF_STC_EXT_VSYNC_TS_REG1

#define XAVBUF_BUF_STC_INIT_VALUE0 0X0000B030

Register: XAVBUF_BUF_STC_INIT_VALUE0

#define XAVBUF_BUF_STC_INIT_VALUE1 0X0000B034

Register: XAVBUF_BUF_STC_INIT_VALUE1

#define XAVBUF_BUF_STC_SNAPSHOT0 0X0000B060

Register: XAVBUF_BUF_STC_SNAPSHOT0

#define XAVBUF_BUF_STC_SNAPSHOT1 0X0000B064

Register: XAVBUF_BUF_STC_SNAPSHOT1

#define XAVBUF_BUF_STC_VID_VSYNC_TS_REG0 0X0000B03C

Register: XAVBUF_BUF_STC_VID_VSYNC_TS_REG0

#define XAVBUF_BUF_STC_VID_VSYNC_TS_REG1 0X0000B040

Register: XAVBUF_BUF_STC_VID_VSYNC_TS_REG1

#define XAVBUF_BUF_VID_COMP0_SCALE_FACTOR 0X0000B20C

Register: XAVBUF_BUF_VID_COMP0_SCALE_FACTOR

#define XAVBUF_BUF_VID_COMP1_SCALE_FACTOR 0X0000B210

Register: XAVBUF_BUF_VID_COMP1_SCALE_FACTOR

#define XAVBUF_BUF_VID_COMP2_SCALE_FACTOR 0X0000B214

Register: XAVBUF_BUF_VID_COMP2_SCALE_FACTOR

#define XAVBUF_CHBUF0 0X0000B010

Register: XAVBUF_CHBUF0

Referenced by XAVBuf_EnableVideoBuffers().

#define XAVBUF_CHBUF1 0X0000B014

Register: XAVBUF_CHBUF1

#define XAVBUF_CHBUF2 0X0000B018

Register: XAVBUF_CHBUF2

#define XAVBUF_CHBUF3 0X0000B01C

Register: XAVBUF_CHBUF3

Referenced by XAVBuf_EnableGraphicsBuffers().

#define XAVBUF_CHBUF4 0X0000B020

Register: XAVBUF_CHBUF4

Referenced by XAVBuf_EnableAudio0Buffers().

#define XAVBUF_CHBUF5 0X0000B024

Register: XAVBUF_CHBUF5

Referenced by XAVBuf_EnableAudio1Buffers().

#define XAVBUF_CLK_FPD_BASEADDR 0XFD1A0000

Address mapping for PLL (CRF and CRL)

Referenced by XAVBuf_SetAudioClock(), and XAVBuf_SetPixelClock().

#define XAVBUF_DITHER_CFG_MAX 0X0000B08C

Register: XAVBUF_DITHER_CFG_MAX

#define XAVBUF_DITHER_CFG_MIN 0X0000B090

Register: XAVBUF_DITHER_CFG_MIN

#define XAVBUF_DITHER_CFG_SEED0 0X0000B080

Register: XAVBUF_DITHER_CFG_SEED0

#define XAVBUF_DITHER_CFG_SEED1 0X0000B084

Register: XAVBUF_DITHER_CFG_SEED1

#define XAVBUF_DITHER_CFG_SEED2 0X0000B088

Register: XAVBUF_DITHER_CFG_SEED2

#define XAVBUF_DOMAIN_SWITCH_CTRL 0X00000044

The following constants define values to manipulate the bits of the Domain Switch register.

For eg. FPD to LPD.

#define XAVBUF_ENABLE_BIT 1

The following constants define values to manipulate the bits of any register.

#define XAVBUF_PATGEN_CRC_B 0X0000CC18

Register: XAVBUF_PATGEN_CRC_B

#define XAVBUF_PATGEN_CRC_G 0X0000CC14

Register: XAVBUF_PATGEN_CRC_G

#define XAVBUF_PATGEN_CRC_R 0X0000CC10

Register: XAVBUF_PATGEN_CRC_R

#define XAVBUF_PATTERN_GEN_SELECT 0X0000B100

Register: XAVBUF_PATTERN_GEN_SELECT

#define XAVBUF_PLL_CFG 0X00000024

The following constants define values to manipulate the bits of the PLL config register.

#define XAVBUF_PLL_CTRL 0X00000020

The following constants define values to manipulate the bits of the VPLL control register.

#define XAVBUF_PLL_FRAC_CFG 0X00000028

The following constants define values to manipulate the bits of the VPLL fractional config register.

#define XAVBUF_PLL_STATUS 0X00000044

The following constants define values to manipulate the bits of the PLL STATUS register.

#define XAVBUF_Pss_Ref_Clk 0

The following constants define values to Reference clock.

#define XAVBuf_ReadReg	(	BaseAddress,
		RegOffset
	)	XAVBuf_In32((BaseAddress) + (RegOffset))

This is a low-level function that reads from the specified register.

Parameters

BaseAddress	is the base address of the device.
RegOffset	is the register offset to be read from.

Returns: The 32-bit value of the specified register.

Note: C-style signature: u32 XAVBuf_ReadReg(u32 BaseAddress, u32 RegOffset)

Referenced by XABuf_LineResetDisable(), XAVBuf_AudioSoftReset(), XAVBuf_InputAudioSelect(), XAVBuf_InputVideoSelect(), XAVBuf_SetAudioClock(), and XAVBuf_SetPixelClock().

#define XAVBUF_V_BLEND_BG_CLR_0 0X0000A000

Register: XAVBUF_V_BLEND_BG_CLR_0

Referenced by XAVBuf_BlendSetBgColor().

#define XAVBUF_V_BLEND_BG_CLR_1 0X0000A004

Register: XAVBUF_V_BLEND_BG_CLR_1

Referenced by XAVBuf_BlendSetBgColor().

#define XAVBUF_V_BLEND_BG_CLR_2 0X0000A008

Register: XAVBUF_V_BLEND_BG_CLR_2

Referenced by XAVBuf_BlendSetBgColor().

#define XAVBUF_V_BLEND_CB_IN1CSC_OFFSET 0X0000A070

Register: XAVBUF_V_BLEND_CB_IN1CSC_OFFSET

#define XAVBUF_V_BLEND_CB_IN2CSC_OFFSET 0X0000A0AC

Register: XAVBUF_V_BLEND_CB_IN2CSC_OFFSET

#define XAVBUF_V_BLEND_CB_OUTCSC_OFFSET 0X0000A07C

Register: XAVBUF_V_BLEND_CB_OUTCSC_OFFSET

#define XAVBUF_V_BLEND_CHROMA_KEY_COMP1 0X0000A1D4

Register: XAVBUF_V_BLEND_CHROMA_KEY_COMP1

#define XAVBUF_V_BLEND_CHROMA_KEY_COMP2 0X0000A1D8

Register: XAVBUF_V_BLEND_CHROMA_KEY_COMP2

#define XAVBUF_V_BLEND_CHROMA_KEY_COMP3 0X0000A1DC

Register: XAVBUF_V_BLEND_CHROMA_KEY_COMP3

#define XAVBUF_V_BLEND_CHROMA_KEY_ENABLE 0X0000A1D0

Register: XAVBUF_V_BLEND_CHROMA_KEY_ENABLE

#define XAVBUF_V_BLEND_CR_IN1CSC_OFFSET 0X0000A06C

Register: XAVBUF_V_BLEND_CR_IN1CSC_OFFSET

#define XAVBUF_V_BLEND_CR_IN2CSC_OFFSET 0X0000A0A8

Register: XAVBUF_V_BLEND_CR_IN2CSC_OFFSET

#define XAVBUF_V_BLEND_CR_OUTCSC_OFFSET 0X0000A078

Register: XAVBUF_V_BLEND_CR_OUTCSC_OFFSET

#define XAVBUF_V_BLEND_IN1CSC_COEFF0 0X0000A044

Register: XAVBUF_V_BLEND_IN1CSC_COEFF0

#define XAVBUF_V_BLEND_IN1CSC_COEFF1 0X0000A048

Register: XAVBUF_V_BLEND_IN1CSC_COEFF1

#define XAVBUF_V_BLEND_IN1CSC_COEFF2 0X0000A04C

Register: XAVBUF_V_BLEND_IN1CSC_COEFF2

#define XAVBUF_V_BLEND_IN1CSC_COEFF3 0X0000A050

Register: XAVBUF_V_BLEND_IN1CSC_COEFF3

#define XAVBUF_V_BLEND_IN1CSC_COEFF4 0X0000A054

Register: XAVBUF_V_BLEND_IN1CSC_COEFF4

#define XAVBUF_V_BLEND_IN1CSC_COEFF5 0X0000A058

Register: XAVBUF_V_BLEND_IN1CSC_COEFF5

#define XAVBUF_V_BLEND_IN1CSC_COEFF6 0X0000A05C

Register: XAVBUF_V_BLEND_IN1CSC_COEFF6

#define XAVBUF_V_BLEND_IN1CSC_COEFF7 0X0000A060

Register: XAVBUF_V_BLEND_IN1CSC_COEFF7

#define XAVBUF_V_BLEND_IN1CSC_COEFF8 0X0000A064

Register: XAVBUF_V_BLEND_IN1CSC_COEFF8

#define XAVBUF_V_BLEND_IN2CSC_COEFF0 0X0000A080

Register: XAVBUF_V_BLEND_IN2CSC_COEFF0

#define XAVBUF_V_BLEND_IN2CSC_COEFF1 0X0000A084

Register: XAVBUF_V_BLEND_IN2CSC_COEFF1

#define XAVBUF_V_BLEND_IN2CSC_COEFF2 0X0000A088

Register: XAVBUF_V_BLEND_IN2CSC_COEFF2

#define XAVBUF_V_BLEND_IN2CSC_COEFF3 0X0000A08C

Register: XAVBUF_V_BLEND_IN2CSC_COEFF3

#define XAVBUF_V_BLEND_IN2CSC_COEFF4 0X0000A090

Register: XAVBUF_V_BLEND_IN2CSC_COEFF4

#define XAVBUF_V_BLEND_IN2CSC_COEFF5 0X0000A094

Register: XAVBUF_V_BLEND_IN2CSC_COEFF5

#define XAVBUF_V_BLEND_IN2CSC_COEFF6 0X0000A098

Register: XAVBUF_V_BLEND_IN2CSC_COEFF6

#define XAVBUF_V_BLEND_IN2CSC_COEFF7 0X0000A09C

Register: XAVBUF_V_BLEND_IN2CSC_COEFF7

#define XAVBUF_V_BLEND_IN2CSC_COEFF8 0X0000A0A0

Register: XAVBUF_V_BLEND_IN2CSC_COEFF8

#define XAVBUF_V_BLEND_LAYER0_CONTROL 0X0000A018

Register: XAVBUF_V_BLEND_LAYER0_CONTROL

#define XAVBUF_V_BLEND_LAYER1_CONTROL 0X0000A01C

Register: XAVBUF_V_BLEND_LAYER1_CONTROL

#define XAVBUF_V_BLEND_LUMA_IN1CSC_OFFSET 0X0000A068

Register: XAVBUF_V_BLEND_LUMA_IN1CSC_OFFSET

#define XAVBUF_V_BLEND_LUMA_IN2CSC_OFFSET 0X0000A0A4

Register: XAVBUF_V_BLEND_LUMA_IN2CSC_OFFSET

#define XAVBUF_V_BLEND_LUMA_OUTCSC_OFFSET 0X0000A074

Register: XAVBUF_V_BLEND_LUMA_OUTCSC_OFFSET

#define XAVBUF_V_BLEND_OUTPUT_VID_FORMAT 0X0000A014

Register: XAVBUF_V_BLEND_OUTPUT_VID_FORMAT

Referenced by XAVBuf_ConfigureOutputVideo().

#define XAVBUF_V_BLEND_RGB2YCBCR_COEFF0 0X0000A020

Register: XAVBUF_V_BLEND_RGB2YCBCR_COEFF0

#define XAVBUF_V_BLEND_RGB2YCBCR_COEFF1 0X0000A024

Register: XAVBUF_V_BLEND_RGB2YCBCR_COEFF1

#define XAVBUF_V_BLEND_RGB2YCBCR_COEFF2 0X0000A028

Register: XAVBUF_V_BLEND_RGB2YCBCR_COEFF2

#define XAVBUF_V_BLEND_RGB2YCBCR_COEFF3 0X0000A02C

Register: XAVBUF_V_BLEND_RGB2YCBCR_COEFF3

#define XAVBUF_V_BLEND_RGB2YCBCR_COEFF4 0X0000A030

Register: XAVBUF_V_BLEND_RGB2YCBCR_COEFF4

#define XAVBUF_V_BLEND_RGB2YCBCR_COEFF5 0X0000A034

Register: XAVBUF_V_BLEND_RGB2YCBCR_COEFF5

#define XAVBUF_V_BLEND_RGB2YCBCR_COEFF6 0X0000A038

Register: XAVBUF_V_BLEND_RGB2YCBCR_COEFF6

#define XAVBUF_V_BLEND_RGB2YCBCR_COEFF7 0X0000A03C

Register: XAVBUF_V_BLEND_RGB2YCBCR_COEFF7

#define XAVBUF_V_BLEND_RGB2YCBCR_COEFF8 0X0000A040

Register: XAVBUF_V_BLEND_RGB2YCBCR_COEFF8

#define XAVBUF_V_BLEND_SET_GLOBAL_ALPHA_REG 0X0000A00C

Register: XAVBUF_V_BLEND_SET_GLOBAL_ALPHA_REG

Referenced by XAVBuf_SetBlenderAlpha().

#define XAVBUF_VIDEO_REF_CTRL 0X00000070

The following constants define values to manipulate the bits of the VIDEO reference control register.

Referenced by XAVBuf_SetPixelClock().

#define XAVBUF_VPLL_SRC_SEL 0

The following constants define values available PLL source to Audio and Video.

Referenced by XAVBuf_SetAudioClock(), and XAVBuf_SetPixelClock().

#define XAVBuf_WriteReg	(	BaseAddress,
		RegOffset,
		Data
	)	XAVBuf_Out32((BaseAddress) + (RegOffset), (Data))

This is a low-level function that writes to the specified register.

Parameters

BaseAddress	is the base address of the device.
RegOffset	is the register offset to write to.
Data	is the 32-bit data to write to the specified register.

Returns: None.

Note: C-style signature: void XAVBuf_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)

Referenced by XABuf_LineResetDisable(), XAVBuf_AudioMixerVolumeControl(), XAVBuf_AudioSoftReset(), XAVBuf_BlendSetBgColor(), XAVBuf_ConfigureOutputVideo(), XAVBuf_EnableAudio0Buffers(), XAVBuf_EnableAudio1Buffers(), XAVBuf_EnableGraphicsBuffers(), XAVBuf_EnableVideoBuffers(), XAVBuf_Initialize(), XAVBuf_InputAudioSelect(), XAVBuf_InputVideoSelect(), XAVBuf_SetAudioVideoClkSrc(), XAVBuf_SetBlenderAlpha(), and XAVBuf_SoftReset().