Overview

This file demonstrates how to use xaxicdma driver on the Xilinx AXI CDMA core (AXICDMA) to transfer packets in hybrid transfer mode through interrupt.

This example does one simple transfer, then a multiple BD transfer, and finally another simple transfer.

Modify NUMBER_OF_BDS_TO_TRANSFER for a different number of BDs to be transferred in the SG transfer.

This example assumes that the system has an interrupt controller.

To see the debug print, you need a Uart16550 or uartlite in your system, and please set "-DDEBUG" in your compiler options for the example, also comment out the "#undef DEBUG" in xdebug.h. You need to rebuild your software executable.

Make sure that MEMORY_BASE is defined properly as per the HW system and the transfer length should be cache-line size aligned.

MODIFICATION HISTORY:

Ver   Who  Date     Changes



1.00a jz   07/30/10 First release
2.01a rkv  02/01/11 Changed function prototype of XAxiCdma_HybridIntrExample
                       to a function taking arguments interrupt instance,device
                       instance,device id,device interrupt id
               Added interrupt support for Cortex A9
2.01a srt  03/06/12 Modified interrupt support for Zynq.
               Added V7 DDR Base Address to fix CR 649405.
                       Modified Flushing and Invalidation of Caches to fix CRs
               648103, 648701.
2.02a srt  03/01/13 Updated DDR base address for IPI designs (CR 703656).
4.1   adk  01/07/16 Updated DDR base address for Ultrascale (CR 799532) and
               removed the defines for S6/V6.
4.3   ms   01/22/17 Modified xil_printf statement in main function to
           ensure that "Successfully ran" and "Failed" strings are
           available in all examples. This is a fix for CR-965028.
      ms   04/05/17 Modified Comment lines in functions to
                    recognize it as documentation block for doxygen
                    generation of examples.
4.4   rsp  02/22/18 Support data buffers above 4GB.Use UINTPTR for storing
                    and typecasting buffer address(CR-995116).
4.8   sk   06/15/20 Fix the compilation error for xreg_cortexa9.h
               preprocessor.
4.8      sk   09/30/20 Modify the buffer length and add cache operations for
               receive and destination buffers to fix the data check
               failure and to make the length cache-line aligned.
4.10  sa   08/12/22 Updated the example to use latest MIG cannoical define
                       i.e XPAR_MIG_0_C0_DDR4_MEMORY_MAP_BASEADDR.
4.11     sa   09/29/22 Fix infinite loops in the example.

Functions
int	XAxiCdma_HybridIntrExample (XScuGic IntcInstancePtr, XAxiCdma InstancePtr, u16 DeviceId, u32 IntrId)
	The example to do hybrid transfers through interrupt. More...

int	main (void)
	The entry point for this example. More...

Function Documentation

int main ( void )

The entry point for this example.

It sets up uart16550 if one is available, invokes the example function, and reports the execution status.

Parameters

None

Returns

XST_SUCCESS if example finishes successfully
XST_FAILURE if example fails.

Note: None

References XAxiCdma_HybridIntrExample().

int XAxiCdma_HybridIntrExample	(	XScuGic *	IntcInstancePtr,
		XAxiCdma *	InstancePtr,
		u16	DeviceId,
		u32	IntrId
	)

The example to do hybrid transfers through interrupt.

It does the following transfers: a simple transfer a multiple BD scatter gather transfer another simple transfer

Parameters

IntcInstancePtr	is a pointer to the INTC instance
InstancePtr	is a pointer to the XAxiCdma instance
DeviceId	is the Device Id of the XAxiCdma instance
IntrId	is the interrupt Id for the XAxiCdma instance in build

Returns

XST_SUCCESS if example finishes successfully
XST_FAILURE if error occurs

Note: If the hardware build has problems with interrupt, then this function hangs

References XAxiCdma_CfgInitialize(), XAxiCdma_IntrEnable(), XAxiCdma_LookupConfig(), and XAXICDMA_XR_IRQ_ALL_MASK.

Referenced by main().

Overview

Functions

Function Documentation