Overview

This file demonstrates how to use the xaxidma driver on the Xilinx AXI DMA core (AXIDMA) to transfer packets.in interrupt mode when the AXIDMA core is configured in simple mode.

This code assumes a loopback hardware widget is connected to the AXI DMA core for data packet loopback.

To see the debug print, you need a Uart16550 or uartlite in your system, and please set "-DDEBUG" in your compiler options. You need to rebuild your software executable.

MODIFICATION HISTORY:

Ver   Who  Date     Changes
----- ---- -------- -------------------------------------------------------
4.00a rkv  02/22/11 New example created for simple DMA, this example is for
               simple DMA,Added interrupt support for Zynq.
4.00a srt  08/04/11 Changed a typo in the RxIntrHandler, changed
               XAXIDMA_DMA_TO_DEVICE to XAXIDMA_DEVICE_TO_DMA
5.00a srt  03/06/12 Added Flushing and Invalidation of Caches to fix CRs
               648103, 648701.
               Added V7 DDR Base Address to fix CR 649405.
6.00a srt  03/27/12 Changed API calls to support MCDMA driver.
7.00a srt  06/18/12 API calls are reverted back for backward compatibility.
7.01a srt  11/02/12 Buffer sizes (Tx and Rx) are modified to meet maximum
               DDR memory limit of the h/w system built with Area mode
7.02a srt  03/01/13 Updated DDR base address for IPI designs (CR 703656).
9.1   adk  01/07/16 Updated DDR base address for Ultrascale (CR 799532) and
               removed the defines for S6/V6.
9.2   vak  15/04/16 Fixed compilation warnings in the example
9.3   ms   01/23/17 Modified xil_printf statement in main function to
                    ensure that "Successfully ran" and "Failed" strings are
                    available in all examples. This is a fix for CR-965028.
9.6   rsp  02/14/18 Support data buffers above 4GB.Use UINTPTR for typecasting
                    buffer address (CR-992638).
9.9   rsp  01/21/19 Fix use of #elif check in deriving DDR_BASE_ADDR.
9.10  rsp  09/17/19 Fix cache maintenance ops for source and dest buffer.
9.14  sk   03/08/22 Delete DDR memory limits comments as they are not
                       relevant to this driver version.
9.15  sa   08/12/22 Updated the example to use latest MIG cannoical define
                       i.e XPAR_MIG_0_C0_DDR4_MEMORY_MAP_BASEADDR.
9.16  sa   09/29/22 Fix infinite loops in the example.

Functions
int	main (void)
	Main function. More...

Function Documentation

int main ( void )

Main function.

This function is the main entry of the interrupt test. It does the following: Set up the output terminal if UART16550 is in the hardware build Initialize the DMA engine Set up Tx and Rx channels Set up the interrupt system for the Tx and Rx interrupts Submit a transfer Wait for the transfer to finish Check transfer status Disable Tx and Rx interrupts Print test status and exit

Parameters

None

Returns

XST_SUCCESS if example finishes successfully
XST_FAILURE if example fails.

Note: None.

References XAxiDma_CfgInitialize(), XAxiDma_HasSg, XAxiDma_IntrDisable, XAxiDma_IntrEnable, XAXIDMA_IRQ_ALL_MASK, XAxiDma_LookupConfig(), and XAxiDma_SimpleTransfer().

Overview

Functions

Function Documentation