axiethernet
Vitis Drivers API Documentation
xaxiethernet_hw.h File Reference

Macros

#define XAxiEthernet_ReadReg(BaseAddress, RegOffset)   (Xil_In32(((BaseAddress) + (RegOffset))))
 XAxiEthernet_ReadReg returns the value read from the register specified by RegOffset. More...
 
#define XAxiEthernet_WriteReg(BaseAddress, RegOffset, Data)   Xil_Out32(((BaseAddress) + (RegOffset)), (Data))
 XAxiEthernet_WriteReg, writes Data to the register specified by RegOffset. More...
 
Axi Ethernet registers offset
#define XAE_RAF_OFFSET   0x00000000
 Reset and Address filter. More...
 
#define XAE_TPF_OFFSET   0x00000004
 Tx Pause Frame. More...
 
#define XAE_IFGP_OFFSET   0x00000008
 Tx Inter-frame gap adjustment. More...
 
#define XAE_IS_OFFSET   0x0000000C
 Interrupt status. More...
 
#define XAE_IP_OFFSET   0x00000010
 Interrupt pending. More...
 
#define XAE_IE_OFFSET   0x00000014
 Interrupt enable. More...
 
#define XAE_TTAG_OFFSET   0x00000018
 Tx VLAN TAG. More...
 
#define XAE_RTAG_OFFSET   0x0000001C
 Rx VLAN TAG. More...
 
#define XAE_UAWL_OFFSET   0x00000020
 Unicast address word lower. More...
 
#define XAE_UAWU_OFFSET   0x00000024
 Unicast address word upper. More...
 
#define XAE_TPID0_OFFSET   0x00000028
 VLAN TPID0 register. More...
 
#define XAE_TPID1_OFFSET   0x0000002C
 VLAN TPID1 register. More...
 
#define XAE_RXBL_OFFSET   0x00000200
 Received Bytes, LSW. More...
 
#define XAE_RXBU_OFFSET   0x00000204
 Received Bytes, MSW. More...
 
#define XAE_TXBL_OFFSET   0x00000208
 Transmitted Bytes, LSW. More...
 
#define XAE_TXBU_OFFSET   0x0000020C
 Transmitted Bytes, MSW. More...
 
#define XAE_RXUNDRL_OFFSET   0x00000210
 Count of undersize(less than 64 bytes) frames received, LSW. More...
 
#define XAE_RXUNDRU_OFFSET   0x00000214
 Count of undersize(less than 64 bytes) frames received, MSW. More...
 
#define XAE_RXFRAGL_OFFSET   0x00000218
 Count of undersized(less than 64 bytes) and bad FCS frames received, LSW. More...
 
#define XAE_RXFRAGU_OFFSET   0x0000021C
 Count of undersized(less than 64 bytes) and bad FCS frames received, MSW. More...
 
#define XAE_RX64BL_OFFSET   0x00000220
 Count of 64 bytes frames received, LSW. More...
 
#define XAE_RX64BU_OFFSET   0x00000224
 Count of 64 bytes frames received, MSW. More...
 
#define XAE_RX65B127L_OFFSET   0x00000228
 Count of 65-127 bytes Frames received, LSW. More...
 
#define XAE_RX65B127U_OFFSET   0x0000022C
 Count of 65-127 bytes Frames received, MSW. More...
 
#define XAE_RX128B255L_OFFSET   0x00000230
 Count of 128-255 bytes Frames received, LSW. More...
 
#define XAE_RX128B255U_OFFSET   0x00000234
 Count of 128-255 bytes frames received, MSW. More...
 
#define XAE_RX256B511L_OFFSET   0x00000238
 Count of 256-511 bytes Frames received, LSW. More...
 
#define XAE_RX256B511U_OFFSET   0x0000023C
 Count of 256-511 bytes frames received, MSW. More...
 
#define XAE_RX512B1023L_OFFSET   0x00000240
 Count of 512-1023 bytes frames received, LSW. More...
 
#define XAE_RX512B1023U_OFFSET   0x00000244
 Count of 512-1023 bytes frames received, MSW. More...
 
#define XAE_RX1024BL_OFFSET   0x00000248
 Count of 1024-MAX bytes frames received, LSW. More...
 
#define XAE_RX1024BU_OFFSET   0x0000024C
 Count of 1024-MAX bytes frames received, MSW. More...
 
#define XAE_RXOVRL_OFFSET   0x00000250
 Count of oversize frames received, LSW. More...
 
#define XAE_RXOVRU_OFFSET   0x00000254
 Count of oversize frames received, MSW. More...
 
#define XAE_TX64BL_OFFSET   0x00000258
 Count of 64 bytes frames transmitted, LSW. More...
 
#define XAE_TX64BU_OFFSET   0x0000025C
 Count of 64 bytes frames transmitted, MSW. More...
 
#define XAE_TX65B127L_OFFSET   0x00000260
 Count of 65-127 bytes frames transmitted, LSW. More...
 
#define XAE_TX65B127U_OFFSET   0x00000264
 Count of 65-127 bytes frames transmitted, MSW. More...
 
#define XAE_TX128B255L_OFFSET   0x00000268
 Count of 128-255 bytes frames transmitted, LSW. More...
 
#define XAE_TX128B255U_OFFSET   0x0000026C
 Count of 128-255 bytes frames transmitted, MSW. More...
 
#define XAE_TX256B511L_OFFSET   0x00000270
 Count of 256-511 bytes frames transmitted, LSW. More...
 
#define XAE_TX256B511U_OFFSET   0x00000274
 Count of 256-511 bytes frames transmitted, MSW. More...
 
#define XAE_TX512B1023L_OFFSET   0x00000278
 Count of 512-1023 bytes frames transmitted, LSW. More...
 
#define XAE_TX512B1023U_OFFSET   0x0000027C
 Count of 512-1023 bytes frames transmitted, MSW. More...
 
#define XAE_TX1024L_OFFSET   0x00000280
 Count of 1024-MAX bytes frames transmitted, LSW. More...
 
#define XAE_TX1024U_OFFSET   0x00000284
 Count of 1024-MAX bytes frames transmitted, MSW. More...
 
#define XAE_TXOVRL_OFFSET   0x00000288
 Count of oversize frames transmitted, LSW. More...
 
#define XAE_TXOVRU_OFFSET   0x0000028C
 Count of oversize frames transmitted, MSW. More...
 
#define XAE_RXFL_OFFSET   0x00000290
 Count of frames received OK, LSW. More...
 
#define XAE_RXFU_OFFSET   0x00000294
 Count of frames received OK, MSW. More...
 
#define XAE_RXFCSERL_OFFSET   0x00000298
 Count of frames received with FCS error and at least 64 bytes, LSW. More...
 
#define XAE_RXFCSERU_OFFSET   0x0000029C
 Count of frames received with FCS error and at least 64 bytes,MSW. More...
 
#define XAE_RXBCSTFL_OFFSET   0x000002A0
 Count of broadcast frames received, LSW. More...
 
#define XAE_RXBCSTFU_OFFSET   0x000002A4
 Count of broadcast frames received, MSW. More...
 
#define XAE_RXMCSTFL_OFFSET   0x000002A8
 Count of multicast frames received, LSW. More...
 
#define XAE_RXMCSTFU_OFFSET   0x000002AC
 Count of multicast frames received, MSW. More...
 
#define XAE_RXCTRFL_OFFSET   0x000002B0
 Count of control frames received, LSW. More...
 
#define XAE_RXCTRFU_OFFSET   0x000002B4
 Count of control frames received, MSW. More...
 
#define XAE_RXLTERL_OFFSET   0x000002B8
 Count of frames received with length error, LSW. More...
 
#define XAE_RXLTERU_OFFSET   0x000002BC
 Count of frames received with length error, MSW. More...
 
#define XAE_RXVLANFL_OFFSET   0x000002C0
 Count of VLAN tagged frames received, LSW. More...
 
#define XAE_RXVLANFU_OFFSET   0x000002C4
 Count of VLAN tagged frames received, MSW. More...
 
#define XAE_RXPFL_OFFSET   0x000002C8
 Count of pause frames received, LSW. More...
 
#define XAE_RXPFU_OFFSET   0x000002CC
 Count of pause frames received, MSW. More...
 
#define XAE_RXUOPFL_OFFSET   0x000002D0
 Count of control frames received with unsupported opcode, LSW. More...
 
#define XAE_RXUOPFU_OFFSET   0x000002D4
 Count of control frames received with unsupported opcode, MSW. More...
 
#define XAE_TXFL_OFFSET   0x000002D8
 Count of frames transmitted OK, LSW. More...
 
#define XAE_TXFU_OFFSET   0x000002DC
 Count of frames transmitted OK, MSW. More...
 
#define XAE_TXBCSTFL_OFFSET   0x000002E0
 Count of broadcast frames transmitted OK, LSW. More...
 
#define XAE_TXBCSTFU_OFFSET   0x000002E4
 Count of broadcast frames transmitted, MSW. More...
 
#define XAE_TXMCSTFL_OFFSET   0x000002E8
 Count of multicast frames transmitted, LSW. More...
 
#define XAE_TXMCSTFU_OFFSET   0x000002EC
 Count of multicast frames transmitted, MSW. More...
 
#define XAE_TXUNDRERL_OFFSET   0x000002F0
 Count of frames transmitted underrun error, LSW. More...
 
#define XAE_TXUNDRERU_OFFSET   0x000002F4
 Count of frames transmitted underrun error, MSW. More...
 
#define XAE_TXCTRFL_OFFSET   0x000002F8
 Count of control frames transmitted, LSW. More...
 
#define XAE_TXCTRFU_OFFSET   0x000002FC
 Count of control frames, transmitted, MSW. More...
 
#define XAE_TXVLANFL_OFFSET   0x00000300
 Count of VLAN tagged frames transmitted, LSW. More...
 
#define XAE_TXVLANFU_OFFSET   0x00000304
 Count of VLAN tagged frames transmitted, MSW. More...
 
#define XAE_TXPFL_OFFSET   0x00000308
 Count of pause frames transmitted, LSW. More...
 
#define XAE_TXPFU_OFFSET   0x0000030C
 Count of pause frames transmitted, MSW. More...
 
#define XAE_TXSCL_OFFSET   0x00000310
 Single Collision Frames Transmitted OK, LSW. More...
 
#define XAE_TXSCU_OFFSET   0x00000314
 Single Collision Frames Transmitted OK, MSW. More...
 
#define XAE_TXMCL_OFFSET   0x00000318
 Multiple Collision Frames Transmitted OK, LSW. More...
 
#define XAE_TXMCU_OFFSET   0x0000031C
 Multiple Collision Frames Transmitted OK, MSW. More...
 
#define XAE_TXDEFL_OFFSET   0x00000320
 Deferred Tx Frames, LSW. More...
 
#define XAE_TXDEFU_OFFSET   0x00000324
 Deferred Tx Frames, MSW. More...
 
#define XAE_TXLTCL_OFFSET   0x00000328
 Frames transmitted with late Collisions, LSW. More...
 
#define XAE_TXLTCU_OFFSET   0x0000032C
 Frames transmitted with late Collisions, MSW. More...
 
#define XAE_TXAECL_OFFSET   0x00000330
 Frames aborted with excessive Collisions, LSW. More...
 
#define XAE_TXAECU_OFFSET   0x00000334
 Frames aborted with excessive Collisions, MSW. More...
 
#define XAE_TXEDEFL_OFFSET   0x00000338
 Transmit Frames with excessive Defferal, LSW. More...
 
#define XAE_TXEDEFU_OFFSET   0x0000033C
 Transmit Frames with excessive Defferal, MSW. More...
 
#define XAE_RXAERL_OFFSET   0x00000340
 Frames received with alignment errors, LSW. More...
 
#define XAE_RXAERU_OFFSET   0x0000034C
 Frames received with alignment errors, MSW. More...
 
#define XAE_RCW0_OFFSET   0x00000400
 Rx Configuration Word 0. More...
 
#define XAE_RCW1_OFFSET   0x00000404
 Rx Configuration Word 1. More...
 
#define XAE_TC_OFFSET   0x00000408
 Tx Configuration. More...
 
#define XAE_FCC_OFFSET   0x0000040C
 Flow Control Configuration. More...
 
#define XAE_EMMC_OFFSET   0x00000410
 EMAC mode configuration. More...
 
#define XAE_RXFC_OFFSET   0x00000414
 Rx Max Frm Config Register. More...
 
#define XAE_TXFC_OFFSET   0x00000418
 Tx Max Frm Config Register. More...
 
#define XAE_TX_TIMESTAMP_ADJ_OFFSET   0x0000041C
 Transmitter time stamp adjust control Register. More...
 
#define XAE_PHYC_OFFSET   0x00000420
 RGMII/SGMII configuration. More...
 
#define XAE_IDREG_OFFSET   0x000004F8
 Identification Register. More...
 
#define XAE_ARREG_OFFSET   0x000004FC
 Ability Register. More...
 
#define XAE_MDIO_MC_OFFSET   0x00000500
 MII Management Config. More...
 
#define XAE_MDIO_MCR_OFFSET   0x00000504
 MII Management Control. More...
 
#define XAE_MDIO_MWD_OFFSET   0x00000508
 MII Management Write Data. More...
 
#define XAE_MDIO_MRD_OFFSET   0x0000050C
 MII Management Read Data. More...
 
#define XAE_MDIO_MIS_OFFSET   0x00000600
 MII Management Interrupt Status. More...
 
#define XAE_MDIO_MIP_OFFSET   0x00000620
 MII Management Interrupt Pending register offse. More...
 
#define XAE_MDIO_MIE_OFFSET   0x00000640
 MII Management Interrupt Enable register offset. More...
 
#define XAE_MDIO_MIC_OFFSET   0x00000660
 MII Management Interrupt Clear register offset. More...
 
#define XAE_UAW0_OFFSET   0x00000700
 Unicast address word 0. More...
 
#define XAE_UAW1_OFFSET   0x00000704
 Unicast address word 1. More...
 
#define XAE_FMI_OFFSET   0x00000708
 Filter Mask Index. More...
 
#define XAE_AF0_OFFSET   0x00000710
 Address Filter 0. More...
 
#define XAE_AF1_OFFSET   0x00000714
 Address Filter 1. More...
 
#define XAE_TX_VLAN_DATA_OFFSET   0x00004000
 TX VLAN data table address. More...
 
#define XAE_RX_VLAN_DATA_OFFSET   0x00008000
 RX VLAN data table address. More...
 
#define XAE_MCAST_TABLE_OFFSET   0x00020000
 Multicast table address. More...
 
Reset and Address Filter (RAF) Register bit definitions.

These bits are associated with the XAE_RAF_OFFSET register.

#define XAE_RAF_MCSTREJ_MASK   0x00000002
 Reject receive multicast destination address. More...
 
#define XAE_RAF_BCSTREJ_MASK   0x00000004
 Reject receive broadcast destination address. More...
 
#define XAE_RAF_TXVTAGMODE_MASK   0x00000018
 Tx VLAN TAG mode. More...
 
#define XAE_RAF_RXVTAGMODE_MASK   0x00000060
 Rx VLAN TAG mode. More...
 
#define XAE_RAF_TXVSTRPMODE_MASK   0x00000180
 Tx VLAN STRIP mode. More...
 
#define XAE_RAF_RXVSTRPMODE_MASK   0x00000600
 Rx VLAN STRIP mode. More...
 
#define XAE_RAF_NEWFNCENBL_MASK   0x00000800
 New function mode. More...
 
#define XAE_RAF_EMULTIFLTRENBL_MASK   0x00001000
 Extended Multicast Filtering mode. More...
 
#define XAE_RAF_STATSRST_MASK   0x00002000
 Statistics Counter Reset. More...
 
#define XAE_RAF_RXBADFRMEN_MASK   0x00004000
 Receive Bad Frame Enable. More...
 
#define XAE_RAF_TXVTAGMODE_SHIFT   3
 Tx Tag mode shift bits. More...
 
#define XAE_RAF_RXVTAGMODE_SHIFT   5
 Rx Tag mode shift bits. More...
 
#define XAE_RAF_TXVSTRPMODE_SHIFT   7
 Tx strip mode shift bits. More...
 
#define XAE_RAF_RXVSTRPMODE_SHIFT   9
 Rx Strip mode shift bits. More...
 
Transmit Pause Frame Register (TPF) bit definitions
#define XAE_TPF_TPFV_MASK   0x0000FFFF
 Tx pause frame value. More...
 
Transmit Inter-Frame Gap Adjustment Register (TFGP) bit definitions
#define XAE_TFGP_IFGP_MASK   0x0000007F
 Transmit inter-frame gap adjustment value. More...
 
Interrupt Status/Enable/Mask Registers bit definitions

The bit definition of these three interrupt registers are the same.

These bits are associated with the XAE_IS_OFFSET, XAE_IP_OFFSET, and XAE_IE_OFFSET registers.

#define XAE_INT_HARDACSCMPLT_MASK   0x00000001
 Hard register access complete. More...
 
#define XAE_INT_AUTONEG_MASK   0x00000002
 Auto negotiation complete. More...
 
#define XAE_INT_RXCMPIT_MASK   0x00000004
 Rx complete. More...
 
#define XAE_INT_RXRJECT_MASK   0x00000008
 Rx frame rejected. More...
 
#define XAE_INT_RXFIFOOVR_MASK   0x00000010
 Rx fifo overrun. More...
 
#define XAE_INT_TXCMPIT_MASK   0x00000020
 Tx complete. More...
 
#define XAE_INT_RXDCMLOCK_MASK   0x00000040
 Rx Dcm Lock. More...
 
#define XAE_INT_MGTRDY_MASK   0x00000080
 MGT clock Lock. More...
 
#define XAE_INT_PHYRSTCMPLT_MASK   0x00000100
 Phy Reset complete. More...
 
#define XAE_INT_ALL_MASK   0x0000003F
 All the ints. More...
 
#define XAE_INT_RECV_ERROR_MASK   (XAE_INT_RXRJECT_MASK | XAE_INT_RXFIFOOVR_MASK)
 INT bits that indicate receive errors. More...
 
TPID Register (TPID) bit definitions
#define XAE_TPID_0_MASK   0x0000FFFF
 TPID 0. More...
 
#define XAE_TPID_1_MASK   0xFFFF0000
 TPID 1. More...
 
Receive Configuration Word 1 (RCW1) Register bit definitions
#define XAE_RCW1_RST_MASK   0x80000000
 Reset. More...
 
#define XAE_RCW1_JUM_MASK   0x40000000
 Jumbo frame enable. More...
 
#define XAE_RCW1_FCS_MASK   0x20000000
 In-Band FCS enable (FCS not stripped) More...
 
#define XAE_RCW1_RX_MASK   0x10000000
 Receiver enable. More...
 
#define XAE_RCW1_VLAN_MASK   0x08000000
 VLAN frame enable. More...
 
#define XAE_RCW1_LT_DIS_MASK   0x02000000
 Length/type field valid check disable. More...
 
#define XAE_RCW1_CL_DIS_MASK   0x01000000
 Control frame Length check disable. More...
 
#define XAE_RCW1_1588_TIMESTAMP_EN_MASK   0x00400000
 Inband 1588 time stamp enable. More...
 
#define XAE_RCW1_PAUSEADDR_MASK   0x0000FFFF
 Pause frame source address bits [47:32].Bits [31:0] are stored in register RCW0. More...
 
Transmitter Configuration (TC) Register bit definitions
#define XAE_TC_RST_MASK   0x80000000
 Reset. More...
 
#define XAE_TC_JUM_MASK   0x40000000
 Jumbo frame enable. More...
 
#define XAE_TC_FCS_MASK   0x20000000
 In-Band FCS enable (FCS not generated) More...
 
#define XAE_TC_TX_MASK   0x10000000
 Transmitter enable. More...
 
#define XAE_TC_VLAN_MASK   0x08000000
 VLAN frame enable. More...
 
#define XAE_TC_IFG_MASK   0x02000000
 Inter-frame gap adjustment enable. More...
 
#define XAE_TC_1588_CMD_EN_MASK   0x00400000
 1588 Cmd field enable More...
 
Flow Control Configuration (FCC) Register Bit definitions
#define XAE_FCC_FCRX_MASK   0x20000000
 Rx flow control enable. More...
 
#define XAE_FCC_FCTX_MASK   0x40000000
 Tx flow control enable. More...
 
Ethernet MAC Mode Configuration (EMMC) Register bit definitions
#define XAE_EMMC_LINKSPEED_MASK   0xC0000000
 Link speed. More...
 
#define XAE_EMMC_RGMII_MASK   0x20000000
 RGMII mode enable. More...
 
#define XAE_EMMC_SGMII_MASK   0x10000000
 SGMII mode enable. More...
 
#define XAE_EMMC_GPCS_MASK   0x08000000
 1000BaseX mode enable More...
 
#define XAE_EMMC_HOST_MASK   0x04000000
 Host interface enable. More...
 
#define XAE_EMMC_TX16BIT   0x02000000
 16 bit Tx client enable More...
 
#define XAE_EMMC_RX16BIT   0x01000000
 16 bit Rx client enable More...
 
#define XAE_EMMC_LINKSPD_10   0x00000000
 Link Speed mask for 10 Mbit. More...
 
#define XAE_EMMC_LINKSPD_100   0x40000000
 Link Speed mask for 100 Mbit. More...
 
#define XAE_EMMC_LINKSPD_1000   0x80000000
 Link Speed mask for 1000 Mbit. More...
 
RGMII/SGMII Configuration (PHYC) Register bit definitions
#define XAE_PHYC_SGMIILINKSPEED_MASK   0xC0000000
 SGMII link speed mask. More...
 
#define XAE_PHYC_RGMIILINKSPEED_MASK   0x0000000C
 RGMII link speed. More...
 
#define XAE_PHYC_RGMIIHD_MASK   0x00000002
 RGMII Half-duplex. More...
 
#define XAE_PHYC_RGMIILINK_MASK   0x00000001
 RGMII link status. More...
 
#define XAE_PHYC_RGLINKSPD_10   0x00000000
 RGMII link 10 Mbit. More...
 
#define XAE_PHYC_RGLINKSPD_100   0x00000004
 RGMII link 100 Mbit. More...
 
#define XAE_PHYC_RGLINKSPD_1000   0x00000008
 RGMII link 1000 Mbit. More...
 
#define XAE_PHYC_SGLINKSPD_10   0x00000000
 SGMII link 10 Mbit. More...
 
#define XAE_PHYC_SGLINKSPD_100   0x40000000
 SGMII link 100 Mbit. More...
 
#define XAE_PHYC_SGLINKSPD_1000   0x80000000
 SGMII link 1000 Mbit. More...
 
MDIO Management Configuration (MC) Register bit definitions
#define XAE_MDIO_MC_MDIOEN_MASK   0x00000040
 MII management enable. More...
 
#define XAE_MDIO_MC_CLOCK_DIVIDE_MAX   0x3F
 Maximum MDIO divisor. More...
 
MDIO Management Control Register (MCR) Register bit definitions
#define XAE_MDIO_MCR_PHYAD_MASK   0x1F000000
 Phy Address Mask. More...
 
#define XAE_MDIO_MCR_PHYAD_SHIFT   24
 Phy Address Shift. More...
 
#define XAE_MDIO_MCR_REGAD_MASK   0x001F0000
 Reg Address Mask. More...
 
#define XAE_MDIO_MCR_REGAD_SHIFT   16
 Reg Address Shift. More...
 
#define XAE_MDIO_MCR_OP_MASK   0x0000C000
 Operation Code Mask. More...
 
#define XAE_MDIO_MCR_OP_SHIFT   13
 Operation Code Shift. More...
 
#define XAE_MDIO_MCR_OP_READ_MASK   0x00008000
 Op Code Read Mask. More...
 
#define XAE_MDIO_MCR_OP_WRITE_MASK   0x00004000
 Op Code Write Mask. More...
 
#define XAE_MDIO_MCR_INITIATE_MASK   0x00000800
 Ready Mask. More...
 
#define XAE_MDIO_MCR_READY_MASK   0x00000080
 Ready Mask. More...
 
MDIO Interrupt Enable/Mask/Status Registers bit definitions

The bit definition of these three interrupt registers are the same.

These bits are associated with the XAE_IS_OFFSET, XAE_IP_OFFSET, and XAE_IE_OFFSET registers.

#define XAE_MDIO_INT_MIIM_RDY_MASK   0x00000001
 MIIM Interrupt. More...
 
Axi Ethernet Unicast Address Register Word 1 (UAW1) Register Bit

definitions

#define XAE_UAW1_UNICASTADDR_MASK   0x0000FFFF
 Station address bits [47:32] Station address bits [31:0] are stored in register UAW0. More...
 
Filter Mask Index (FMI) Register bit definitions
#define XAE_FMI_PM_MASK   0x80000000
 Promiscuous mode enable. More...
 
#define XAE_FMI_IND_MASK   0x00000003
 Index Mask. More...
 
Extended multicast buffer descriptor bit mask
#define XAE_BD_RX_USR2_BCAST_MASK   0x00000004
 
#define XAE_BD_RX_USR2_IP_MCAST_MASK   0x00000002
 
#define XAE_BD_RX_USR2_MCAST_MASK   0x00000001
 
Axi Ethernet Multicast Address Register Word 1 (MAW1)
#define XAE_MAW1_RNW_MASK   0x00800000
 Multicast address table register read enable. More...
 
#define XAE_MAW1_ADDR_MASK   0x00030000
 Multicast address table register address. More...
 
#define XAE_MAW1_MULTICADDR_MASK   0x0000FFFF
 Multicast address bits [47:32] Multicast address bits [31:0] are stored in register MAW0. More...
 
#define XAE_MAW1_MATADDR_SHIFT_MASK   16
 Number of bits to shift right to align with XAE_MAW1_CAMADDR_MASK. More...
 
Other Constant definitions used in the driver
#define XAE_SPEED_10_MBPS   10
 Speed of 10 Mbps. More...
 
#define XAE_SPEED_100_MBPS   100
 Speed of 100 Mbps. More...
 
#define XAE_SPEED_1000_MBPS   1000
 Speed of 1000 Mbps. More...
 
#define XAE_SPEED_2500_MBPS   2500
 Speed of 2500 Mbps. More...
 
#define XAE_SOFT_TEMAC_LOW_SPEED   0
 For soft cores with 10/100 Mbps speed. More...
 
#define XAE_SOFT_TEMAC_HIGH_SPEED   1
 For soft cores with 10/100/1000 Mbps speed. More...
 
#define XAE_HARD_TEMAC_TYPE   2
 For hard TEMAC cores used virtex-6. More...
 
#define XAE_PHY_ADDR_LIMIT   31
 Max limit while accessing and searching for available PHYs. More...
 
#define XAE_PHY_REG_NUM_LIMIT   31
 Max register limit in PHY as mandated by the spec. More...
 
#define XAE_RST_DEFAULT_TIMEOUT_VAL   1000000
 Timeout in us used while checking if the core had come out of reset or for the driver API to wait for before returning a failure case. More...
 
#define XAE_VLAN_TABL_STRP_FLD_LEN   1
 Strip field length in vlan table used for extended vlan features. More...
 
#define XAE_VLAN_TABL_TAG_FLD_LEN   1
 Tag field length in vlan table used for extended vlan features. More...
 
#define XAE_MAX_VLAN_TABL_ENTRY   0xFFF
 Max possible number of entries in vlan table used for extended vlan features. More...
 
#define XAE_VLAN_TABL_VID_START_OFFSET   2
 VID field start offset in each entry in the VLAN table. More...
 
#define XAE_VLAN_TABL_STRP_STRT_OFFSET   1
 Strip field start offset in each entry in the VLAN table. More...
 
#define XAE_VLAN_TABL_STRP_ENTRY_MASK   0x01
 Mask used to extract the the strip field from an entry in VLAN table. More...
 
#define XAE_VLAN_TABL_TAG_ENTRY_MASK   0x01
 Mask used to extract the the tag field from an entry in VLAN table. More...