Xilinx Vitis Drivers API Documentation
axipcie Documentation

This file contains the software API definition of the Xilinx AXI PCIe IP (XAxiPcie). This driver provides "C" function interface to application/upper layer to access the hardware.

Features The driver provides its user with entry points

  • To initialize and configure itself and the hardware
  • To access PCIe configuration space locally
  • To enable/disable and to report errors (interrupts).

IP Hardware Configuration The AXI PCIE IP supports only the endpoint for Virtex®-6 and Spartan®-6 families.

The AXI PCIE IP supports both the endpoint and Root Port for the Kintex® 7 devices.

Driver Initialization & Configuration

The XAxiPcie_Config structure is used by the driver to configure itself. This configuration structure is typically created by the tool-chain based on HW build properties.

To support multiple runtime loading and initialization strategies employed by various operating systems, the driver instance can be initialized in the following way:

  • XAxiPcie_LookupConfig(DeviceId) - Use the device identifier to find the static configuration structure defined in xaxipcie_g.c. This is setup by the tools. For some operating systems the config structure will be initialized by the software and this call is not needed.
  • XAxiPcie_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) - Uses a configuration structure provided by the caller. If running in a system with address translation, the provided virtual memory base address replaces the physical address present in the configuration structure.

Interrupt Management

The XAxiPcie driver provides interrupt management functions. It allows the caller to enable/disable each individual interrupt as well as get/clear pending interrupts. Implementation of callback handlers is left to the user.

Ver   Who  Date     Changes

1.00a rkv 03/03/11 Original code. 2.00a nm 10/19/11 Added support of pcie root complex functionality. Changed these functions -renamed function XAxiPcie_GetRequestId to XAxiPcie_GetRequesterId -added two functions arguments RootPortPtr & ECAMSizePtr to XAxiPcie_GetBridgeInfo API Added these new API for root complex support

  • XAxiPcie_GetRootPortStatusCtrl
  • XAxiPcie_SetRootPortStatusCtrl
  • XAxiPcie_SetRootPortMSIBase
  • XAxiPcie_GetRootPortErrFIFOMsg
  • XAxiPcie_ClearRootPortErrFIFOMsg
  • XAxiPcie_GetRootPortIntFIFOReg
  • XAxiPcie_ClearRootPortIntFIFOReg
  • XAxiPcie_WriteLocalConfigSpace
  • XAxiPcie_ComposeExternalConfigAddress
  • XAxiPcie_ReadRemoteConfigSpace
  • XAxiPcie_WriteRemoteConfigSpace
2.01a nm   04/01/12  Removed XAxiPcie_SetRequesterId and
               XAxiPcie_SetBlPortNumber APIs as these are writing
               to Read Only bits for CR638299.
2.02a nm   08/01/12  Updated for removing compilation errors with C++,
               Removed the Endian Swap in
               XAxiPcie_ReadRemoteConfigSpace and
               XAxiPcie_WriteRemoteConfigSpace APIs as the HW
               has been fixed and the swapping is not required
               in  the driver (CR 657412)
2.03a srt  04/13/13  Removed Warnings (CR 705004).
2.04a srt  09/06/13  Fixed CR 734175:
               C_BASEADDR and C_HIGHADDR configuration parameters are
                       renamed to BASEADDR and HIGHADDR in Vivado builds.
                     Modified the tcl for this change.
3.0   adk  19/12/13 Updated as per the New Tcl API's
3.1   sk   11/10/15 Used UINTPTR instead of u32 for Baseaddress CR# 867425.
                    Changed the prototype of XAxiPcie_CfgInitialize API.
      ms   01/23/17 Added xil_printf statement in main function for all
                   examples to ensure that "Successfully ran" and "Failed"
                   strings are available in all examples. This is a fix
                   for CR-965028.
      ms   03/17/17 Added readme.txt file in examples folder for doxygen
      ms   04/05/17 Added tabspace for return statements in functions
                    of axipcie examples for proper documentation while
                    generating doxygen.
3.2     nsk  11/20/19 Added support for axi_pcie3