Xilinx Vitis Drivers API Documentation
clk_wiz Documentation

This is main header file of the Xilinx Clock Wizard driverClock wizard Overview The Clock monitor feature is a part of Clocking Wizard IP. It allows a user to monitor the clock in a given system for clock loss, out of range.In Zynq or Zynq Ultrascale, the clock monitored can be either a PS or a PL clock. In FPGAs, the clock monitored can be an arbitrary clock.

Clock wizard Features

  • Clock Stop – The clock is flat lined.
  • Clock Glitch – Variation in the duty cycle of the clock.
  • Overrun - The number of transitions in the clock are more than expected
  • Underrun - The number of transitions in the clock are less than expected.
  • Overrun and Underrun are termed as “out of range” errors.

Clock Monitor Configurations

  • The GUI in IPI allows for the following configurations
  • Enable 4 User clocks
  • Enable User clock PLL.
  • Select reference clock frequency
  • Select 4 user clock frequencies


Subsystem Driver Usage

Memory Requirement

Interrupt Service

Virtual Memory

This driver supports Virtual Memory. The RTOS is responsible for calculating the correct device base address in Virtual Memory space.


This driver is not thread safe. Any needs for threads or thread mutual exclusion must be satisfied by the layer above this driver.


Asserts are used within all Xilinx drivers to enforce constraints on argument values. Asserts can be turned off on a system-wide basis by defining, at compile time, the NDEBUG identifier. By default, asserts are turned on and it is recommended that application developers leave asserts on during development.

Ver Who Date     Changes

1.0 ram 02/12/16 Initial version for Clock Wizard 1.1 ms 01/23/17 Modified xil_printf statement in main function for all examples to ensure that "Successfully ran" and "Failed" strings are available in all examples. This is a fix for CR-965028. 1.2 ms 03/02/17 Fixed compilation errors in xclk_wiz_intr.c, xclk_wiz_g.c and warnings in xclk_wiz.c files. Fix for CR-970507. ms 03/17/17 Added readme.txt file in examples folder for doxygen generation. 1.3 sd 4/09/20 Added versal support. 1.4 sd 5/22/20 Added zynqmp set rate.