csudma
Xilinx Vitis Drivers API Documentation
csudma Documentation

The CSU_DMA is present inside CSU (Configuration Security Unit) module which is located within the Low-Power Subsystem (LPS) internal to the PS.CSU_DMA allows the CSU to move data efficiently between the memory (32 bit AXI interface) and the CSU stream peripherals (SHA, AES and PCAP) via Secure Stream Switch (SSS).

The CSU_DMA is a 2 channel simple DMA, allowing separate control of the SRC (read) channel and DST (write) channel. The DMA is effectively able to transfer data:

  • From PS-side to the SSS-side (SRC DMA only).
  • From SSS-side to the PS-side (DST DMA only).
  • Simultaneous PS-side to SSS_side and SSS-side to the PS-side.

Initialization & Configuration

The device driver enables higher layer software (e.g., an application) to communicate to the CSU_DMA core.

XCsuDma_CfgInitialize() API is used to initialize the CSU_DMA core. The user needs to first call the XCsuDma_LookupConfig() API which returns the Configuration structure pointer which is passed as a parameter to the XCsuDma_CfgInitialize() API.

Reset This driver will not support handling of CRP PDMA Reset in case of PMCDMA inorder to support multiple level of handoff's. User needs to call the XCsuDma_PmcReset() API before performing any driver operation to make sure PMCDMA is in proper state.

Interrupts This driver will not support handling of interrupts user should write handler to handle the interrupts.

Virtual Memory

This driver supports Virtual Memory. The RTOS is responsible for calculating the correct device base address in Virtual Memory space.

Threads

This driver is not thread safe. Any needs for threads or thread mutual exclusion must be satisfied by the layer above this driver.

Asserts

Asserts are used within all Xilinx drivers to enforce constraints on argument values. Asserts can be turned off on a system-wide basis by defining, at compile time, the NDEBUG identifier. By default, asserts are turned on and it is recommended that users leave asserts on during development.

Building the driver

The XCsuDma driver is composed of several source files. This allows the user to build and link only those parts of the driver that are necessary.

This section contains identifiers and register-level driver functions (or macros), range macros, structure typedefs that can be used to access the Xilinx CSU_DMA core instance.

MODIFICATION HISTORY:
Ver   Who     Date     Changes


1.0 vnsld 22/10/14 First release 1.1 adk 10/05/16 Fixed CR#951040 race condition in the recv path when source and destination points to the same buffer. ms 03/17/17 Added readme.txt file in examples folder for doxygen generation. ms 04/10/17 Modified filename tag in xcsudma_selftest_example.c to include the file in doxygen examples. 1.2 adk 11/22/17 Added peripheral test app support for CSUDMA driver. 1.4 adk 04/12/17 Added support for PMC DMA. adk 09/03/18 Added new API XCsuDma_64BitTransfer() useful for 64-bit dma transfers through PMU processor(CR#996201). adk 25/06/18 Move CRP and PMC Global address defines to xparameters_ps.h file(CR#1002035). adk 08/08/18 Added new API XCsuDma_WaitForDoneTimeout() useful for polling dma transfer done. adk 28/08/18 Fixed misra-c required standard violations.. Rama 02/26/19 Fixed IAR issue by changing "XCsuDma_WaitForDoneTimeout" to function arc 03/26/19 Fixed MISRA-C violations. 1.7 hk 08/03/20 Reorganize transfer function to accommodate all processors and cache functionality. 1.7 sk 08/26/20 Fix MISRA-C violations. 1.8 nsk 12/14/20 Updated the tcl to not to use the instance names. 1.9 sk 02/11/21 Add description for the dmatype macros. 1.9 sk 02/11/21 Remove the prototype of undefined functions. 1.11 sk 03/03/22 Move addtogroup to starting of the file and replace driver version with Overview. 1.11 sk 03/03/22 Update overview section based on review comments. 1.11 adk 03/15/22 Fixed syntax errors in csudma_tapp.tcl file, when stdout is configured as none.