dmaps
Xilinx Vitis Drivers API Documentation
xdmaps_hw.h File Reference

Macros

#define XDmaPs_WriteReg(BaseAddress, RegOffset, RegisterValue)   Xil_Out32((BaseAddress) + (RegOffset), (RegisterValue))
 Write a DMAC register.
 
Register Map

Register offsets for the DMAC.

#define XDMAPS_DS_OFFSET   0x000 /* DMA Status Register */
 
#define XDMAPS_DPC_OFFSET   0x004 /* DMA Program Counter Rregister */
 
#define XDMAPS_INTEN_OFFSET   0X020 /* DMA Interrupt Enable Register */
 
#define XDMAPS_ES_OFFSET   0x024 /* DMA Event Status Register */
 
#define XDMAPS_INTSTATUS_OFFSET
 
#define XDMAPS_INTCLR_OFFSET   0x02c /* DMA Interrupt Clear Register */
 
#define XDMAPS_FSM_OFFSET
 
#define XDMAPS_FSC_OFFSET
 
#define XDMAPS_FTM_OFFSET   0x038 /* DMA Fault Type DMA Manager Register */
 
#define XDMAPS_FTC0_OFFSET   0x040 /* DMA Fault Type for DMA Channel 0 */
 
#define XDmaPs_FTCn_OFFSET(ch)   (XDMAPS_FTC0_OFFSET + (ch) * 4)
 
#define XDMAPS_CS0_OFFSET   0x100 /* Channel Status for DMA Channel 0 */
 
#define XDmaPs_CSn_OFFSET(ch)   (XDMAPS_CS0_OFFSET + (ch) * 8)
 
#define XDMAPS_CPC0_OFFSET
 
#define XDmaPs_CPCn_OFFSET(ch)   (XDMAPS_CPC0_OFFSET + (ch) * 8)
 
#define XDMAPS_SA_0_OFFSET
 
#define XDmaPs_SA_n_OFFSET(ch)   (XDMAPS_SA_0_OFFSET + (ch) * 0x20)
 
#define XDMAPS_DA_0_OFFSET
 
#define XDmaPs_DA_n_OFFSET(ch)   (XDMAPS_DA_0_OFFSET + (ch) * 0x20)
 
#define XDMAPS_CC_0_OFFSET
 
#define XDmaPs_CC_n_OFFSET(ch)   (XDMAPS_CC_0_OFFSET + (ch) * 0x20)
 
#define XDMAPS_LC0_0_OFFSET   0x40C /* Loop Counter 0 for DMA Channel 0 */
 
#define XDmaPs_LC0_n_OFFSET(ch)   (XDMAPS_LC0_0_OFFSET + (ch) * 0x20)
 
#define XDMAPS_LC1_0_OFFSET   0x410 /* Loop Counter 1 for DMA Channel 0 */
 
#define XDmaPs_LC1_n_OFFSET(ch)   (XDMAPS_LC1_0_OFFSET + (ch) * 0x20)
 
#define XDMAPS_DBGSTATUS_OFFSET   0xD00 /* Debug Status Register */
 
#define XDMAPS_DBGCMD_OFFSET   0xD04 /* Debug Command Register */
 
#define XDMAPS_DBGINST0_OFFSET   0xD08 /* Debug Instruction 0 Register */
 
#define XDMAPS_DBGINST1_OFFSET   0xD0C /* Debug Instruction 1 Register */
 
#define XDMAPS_CR0_OFFSET   0xE00 /* Configuration Register 0 */
 
#define XDMAPS_CR1_OFFSET   0xE04 /* Configuration Register 1 */
 
#define XDMAPS_CR2_OFFSET   0xE08 /* Configuration Register 2 */
 
#define XDMAPS_CR3_OFFSET   0xE0C /* Configuration Register 3 */
 
#define XDMAPS_CR4_OFFSET   0xE10 /* Configuration Register 4 */
 
#define XDMAPS_CRDN_OFFSET   0xE14 /* Configuration Register Dn */
 
#define XDMAPS_PERIPH_ID_0_OFFSET
 
#define XDMAPS_PERIPH_ID_1_OFFSET
 
#define XDMAPS_PERIPH_ID_2_OFFSET
 
#define XDMAPS_PERIPH_ID_3_OFFSET
 
#define XDMAPS_PCELL_ID_0_OFFSET
 
#define XDMAPS_PCELL_ID_1_OFFSET
 
#define XDMAPS_PCELL_ID_2_OFFSET
 
#define XDMAPS_PCELL_ID_3_OFFSET
 
#define XDMAPS_DS_DMA_STATUS   0x0F /* DMA status mask */
 
#define XDMAPS_DS_DMA_STATUS_STOPPED   0x00 /* debug status busy mask */
 
#define XDMAPS_DBGSTATUS_BUSY   0x01 /* debug status busy mask */
 
#define XDMAPS_CS_ACTIVE_MASK
 
#define XDMAPS_CR1_I_CACHE_LEN_MASK   0x07 /* i_cache_len mask */
 
#define XDmaPs_DBGINST0(b1, b0, ch, dbg_th)   (((b1) << 24) | ((b0) << 16) | (((ch) & 0x7) << 8) | ((dbg_th & 0x1)))
 

Functions

void XDmaPs_ResetHw (u32 BaseAddress)
 This function perform the reset sequence to the given dmaps interface by configuring the appropriate control bits in the dmaps specifc registers the dmaps reset squence involves the following steps Disable all the interuupts Clear the pending interrupts Kill all the active channel threads Kill the manager thread.