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emacps
Vitis Drivers API Documentation
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emacps
Vitis Drivers API Documentation
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Macros | |
| #define | XEMACPS_MAX_MAC_ADDR 4U |
| Maxmum number of mac address supported. More... | |
| #define | XEMACPS_MAX_TYPE_ID 4U |
| Maxmum number of type id supported. More... | |
| #define | XEMACPS_BD_ALIGNMENT 4U |
| Minimum buffer descriptor alignment on the local bus. More... | |
| #define | XEMACPS_RX_BUF_ALIGNMENT 4U |
| Minimum buffer alignment when using options that impose alignment restrictions on the buffer data on the local bus. More... | |
| #define | XEMACPS_RX_BUF_SIZE 1536U |
| Specify the receive buffer size in bytes, 64, 128, ... More... | |
| #define | XEMACPS_RX_BUF_UNIT 64U |
| Number of receive buffer bytes as a unit, this is HW setup. More... | |
| #define | XEMACPS_MAX_RXBD 128U |
| Size of RX buffer descriptor queues. More... | |
| #define | XEMACPS_MAX_TXBD 128U |
| Size of TX buffer descriptor queues. More... | |
| #define | XEMACPS_MAX_HASH_BITS 64U |
| Maximum value for hash bits. More... | |
| #define | XEMACPS_NWCTRL_OFFSET 0x00000000U |
| Network Control reg. More... | |
| #define | XEMACPS_NWCFG_OFFSET 0x00000004U |
| Network Config reg. More... | |
| #define | XEMACPS_NWSR_OFFSET 0x00000008U |
| Network Status reg. More... | |
| #define | XEMACPS_DMACR_OFFSET 0x00000010U |
| DMA Control reg. More... | |
| #define | XEMACPS_TXSR_OFFSET 0x00000014U |
| TX Status reg. More... | |
| #define | XEMACPS_RXQBASE_OFFSET 0x00000018U |
| RX Q Base address reg. More... | |
| #define | XEMACPS_TXQBASE_OFFSET 0x0000001CU |
| TX Q Base address reg. More... | |
| #define | XEMACPS_RXSR_OFFSET 0x00000020U |
| RX Status reg. More... | |
| #define | XEMACPS_ISR_OFFSET 0x00000024U |
| Interrupt Status reg. More... | |
| #define | XEMACPS_IER_OFFSET 0x00000028U |
| Interrupt Enable reg. More... | |
| #define | XEMACPS_IDR_OFFSET 0x0000002CU |
| Interrupt Disable reg. More... | |
| #define | XEMACPS_IMR_OFFSET 0x00000030U |
| Interrupt Mask reg. More... | |
| #define | XEMACPS_PHYMNTNC_OFFSET 0x00000034U |
| Phy Maintaince reg. More... | |
| #define | XEMACPS_RXPAUSE_OFFSET 0x00000038U |
| RX Pause Time reg. More... | |
| #define | XEMACPS_TXPAUSE_OFFSET 0x0000003CU |
| TX Pause Time reg. More... | |
| #define | XEMACPS_JUMBOMAXLEN_OFFSET 0x00000048U |
| Jumbo max length reg. More... | |
| #define | XEMACPS_RXWATERMARK_OFFSET 0x0000007CU |
| RX watermark reg. More... | |
| #define | XEMACPS_HASHL_OFFSET 0x00000080U |
| Hash Low address reg. More... | |
| #define | XEMACPS_HASHH_OFFSET 0x00000084U |
| Hash High address reg. More... | |
| #define | XEMACPS_LADDR1L_OFFSET 0x00000088U |
| Specific1 addr low reg. More... | |
| #define | XEMACPS_LADDR1H_OFFSET 0x0000008CU |
| Specific1 addr high reg. More... | |
| #define | XEMACPS_LADDR2L_OFFSET 0x00000090U |
| Specific2 addr low reg. More... | |
| #define | XEMACPS_LADDR2H_OFFSET 0x00000094U |
| Specific2 addr high reg. More... | |
| #define | XEMACPS_LADDR3L_OFFSET 0x00000098U |
| Specific3 addr low reg. More... | |
| #define | XEMACPS_LADDR3H_OFFSET 0x0000009CU |
| Specific3 addr high reg. More... | |
| #define | XEMACPS_LADDR4L_OFFSET 0x000000A0U |
| Specific4 addr low reg. More... | |
| #define | XEMACPS_LADDR4H_OFFSET 0x000000A4U |
| Specific4 addr high reg. More... | |
| #define | XEMACPS_MATCH1_OFFSET 0x000000A8U |
| Type ID1 Match reg. More... | |
| #define | XEMACPS_MATCH2_OFFSET 0x000000ACU |
| Type ID2 Match reg. More... | |
| #define | XEMACPS_MATCH3_OFFSET 0x000000B0U |
| Type ID3 Match reg. More... | |
| #define | XEMACPS_MATCH4_OFFSET 0x000000B4U |
| Type ID4 Match reg. More... | |
| #define | XEMACPS_STRETCH_OFFSET 0x000000BCU |
| IPG Stretch reg. More... | |
| #define | XEMACPS_OCTTXL_OFFSET 0x00000100U |
| Octects transmitted Low reg. More... | |
| #define | XEMACPS_OCTTXH_OFFSET 0x00000104U |
| Octects transmitted High reg. More... | |
| #define | XEMACPS_TXCNT_OFFSET 0x00000108U |
| Error-free Frmaes transmitted counter. More... | |
| #define | XEMACPS_TXBCCNT_OFFSET 0x0000010CU |
| Error-free Broadcast Frames counter. More... | |
| #define | XEMACPS_TXMCCNT_OFFSET 0x00000110U |
| Error-free Multicast Frame counter. More... | |
| #define | XEMACPS_TXPAUSECNT_OFFSET 0x00000114U |
| Pause Frames Transmitted Counter. More... | |
| #define | XEMACPS_TX64CNT_OFFSET 0x00000118U |
| Error-free 64 byte Frames Transmitted counter. More... | |
| #define | XEMACPS_TX65CNT_OFFSET 0x0000011CU |
| Error-free 65-127 byte Frames Transmitted counter. More... | |
| #define | XEMACPS_TX128CNT_OFFSET 0x00000120U |
| Error-free 128-255 byte Frames Transmitted counter. More... | |
| #define | XEMACPS_TX256CNT_OFFSET 0x00000124U |
| Error-free 256-511 byte Frames transmitted counter. More... | |
| #define | XEMACPS_TX512CNT_OFFSET 0x00000128U |
| Error-free 512-1023 byte Frames transmitted counter. More... | |
| #define | XEMACPS_TX1024CNT_OFFSET 0x0000012CU |
| Error-free 1024-1518 byte Frames transmitted counter. More... | |
| #define | XEMACPS_TX1519CNT_OFFSET 0x00000130U |
| Error-free larger than 1519 byte Frames transmitted counter. More... | |
| #define | XEMACPS_TXURUNCNT_OFFSET 0x00000134U |
| TX under run error counter. More... | |
| #define | XEMACPS_SNGLCOLLCNT_OFFSET 0x00000138U |
| Single Collision Frame Counter. More... | |
| #define | XEMACPS_MULTICOLLCNT_OFFSET 0x0000013CU |
| Multiple Collision Frame Counter. More... | |
| #define | XEMACPS_EXCESSCOLLCNT_OFFSET 0x00000140U |
| Excessive Collision Frame Counter. More... | |
| #define | XEMACPS_LATECOLLCNT_OFFSET 0x00000144U |
| Late Collision Frame Counter. More... | |
| #define | XEMACPS_TXDEFERCNT_OFFSET 0x00000148U |
| Deferred Transmission Frame Counter. More... | |
| #define | XEMACPS_TXCSENSECNT_OFFSET 0x0000014CU |
| Transmit Carrier Sense Error Counter. More... | |
| #define | XEMACPS_OCTRXL_OFFSET 0x00000150U |
| Octects Received register Low. More... | |
| #define | XEMACPS_OCTRXH_OFFSET 0x00000154U |
| Octects Received register High. More... | |
| #define | XEMACPS_RXCNT_OFFSET 0x00000158U |
| Error-free Frames Received Counter. More... | |
| #define | XEMACPS_RXBROADCNT_OFFSET 0x0000015CU |
| Error-free Broadcast Frames Received Counter. More... | |
| #define | XEMACPS_RXMULTICNT_OFFSET 0x00000160U |
| Error-free Multicast Frames Received Counter. More... | |
| #define | XEMACPS_RXPAUSECNT_OFFSET 0x00000164U |
| Pause Frames Received Counter. More... | |
| #define | XEMACPS_RX64CNT_OFFSET 0x00000168U |
| Error-free 64 byte Frames Received Counter. More... | |
| #define | XEMACPS_RX65CNT_OFFSET 0x0000016CU |
| Error-free 65-127 byte Frames Received Counter. More... | |
| #define | XEMACPS_RX128CNT_OFFSET 0x00000170U |
| Error-free 128-255 byte Frames Received Counter. More... | |
| #define | XEMACPS_RX256CNT_OFFSET 0x00000174U |
| Error-free 256-512 byte Frames Received Counter. More... | |
| #define | XEMACPS_RX512CNT_OFFSET 0x00000178U |
| Error-free 512-1023 byte Frames Received Counter. More... | |
| #define | XEMACPS_RX1024CNT_OFFSET 0x0000017CU |
| Error-free 1024-1518 byte Frames Received Counter. More... | |
| #define | XEMACPS_RX1519CNT_OFFSET 0x00000180U |
| Error-free 1519-max byte Frames Received Counter. More... | |
| #define | XEMACPS_RXUNDRCNT_OFFSET 0x00000184U |
| Undersize Frames Received Counter. More... | |
| #define | XEMACPS_RXOVRCNT_OFFSET 0x00000188U |
| Oversize Frames Received Counter. More... | |
| #define | XEMACPS_RXJABCNT_OFFSET 0x0000018CU |
| Jabbers Received Counter. More... | |
| #define | XEMACPS_RXFCSCNT_OFFSET 0x00000190U |
| Frame Check Sequence Error Counter. More... | |
| #define | XEMACPS_RXLENGTHCNT_OFFSET 0x00000194U |
| Length Field Error Counter. More... | |
| #define | XEMACPS_RXSYMBCNT_OFFSET 0x00000198U |
| Symbol Error Counter. More... | |
| #define | XEMACPS_RXALIGNCNT_OFFSET 0x0000019CU |
| Alignment Error Counter. More... | |
| #define | XEMACPS_RXRESERRCNT_OFFSET 0x000001A0U |
| Receive Resource Error Counter. More... | |
| #define | XEMACPS_RXORCNT_OFFSET 0x000001A4U |
| Receive Overrun Counter. More... | |
| #define | XEMACPS_RXIPCCNT_OFFSET 0x000001A8U |
| IP header Checksum Error Counter. More... | |
| #define | XEMACPS_RXTCPCCNT_OFFSET 0x000001ACU |
| TCP Checksum Error Counter. More... | |
| #define | XEMACPS_RXUDPCCNT_OFFSET 0x000001B0U |
| UDP Checksum Error Counter. More... | |
| #define | XEMACPS_LAST_OFFSET 0x000001B4U |
| Last statistic counter offset, for clearing. More... | |
| #define | XEMACPS_1588_SEC_OFFSET 0x000001D0U |
| 1588 second counter More... | |
| #define | XEMACPS_1588_NANOSEC_OFFSET 0x000001D4U |
| 1588 nanosecond counter More... | |
| #define | XEMACPS_1588_ADJ_OFFSET 0x000001D8U |
| 1588 nanosecond adjustment counter More... | |
| #define | XEMACPS_1588_INC_OFFSET 0x000001DCU |
| 1588 nanosecond increment counter More... | |
| #define | XEMACPS_PTP_TXSEC_OFFSET 0x000001E0U |
| 1588 PTP transmit second counter More... | |
| #define | XEMACPS_PTP_TXNANOSEC_OFFSET 0x000001E4U |
| 1588 PTP transmit nanosecond counter More... | |
| #define | XEMACPS_PTP_RXSEC_OFFSET 0x000001E8U |
| 1588 PTP receive second counter More... | |
| #define | XEMACPS_PTP_RXNANOSEC_OFFSET 0x000001ECU |
| 1588 PTP receive nanosecond counter More... | |
| #define | XEMACPS_PTPP_TXSEC_OFFSET 0x000001F0U |
| 1588 PTP peer transmit second counter More... | |
| #define | XEMACPS_PTPP_TXNANOSEC_OFFSET 0x000001F4U |
| 1588 PTP peer transmit nanosecond counter More... | |
| #define | XEMACPS_PTPP_RXSEC_OFFSET 0x000001F8U |
| 1588 PTP peer receive second counter More... | |
| #define | XEMACPS_PTPP_RXNANOSEC_OFFSET 0x000001FCU |
| 1588 PTP peer receive nanosecond counter More... | |
| #define | XEMACPS_INTQ1_STS_OFFSET 0x00000400U |
| Interrupt Q1 Status reg. More... | |
| #define | XEMACPS_TXQ1BASE_OFFSET 0x00000440U |
| TX Q1 Base address reg. More... | |
| #define | XEMACPS_RXQ1BASE_OFFSET 0x00000480U |
| RX Q1 Base address reg. More... | |
| #define | XEMACPS_DMA_RXQ1_BUFSIZE_OFFSET 0x000004A0U |
| RX Q1 DMA buffer size reg. More... | |
| #define | XEMACPS_MSBBUF_TXQBASE_OFFSET 0x000004C8U |
| MSB Buffer TX Q Base reg. More... | |
| #define | XEMACPS_MSBBUF_RXQBASE_OFFSET 0x000004D4U |
| MSB Buffer RX Q Base reg. More... | |
| #define | XEMACPS_INTQ1_IER_OFFSET 0x00000600U |
| Interrupt Q1 Enable reg. More... | |
| #define | XEMACPS_INTQ1_IDR_OFFSET 0x00000620U |
| Interrupt Q1 Disable reg. More... | |
| #define | XEMACPS_INTQ1_IMR_OFFSET 0x00000640U |
| Interrupt Q1 Mask reg. More... | |
| #define | XEMACPS_BD_ADDR_OFFSET 0x00000000U |
| word 0/addr of BDs More... | |
| #define | XEMACPS_BD_STAT_OFFSET 0x00000004U |
| word 1/status of BDs More... | |
| #define | XEMACPS_BD_ADDR_HI_OFFSET 0x00000008U |
| word 2/addr of BDs More... | |
| #define | XEMACPS_TXBUF_USED_MASK 0x80000000U |
| Used bit. More... | |
| #define | XEMACPS_TXBUF_WRAP_MASK 0x40000000U |
| Wrap bit, last descriptor. More... | |
| #define | XEMACPS_TXBUF_RETRY_MASK 0x20000000U |
| Retry limit exceeded. More... | |
| #define | XEMACPS_TXBUF_URUN_MASK 0x10000000U |
| Transmit underrun occurred. More... | |
| #define | XEMACPS_TXBUF_EXH_MASK 0x08000000U |
| Buffers exhausted. More... | |
| #define | XEMACPS_TXBUF_TCP_MASK 0x04000000U |
| Late collision. More... | |
| #define | XEMACPS_TXBUF_NOCRC_MASK 0x00010000U |
| No CRC. More... | |
| #define | XEMACPS_TXBUF_LAST_MASK 0x00008000U |
| Last buffer. More... | |
| #define | XEMACPS_TXBUF_LEN_MASK 0x00003FFFU |
| Mask for length field. More... | |
| #define | XEMACPS_RXBUF_BCAST_MASK 0x80000000U |
| Broadcast frame. More... | |
| #define | XEMACPS_RXBUF_MULTIHASH_MASK 0x40000000U |
| Multicast hashed frame. More... | |
| #define | XEMACPS_RXBUF_UNIHASH_MASK 0x20000000U |
| Unicast hashed frame. More... | |
| #define | XEMACPS_RXBUF_EXH_MASK 0x08000000U |
| buffer exhausted More... | |
| #define | XEMACPS_RXBUF_AMATCH_MASK 0x06000000U |
| Specific address matched. More... | |
| #define | XEMACPS_RXBUF_IDFOUND_MASK 0x01000000U |
| Type ID matched. More... | |
| #define | XEMACPS_RXBUF_IDMATCH_MASK 0x00C00000U |
| ID matched mask. More... | |
| #define | XEMACPS_RXBUF_VLAN_MASK 0x00200000U |
| VLAN tagged. More... | |
| #define | XEMACPS_RXBUF_PRI_MASK 0x00100000U |
| Priority tagged. More... | |
| #define | XEMACPS_RXBUF_VPRI_MASK 0x000E0000U |
| Vlan priority. More... | |
| #define | XEMACPS_RXBUF_CFI_MASK 0x00010000U |
| CFI frame. More... | |
| #define | XEMACPS_RXBUF_EOF_MASK 0x00008000U |
| End of frame. More... | |
| #define | XEMACPS_RXBUF_SOF_MASK 0x00004000U |
| Start of frame. More... | |
| #define | XEMACPS_RXBUF_LEN_MASK 0x00001FFFU |
| Mask for length field. More... | |
| #define | XEMACPS_RXBUF_LEN_JUMBO_MASK 0x00003FFFU |
| Mask for jumbo length. More... | |
| #define | XEMACPS_RXBUF_WRAP_MASK 0x00000002U |
| Wrap bit, last BD. More... | |
| #define | XEMACPS_RXBUF_NEW_MASK 0x00000001U |
| Used bit. More... | |
| #define | XEMACPS_RXBUF_ADD_MASK 0xFFFFFFFCU |
| Mask for address. More... | |
| #define | XEmacPs_ReadReg(BaseAddress, RegOffset) XEmacPs_In32((BaseAddress) + (u32)(RegOffset)) |
| Read the given register. More... | |
| #define | XEmacPs_WriteReg(BaseAddress, RegOffset, Data) XEmacPs_Out32((BaseAddress) + (u32)(RegOffset), (u32)(Data)) |
| Write the given register. More... | |
Direction identifiers | |
These are used by several functions and callbacks that need to specify whether an operation specifies a send or receive channel. | |
| #define | XEMACPS_SEND 1U |
| send direction More... | |
| #define | XEMACPS_RECV 2U |
| receive direction More... | |
network control register bit definitions | |
| #define | XEMACPS_NWCTRL_FLUSH_DPRAM_MASK 0x00040000U |
| Flush a packet from Rx SRAM. More... | |
| #define | XEMACPS_NWCTRL_ZEROPAUSETX_MASK 0x00000800U |
| Transmit zero quantum pause frame. More... | |
| #define | XEMACPS_NWCTRL_PAUSETX_MASK 0x00000800U |
| Transmit pause frame. More... | |
| #define | XEMACPS_NWCTRL_HALTTX_MASK 0x00000400U |
| Halt transmission after current frame. More... | |
| #define | XEMACPS_NWCTRL_STARTTX_MASK 0x00000200U |
| Start tx (tx_go) More... | |
| #define | XEMACPS_NWCTRL_STATWEN_MASK 0x00000080U |
| Enable writing to stat counters. More... | |
| #define | XEMACPS_NWCTRL_STATINC_MASK 0x00000040U |
| Increment statistic registers. More... | |
| #define | XEMACPS_NWCTRL_STATCLR_MASK 0x00000020U |
| Clear statistic registers. More... | |
| #define | XEMACPS_NWCTRL_MDEN_MASK 0x00000010U |
| Enable MDIO port. More... | |
| #define | XEMACPS_NWCTRL_TXEN_MASK 0x00000008U |
| Enable transmit. More... | |
| #define | XEMACPS_NWCTRL_RXEN_MASK 0x00000004U |
| Enable receive. More... | |
| #define | XEMACPS_NWCTRL_LOOPEN_MASK 0x00000002U |
| local loopback More... | |
network configuration register bit definitions | |
| #define | XEMACPS_NWCFG_BADPREAMBEN_MASK 0x20000000U |
| disable rejection of non-standard preamble More... | |
| #define | XEMACPS_NWCFG_IPDSTRETCH_MASK 0x10000000U |
| enable transmit IPG More... | |
| #define | XEMACPS_NWCFG_SGMIIEN_MASK 0x08000000U |
| SGMII Enable. More... | |
| #define | XEMACPS_NWCFG_FCSIGNORE_MASK 0x04000000U |
| disable rejection of FCS error More... | |
| #define | XEMACPS_NWCFG_HDRXEN_MASK 0x02000000U |
| RX half duplex. More... | |
| #define | XEMACPS_NWCFG_RXCHKSUMEN_MASK 0x01000000U |
| enable RX checksum offload More... | |
| #define | XEMACPS_NWCFG_PAUSECOPYDI_MASK 0x00800000U |
| Do not copy pause Frames to memory. More... | |
| #define | XEMACPS_NWCFG_DWIDTH_64_MASK 0x00200000U |
| 64 bit Data bus width More... | |
| #define | XEMACPS_NWCFG_MDC_SHIFT_MASK 18U |
| shift bits for MDC More... | |
| #define | XEMACPS_NWCFG_MDCCLKDIV_MASK 0x001C0000U |
| MDC Mask PCLK divisor. More... | |
| #define | XEMACPS_NWCFG_FCSREM_MASK 0x00020000U |
| Discard FCS from received frames. More... | |
| #define | XEMACPS_NWCFG_LENERRDSCRD_MASK 0x00010000U |
| RX length error discard. More... | |
| #define | XEMACPS_NWCFG_RXOFFS_MASK 0x0000C000U |
| RX buffer offset. More... | |
| #define | XEMACPS_NWCFG_PAUSEEN_MASK 0x00002000U |
| Enable pause RX. More... | |
| #define | XEMACPS_NWCFG_RETRYTESTEN_MASK 0x00001000U |
| Retry test. More... | |
| #define | XEMACPS_NWCFG_XTADDMACHEN_MASK 0x00000200U |
| External address match enable. More... | |
| #define | XEMACPS_NWCFG_PCSSEL_MASK 0x00000800U |
| PCS Select. More... | |
| #define | XEMACPS_NWCFG_1000_MASK 0x00000400U |
| 1000 Mbps More... | |
| #define | XEMACPS_NWCFG_1536RXEN_MASK 0x00000100U |
| Enable 1536 byte frames reception. More... | |
| #define | XEMACPS_NWCFG_UCASTHASHEN_MASK 0x00000080U |
| Receive unicast hash frames. More... | |
| #define | XEMACPS_NWCFG_MCASTHASHEN_MASK 0x00000040U |
| Receive multicast hash frames. More... | |
| #define | XEMACPS_NWCFG_BCASTDI_MASK 0x00000020U |
| Do not receive broadcast frames. More... | |
| #define | XEMACPS_NWCFG_COPYALLEN_MASK 0x00000010U |
| Copy all frames. More... | |
| #define | XEMACPS_NWCFG_JUMBO_MASK 0x00000008U |
| Jumbo frames. More... | |
| #define | XEMACPS_NWCFG_NVLANDISC_MASK 0x00000004U |
| Receive only VLAN frames. More... | |
| #define | XEMACPS_NWCFG_FDEN_MASK 0x00000002U |
| full duplex More... | |
| #define | XEMACPS_NWCFG_100_MASK 0x00000001U |
| 100 Mbps More... | |
| #define | XEMACPS_NWCFG_RESET_MASK 0x00080000U |
| reset value More... | |
network status register bit definitaions | |
| #define | XEMACPS_NWSR_MDIOIDLE_MASK 0x00000004U |
| PHY management idle. More... | |
| #define | XEMACPS_NWSR_MDIO_MASK 0x00000002U |
| Status of mdio_in. More... | |
MAC address register word 1 mask | |
| #define | XEMACPS_LADDR_MACH_MASK 0x0000FFFFU |
| Address bits[47:32] bit[31:0] are in BOTTOM. More... | |
DMA control register bit definitions | |
| #define | XEMACPS_DMACR_ADDR_WIDTH_64 0x40000000U |
| 64 bit address bus More... | |
| #define | XEMACPS_DMACR_TXEXTEND_MASK 0x20000000U |
| Tx Extended desc mode. More... | |
| #define | XEMACPS_DMACR_RXEXTEND_MASK 0x10000000U |
| Rx Extended desc mode. More... | |
| #define | XEMACPS_DMACR_RXBUF_MASK 0x00FF0000U |
| Mask bit for RX buffer size. More... | |
| #define | XEMACPS_DMACR_RXBUF_SHIFT 16U |
| Shift bit for RX buffer size. More... | |
| #define | XEMACPS_DMACR_TCPCKSUM_MASK 0x00000800U |
| enable/disable TX checksum offload More... | |
| #define | XEMACPS_DMACR_TXSIZE_MASK 0x00000400U |
| TX buffer memory size. More... | |
| #define | XEMACPS_DMACR_RXSIZE_MASK 0x00000300U |
| RX buffer memory size. More... | |
| #define | XEMACPS_DMACR_ENDIAN_MASK 0x00000080U |
| endian configuration More... | |
| #define | XEMACPS_DMACR_BLENGTH_MASK 0x0000001FU |
| buffer burst length More... | |
| #define | XEMACPS_DMACR_SINGLE_AHB_BURST 0x00000001U |
| single AHB bursts More... | |
| #define | XEMACPS_DMACR_INCR4_AHB_BURST 0x00000004U |
| 4 bytes AHB bursts More... | |
| #define | XEMACPS_DMACR_INCR8_AHB_BURST 0x00000008U |
| 8 bytes AHB bursts More... | |
| #define | XEMACPS_DMACR_INCR16_AHB_BURST 0x00000010U |
| 16 bytes AHB bursts More... | |
transmit status register bit definitions | |
| #define | XEMACPS_TXSR_HRESPNOK_MASK 0x00000100U |
| Transmit hresp not OK. More... | |
| #define | XEMACPS_TXSR_URUN_MASK 0x00000040U |
| Transmit underrun. More... | |
| #define | XEMACPS_TXSR_TXCOMPL_MASK 0x00000020U |
| Transmit completed OK. More... | |
| #define | XEMACPS_TXSR_BUFEXH_MASK 0x00000010U |
| Transmit buffs exhausted mid frame. More... | |
| #define | XEMACPS_TXSR_TXGO_MASK 0x00000008U |
| Status of go flag. More... | |
| #define | XEMACPS_TXSR_RXOVR_MASK 0x00000004U |
| Retry limit exceeded. More... | |
| #define | XEMACPS_TXSR_FRAMERX_MASK 0x00000002U |
| Collision tx frame. More... | |
| #define | XEMACPS_TXSR_USEDREAD_MASK 0x00000001U |
| TX buffer used bit set. More... | |
| #define | XEMACPS_TXSR_ERROR_MASK |
receive status register bit definitions | |
| #define | XEMACPS_RXSR_HRESPNOK_MASK 0x00000008U |
| Receive hresp not OK. More... | |
| #define | XEMACPS_RXSR_RXOVR_MASK 0x00000004U |
| Receive overrun. More... | |
| #define | XEMACPS_RXSR_FRAMERX_MASK 0x00000002U |
| Frame received OK. More... | |
| #define | XEMACPS_RXSR_BUFFNA_MASK 0x00000001U |
| RX buffer used bit set. More... | |
| #define | XEMACPS_RXSR_ERROR_MASK |
| #define | XEMACPS_SR_ALL_MASK 0xFFFFFFFFU |
| Mask for full register. More... | |
PCS control register bit definitions | |
| #define | XEMACPS_PCS_CON_AUTO_NEG_MASK 0x00001000U |
| Auto-negotiation. More... | |
PCS status register bit definitions | |
| #define | XEMACPS_PCS_STATUS_LINK_STATUS_MASK 0x00000004U |
| Link status. More... | |
Interrupt Q1 status register bit definitions | |
| #define | XEMACPS_INTQ1SR_TXCOMPL_MASK 0x00000080U |
| Transmit completed OK. More... | |
| #define | XEMACPS_INTQ1SR_TXERR_MASK 0x00000040U |
| Transmit AMBA Error. More... | |
| #define | XEMACPS_INTQ1SR_RXCOMPL_MASK 0x00000002U |
| Receive completed OK. More... | |
| #define | XEMACPS_INTQ1_IXR_ALL_MASK |
| #define | XEMACPS_INTQ1_IXR_TX_MASK |
| #define | XEMACPS_INTQ1_IXR_RX_MASK (u32)XEMACPS_INTQ1SR_RXCOMPL_MASK |
| #define | XEMACPS_INTQISR_RXCOMPL_MASK XEMACPS_INTQ1SR_RXCOMPL_MASK |
| #define | XEMACPS_INTQISR_TXCOMPL_MASK XEMACPS_INTQ1SR_TXCOMPL_MASK |
| #define | XEMACPS_INTQSR_TXERR_MASK XEMACPS_INTQ1SR_TXERR_MASK |
| #define | XEMACPS_INTQ_IXR_ALL_MASK XEMACPS_INTQ1_IXR_ALL_MASK |
interrupts bit definitions | |
Bits definitions are same in XEMACPS_ISR_OFFSET, XEMACPS_IER_OFFSET, XEMACPS_IDR_OFFSET, and XEMACPS_IMR_OFFSET | |
| #define | XEMACPS_IXR_PTPPSTX_MASK 0x02000000U |
| PTP Pdelay_resp TXed. More... | |
| #define | XEMACPS_IXR_PTPPDRTX_MASK 0x01000000U |
| PTP Pdelay_req TXed. More... | |
| #define | XEMACPS_IXR_PTPPSRX_MASK 0x00800000U |
| PTP Pdelay_resp RXed. More... | |
| #define | XEMACPS_IXR_PTPPDRRX_MASK 0x00400000U |
| PTP Pdelay_req RXed. More... | |
| #define | XEMACPS_IXR_PTPSTX_MASK 0x00200000U |
| PTP Sync TXed. More... | |
| #define | XEMACPS_IXR_PTPDRTX_MASK 0x00100000U |
| PTP Delay_req TXed. More... | |
| #define | XEMACPS_IXR_PTPSRX_MASK 0x00080000U |
| PTP Sync RXed. More... | |
| #define | XEMACPS_IXR_PTPDRRX_MASK 0x00040000U |
| PTP Delay_req RXed. More... | |
| #define | XEMACPS_IXR_PAUSETX_MASK 0x00004000U |
| Pause frame transmitted. More... | |
| #define | XEMACPS_IXR_PAUSEZERO_MASK 0x00002000U |
| Pause time has reached zero. More... | |
| #define | XEMACPS_IXR_PAUSENZERO_MASK 0x00001000U |
| Pause frame received. More... | |
| #define | XEMACPS_IXR_HRESPNOK_MASK 0x00000800U |
| hresp not ok More... | |
| #define | XEMACPS_IXR_RXOVR_MASK 0x00000400U |
| Receive overrun occurred. More... | |
| #define | XEMACPS_IXR_TXCOMPL_MASK 0x00000080U |
| Frame transmitted ok. More... | |
| #define | XEMACPS_IXR_TXEXH_MASK 0x00000040U |
| Transmit err occurred or no buffers. More... | |
| #define | XEMACPS_IXR_RETRY_MASK 0x00000020U |
| Retry limit exceeded. More... | |
| #define | XEMACPS_IXR_URUN_MASK 0x00000010U |
| Transmit underrun. More... | |
| #define | XEMACPS_IXR_TXUSED_MASK 0x00000008U |
| Tx buffer used bit read. More... | |
| #define | XEMACPS_IXR_RXUSED_MASK 0x00000004U |
| Rx buffer used bit read. More... | |
| #define | XEMACPS_IXR_FRAMERX_MASK 0x00000002U |
| Frame received ok. More... | |
| #define | XEMACPS_IXR_MGMNT_MASK 0x00000001U |
| PHY management complete. More... | |
| #define | XEMACPS_IXR_ALL_MASK 0x00007FFFU |
| Everything! More... | |
| #define | XEMACPS_IXR_TX_ERR_MASK |
| #define | XEMACPS_IXR_RX_ERR_MASK |
PHY Maintenance bit definitions | |
| #define | XEMACPS_PHYMNTNC_OP_MASK 0x40020000U |
| operation mask bits More... | |
| #define | XEMACPS_PHYMNTNC_OP_R_MASK 0x20000000U |
| read operation More... | |
| #define | XEMACPS_PHYMNTNC_OP_W_MASK 0x10000000U |
| write operation More... | |
| #define | XEMACPS_PHYMNTNC_ADDR_MASK 0x0F800000U |
| Address bits. More... | |
| #define | XEMACPS_PHYMNTNC_REG_MASK 0x007C0000U |
| register bits More... | |
| #define | XEMACPS_PHYMNTNC_DATA_MASK 0x00000FFFU |
| data bits More... | |
| #define | XEMACPS_PHYMNTNC_PHAD_SHFT_MSK 23U |
| Shift bits for PHYAD. More... | |
| #define | XEMACPS_PHYMNTNC_PREG_SHFT_MSK 18U |
| Shift bits for PHREG. More... | |
RX watermark bit definitions | |
| #define | XEMACPS_RXWM_HIGH_MASK 0x0000FFFFU |
| RXWM high mask. More... | |
| #define | XEMACPS_RXWM_LOW_MASK 0xFFFF0000U |
| RXWM low mask. More... | |
| #define | XEMACPS_RXWM_LOW_SHFT_MSK 16U |
| Shift for RXWM low. More... | |
Screening Type2 bit definitions | |
| #define | XEMACPS_CMPA_ENABLE_MASK 0x00040000U |
| Enable Compare A. More... | |
| #define | XEMACPS_CMPA_MASK 0x0003E000U |
| Compare reg number. More... | |
Enumerations | |
MDC clock division | |
currently supporting 8, 16, 32, 48, 64, 96, 128, 224. | |
| enum | XEmacPs_MdcDiv |
Functions | |
| void | XEmacPs_ResetHw (u32 BaseAddr) |
| This function perform the reset sequence to the given emacps interface by configuring the appropriate control bits in the emacps specific registers. More... | |
| u32 | XEmacPs_GetQxOffset (XEmacPs_QxRegOffset RegName, u8 Queue) |
| The register offset of a specific queue register is returned by this function. More... | |
Queue Registers Offset | |
| #define | MAX_QUEUES_FEASIBLE 2 /* Max queues possible on latest device */ |
| enum | XEmacPs_QxRegOffset |