Data Structures
struct	XEmacPs_Config
	This typedef contains configuration information for a device. More...

struct	XEmacPs_Instance
	The XEmacPs driver instance data. More...

struct	XEmacPs_BdRing
	This is an internal structure used to maintain the DMA list. More...

Macros
#define	XEMACPS_MDIO_DIV_DFT MDC_DIV_32
	Default MDIO clock divisor. More...

#define	XEmacPs_GetTxRing(InstancePtr) ((InstancePtr)->TxBdRing)
	Retrieve the Tx ring object. More...

#define	XEmacPs_GetRxRing(InstancePtr) ((InstancePtr)->RxBdRing)
	Retrieve the Rx ring object. More...

#define	XEmacPs_IntEnable(InstancePtr, Mask)
	Enable interrupts specified in Mask. More...

#define	XEmacPs_IntDisable(InstancePtr, Mask)
	Disable interrupts specified in Mask. More...

#define	XEmacPs_IntQiEnable(InstancePtr, Queue, Mask)
	Enable interrupts of queue Queue specified in Mask. More...

#define	XEmacPs_IntQiDisable(InstancePtr, Queue, Mask)
	Disable interrupts of queue Queue specified in Mask. More...

#define	XEmacPs_Transmit(InstancePtr)
	This macro triggers trasmit circuit to send data currently in TX buffer(s). More...

#define	XEmacPs_IsRxCsum(InstancePtr)
	This macro determines if the device is configured with checksum offloading on the receive channel. More...

#define	XEmacPs_IsTxCsum(InstancePtr)
	This macro determines if the device is configured with checksum offloading on the transmit channel. More...

#define	XEmacPs_SetRXWatermark(InstancePtr, High, Low)
	This macro sets RX watermark register. More...

#define	XEmacPs_GetRXWatermark(InstancePtr)
	This macro gets RX watermark register. More...

#define	XEmacPs_BdClear(BdPtr) memset((BdPtr), 0, sizeof(XEmacPs_Bd))
	Zero out BD fields. More...

#define	XEmacPs_BdRead(BaseAddress, Offset) ((u32 )((UINTPTR)((void*)(BaseAddress)) + (u32)(Offset)))
	Read the given Buffer Descriptor word. More...

#define	XEmacPs_BdWrite(BaseAddress, Offset, Data) ((u32 )((UINTPTR)(void*)(BaseAddress) + (u32)(Offset)) = (u32)(Data))
	Write the given Buffer Descriptor word. More...

#define	XEmacPs_BdSetAddressTx(BdPtr, Addr) XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, (u32)(Addr))
	Set the BD's Address field (word 0). More...

#define	XEmacPs_BdSetAddressRx(BdPtr, Addr)
	Set the BD's Address field (word 0). More...

#define	XEmacPs_BdSetStatus(BdPtr, Data)
	Set the BD's Status field (word 1). More...

#define	XEmacPs_BdGetStatus(BdPtr) XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET)
	Retrieve the BD's Packet DMA transfer status word (word 1). More...

#define	XEmacPs_BdGetBufAddr(BdPtr) (XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & XEMACPS_RXBUF_ADD_MASK)
	Get the address (bits 0..31) of the BD's buffer address (word 0) More...

#define	XEmacPs_BdSetLength(BdPtr, LenBytes)
	Set transfer length in bytes for the given BD. More...

#define	XEmacPs_BdGetLength(BdPtr)
	Retrieve the BD length field. More...

#define	XEmacPs_GetRxFrameSize(InstancePtr, BdPtr)
	Retrieve the RX frame size. More...

#define	XEmacPs_BdIsLast(BdPtr)
	Test whether the given BD has been marked as the last BD of a packet. More...

#define	XEmacPs_BdSetLast(BdPtr)
	Tell the DMA engine that the given transmit BD marks the end of the current packet to be processed. More...

#define	XEmacPs_BdClearLast(BdPtr)
	Tell the DMA engine that the current packet does not end with the given BD. More...

#define	XEmacPs_BdIsRxWrap(BdPtr)
	Set this bit to mark the last descriptor in the receive buffer descriptor list. More...

#define	XEmacPs_BdIsTxWrap(BdPtr)
	Sets this bit to mark the last descriptor in the transmit buffer descriptor list. More...

#define	XEmacPs_BdIsRxNew(BdPtr)
	Determine the new bit of the receive BD. More...

#define	XEmacPs_BdSetTxUsed(BdPtr)
	Software sets this bit to disable the buffer to be read by the hardware. More...

#define	XEmacPs_BdClearTxUsed(BdPtr)
	Software clears this bit to enable the buffer to be read by the hardware. More...

#define	XEmacPs_BdIsTxUsed(BdPtr)
	Determine the used bit of the transmit BD. More...

#define	XEmacPs_BdIsTxRetry(BdPtr)
	Determine if a frame fails to be transmitted due to too many retries. More...

#define	XEmacPs_BdIsTxUrun(BdPtr)
	Determine if a frame fails to be transmitted due to data can not be feteched in time or buffers are exhausted. More...

#define	XEmacPs_BdIsTxExh(BdPtr)
	Determine if a frame fails to be transmitted due to buffer is exhausted mid-frame. More...

#define	XEmacPs_BdSetTxNoCRC(BdPtr)
	Sets this bit, no CRC will be appended to the current frame. More...

#define	XEmacPs_BdClearTxNoCRC(BdPtr)
	Clear this bit, CRC will be appended to the current frame. More...

#define	XEmacPs_BdIsRxBcast(BdPtr)
	Determine the broadcast bit of the receive BD. More...

#define	XEmacPs_BdIsRxMultiHash(BdPtr)
	Determine the multicast hash bit of the receive BD. More...

#define	XEmacPs_BdIsRxUniHash(BdPtr)
	Determine the unicast hash bit of the receive BD. More...

#define	XEmacPs_BdIsRxVlan(BdPtr)
	Determine if the received frame is a VLAN Tagged frame. More...

#define	XEmacPs_BdIsRxPri(BdPtr)
	Determine if the received frame has Type ID of 8100h and null VLAN identifier(Priority tag). More...

#define	XEmacPs_BdIsRxCFI(BdPtr)
	Determine if the received frame's Concatenation Format Indicator (CFI) of the frames VLANTCI field was set. More...

#define	XEmacPs_BdIsRxEOF(BdPtr)
	Determine the End Of Frame (EOF) bit of the receive BD. More...

#define	XEmacPs_BdIsRxSOF(BdPtr)
	Determine the Start Of Frame (SOF) bit of the receive BD. More...

#define	XEmacPs_BdRingCntCalc(Alignment, Bytes) (u32)((Bytes) / (sizeof(XEmacPs_Bd)))
	Use this macro at initialization time to determine how many BDs will fit in a BD list within the given memory constraints. More...

#define	XEmacPs_BdRingMemCalc(Alignment, NumBd) (u32)(sizeof(XEmacPs_Bd) * (NumBd))
	Use this macro at initialization time to determine how many bytes of memory is required to contain a given number of BDs at a given alignment. More...

#define	XEmacPs_BdRingGetCnt(RingPtr) ((RingPtr)->AllCnt)
	Return the total number of BDs allocated by this channel with XEmacPs_BdRingCreate(). More...

#define	XEmacPs_BdRingGetFreeCnt(RingPtr) ((RingPtr)->FreeCnt)
	Return the number of BDs allocatable with XEmacPs_BdRingAlloc() for pre- processing. More...

#define	XEmacPs_BdRingNext(RingPtr, BdPtr)
	Return the next BD from BdPtr in a list. More...

#define	XEmacPs_BdRingPrev(RingPtr, BdPtr)
	Return the previous BD from BdPtr in the list. More...

#define	XEMACPS_MAX_MAC_ADDR 4U
	Maxmum number of mac address supported. More...

#define	XEMACPS_MAX_TYPE_ID 4U
	Maxmum number of type id supported. More...

#define	XEMACPS_BD_ALIGNMENT 4U
	Minimum buffer descriptor alignment on the local bus. More...

#define	XEMACPS_RX_BUF_ALIGNMENT 4U
	Minimum buffer alignment when using options that impose alignment restrictions on the buffer data on the local bus. More...

#define	XEMACPS_RX_BUF_SIZE 1536U
	Specify the receive buffer size in bytes, 64, 128, ... More...

#define	XEMACPS_RX_BUF_UNIT 64U
	Number of receive buffer bytes as a unit, this is HW setup. More...

#define	XEMACPS_MAX_RXBD 128U
	Size of RX buffer descriptor queues. More...

#define	XEMACPS_MAX_TXBD 128U
	Size of TX buffer descriptor queues. More...

#define	XEMACPS_MAX_HASH_BITS 64U
	Maximum value for hash bits. More...

#define	XEMACPS_NWCTRL_OFFSET 0x00000000U
	Network Control reg. More...

#define	XEMACPS_NWCFG_OFFSET 0x00000004U
	Network Config reg. More...

#define	XEMACPS_NWSR_OFFSET 0x00000008U
	Network Status reg. More...

#define	XEMACPS_DMACR_OFFSET 0x00000010U
	DMA Control reg. More...

#define	XEMACPS_TXSR_OFFSET 0x00000014U
	TX Status reg. More...

#define	XEMACPS_RXQBASE_OFFSET 0x00000018U
	RX Q Base address reg. More...

#define	XEMACPS_TXQBASE_OFFSET 0x0000001CU
	TX Q Base address reg. More...

#define	XEMACPS_RXSR_OFFSET 0x00000020U
	RX Status reg. More...

#define	XEMACPS_ISR_OFFSET 0x00000024U
	Interrupt Status reg. More...

#define	XEMACPS_IER_OFFSET 0x00000028U
	Interrupt Enable reg. More...

#define	XEMACPS_IDR_OFFSET 0x0000002CU
	Interrupt Disable reg. More...

#define	XEMACPS_IMR_OFFSET 0x00000030U
	Interrupt Mask reg. More...

#define	XEMACPS_PHYMNTNC_OFFSET 0x00000034U
	Phy Maintaince reg. More...

#define	XEMACPS_RXPAUSE_OFFSET 0x00000038U
	RX Pause Time reg. More...

#define	XEMACPS_TXPAUSE_OFFSET 0x0000003CU
	TX Pause Time reg. More...

#define	XEMACPS_JUMBOMAXLEN_OFFSET 0x00000048U
	Jumbo max length reg. More...

#define	XEMACPS_RXWATERMARK_OFFSET 0x0000007CU
	RX watermark reg. More...

#define	XEMACPS_HASHL_OFFSET 0x00000080U
	Hash Low address reg. More...

#define	XEMACPS_HASHH_OFFSET 0x00000084U
	Hash High address reg. More...

#define	XEMACPS_LADDR1L_OFFSET 0x00000088U
	Specific1 addr low reg. More...

#define	XEMACPS_LADDR1H_OFFSET 0x0000008CU
	Specific1 addr high reg. More...

#define	XEMACPS_LADDR2L_OFFSET 0x00000090U
	Specific2 addr low reg. More...

#define	XEMACPS_LADDR2H_OFFSET 0x00000094U
	Specific2 addr high reg. More...

#define	XEMACPS_LADDR3L_OFFSET 0x00000098U
	Specific3 addr low reg. More...

#define	XEMACPS_LADDR3H_OFFSET 0x0000009CU
	Specific3 addr high reg. More...

#define	XEMACPS_LADDR4L_OFFSET 0x000000A0U
	Specific4 addr low reg. More...

#define	XEMACPS_LADDR4H_OFFSET 0x000000A4U
	Specific4 addr high reg. More...

#define	XEMACPS_MATCH1_OFFSET 0x000000A8U
	Type ID1 Match reg. More...

#define	XEMACPS_MATCH2_OFFSET 0x000000ACU
	Type ID2 Match reg. More...

#define	XEMACPS_MATCH3_OFFSET 0x000000B0U
	Type ID3 Match reg. More...

#define	XEMACPS_MATCH4_OFFSET 0x000000B4U
	Type ID4 Match reg. More...

#define	XEMACPS_STRETCH_OFFSET 0x000000BCU
	IPG Stretch reg. More...

#define	XEMACPS_OCTTXL_OFFSET 0x00000100U
	Octects transmitted Low reg. More...

#define	XEMACPS_OCTTXH_OFFSET 0x00000104U
	Octects transmitted High reg. More...

#define	XEMACPS_TXCNT_OFFSET 0x00000108U
	Error-free Frmaes transmitted counter. More...

#define	XEMACPS_TXBCCNT_OFFSET 0x0000010CU
	Error-free Broadcast Frames counter. More...

#define	XEMACPS_TXMCCNT_OFFSET 0x00000110U
	Error-free Multicast Frame counter. More...

#define	XEMACPS_TXPAUSECNT_OFFSET 0x00000114U
	Pause Frames Transmitted Counter. More...

#define	XEMACPS_TX64CNT_OFFSET 0x00000118U
	Error-free 64 byte Frames Transmitted counter. More...

#define	XEMACPS_TX65CNT_OFFSET 0x0000011CU
	Error-free 65-127 byte Frames Transmitted counter. More...

#define	XEMACPS_TX128CNT_OFFSET 0x00000120U
	Error-free 128-255 byte Frames Transmitted counter. More...

#define	XEMACPS_TX256CNT_OFFSET 0x00000124U
	Error-free 256-511 byte Frames transmitted counter. More...

#define	XEMACPS_TX512CNT_OFFSET 0x00000128U
	Error-free 512-1023 byte Frames transmitted counter. More...

#define	XEMACPS_TX1024CNT_OFFSET 0x0000012CU
	Error-free 1024-1518 byte Frames transmitted counter. More...

#define	XEMACPS_TX1519CNT_OFFSET 0x00000130U
	Error-free larger than 1519 byte Frames transmitted counter. More...

#define	XEMACPS_TXURUNCNT_OFFSET 0x00000134U
	TX under run error counter. More...

#define	XEMACPS_SNGLCOLLCNT_OFFSET 0x00000138U
	Single Collision Frame Counter. More...

#define	XEMACPS_MULTICOLLCNT_OFFSET 0x0000013CU
	Multiple Collision Frame Counter. More...

#define	XEMACPS_EXCESSCOLLCNT_OFFSET 0x00000140U
	Excessive Collision Frame Counter. More...

#define	XEMACPS_LATECOLLCNT_OFFSET 0x00000144U
	Late Collision Frame Counter. More...

#define	XEMACPS_TXDEFERCNT_OFFSET 0x00000148U
	Deferred Transmission Frame Counter. More...

#define	XEMACPS_TXCSENSECNT_OFFSET 0x0000014CU
	Transmit Carrier Sense Error Counter. More...

#define	XEMACPS_OCTRXL_OFFSET 0x00000150U
	Octects Received register Low. More...

#define	XEMACPS_OCTRXH_OFFSET 0x00000154U
	Octects Received register High. More...

#define	XEMACPS_RXCNT_OFFSET 0x00000158U
	Error-free Frames Received Counter. More...

#define	XEMACPS_RXBROADCNT_OFFSET 0x0000015CU
	Error-free Broadcast Frames Received Counter. More...

#define	XEMACPS_RXMULTICNT_OFFSET 0x00000160U
	Error-free Multicast Frames Received Counter. More...

#define	XEMACPS_RXPAUSECNT_OFFSET 0x00000164U
	Pause Frames Received Counter. More...

#define	XEMACPS_RX64CNT_OFFSET 0x00000168U
	Error-free 64 byte Frames Received Counter. More...

#define	XEMACPS_RX65CNT_OFFSET 0x0000016CU
	Error-free 65-127 byte Frames Received Counter. More...

#define	XEMACPS_RX128CNT_OFFSET 0x00000170U
	Error-free 128-255 byte Frames Received Counter. More...

#define	XEMACPS_RX256CNT_OFFSET 0x00000174U
	Error-free 256-512 byte Frames Received Counter. More...

#define	XEMACPS_RX512CNT_OFFSET 0x00000178U
	Error-free 512-1023 byte Frames Received Counter. More...

#define	XEMACPS_RX1024CNT_OFFSET 0x0000017CU
	Error-free 1024-1518 byte Frames Received Counter. More...

#define	XEMACPS_RX1519CNT_OFFSET 0x00000180U
	Error-free 1519-max byte Frames Received Counter. More...

#define	XEMACPS_RXUNDRCNT_OFFSET 0x00000184U
	Undersize Frames Received Counter. More...

#define	XEMACPS_RXOVRCNT_OFFSET 0x00000188U
	Oversize Frames Received Counter. More...

#define	XEMACPS_RXJABCNT_OFFSET 0x0000018CU
	Jabbers Received Counter. More...

#define	XEMACPS_RXFCSCNT_OFFSET 0x00000190U
	Frame Check Sequence Error Counter. More...

#define	XEMACPS_RXLENGTHCNT_OFFSET 0x00000194U
	Length Field Error Counter. More...

#define	XEMACPS_RXSYMBCNT_OFFSET 0x00000198U
	Symbol Error Counter. More...

#define	XEMACPS_RXALIGNCNT_OFFSET 0x0000019CU
	Alignment Error Counter. More...

#define	XEMACPS_RXRESERRCNT_OFFSET 0x000001A0U
	Receive Resource Error Counter. More...

#define	XEMACPS_RXORCNT_OFFSET 0x000001A4U
	Receive Overrun Counter. More...

#define	XEMACPS_RXIPCCNT_OFFSET 0x000001A8U
	IP header Checksum Error Counter. More...

#define	XEMACPS_RXTCPCCNT_OFFSET 0x000001ACU
	TCP Checksum Error Counter. More...

#define	XEMACPS_RXUDPCCNT_OFFSET 0x000001B0U
	UDP Checksum Error Counter. More...

#define	XEMACPS_LAST_OFFSET 0x000001B4U
	Last statistic counter offset, for clearing. More...

#define	XEMACPS_1588_SEC_OFFSET 0x000001D0U
	1588 second counter More...

#define	XEMACPS_1588_NANOSEC_OFFSET 0x000001D4U
	1588 nanosecond counter More...

#define	XEMACPS_1588_ADJ_OFFSET 0x000001D8U
	1588 nanosecond adjustment counter More...

#define	XEMACPS_1588_INC_OFFSET 0x000001DCU
	1588 nanosecond increment counter More...

#define	XEMACPS_PTP_TXSEC_OFFSET 0x000001E0U
	1588 PTP transmit second counter More...

#define	XEMACPS_PTP_TXNANOSEC_OFFSET 0x000001E4U
	1588 PTP transmit nanosecond counter More...

#define	XEMACPS_PTP_RXSEC_OFFSET 0x000001E8U
	1588 PTP receive second counter More...

#define	XEMACPS_PTP_RXNANOSEC_OFFSET 0x000001ECU
	1588 PTP receive nanosecond counter More...

#define	XEMACPS_PTPP_TXSEC_OFFSET 0x000001F0U
	1588 PTP peer transmit second counter More...

#define	XEMACPS_PTPP_TXNANOSEC_OFFSET 0x000001F4U
	1588 PTP peer transmit nanosecond counter More...

#define	XEMACPS_PTPP_RXSEC_OFFSET 0x000001F8U
	1588 PTP peer receive second counter More...

#define	XEMACPS_PTPP_RXNANOSEC_OFFSET 0x000001FCU
	1588 PTP peer receive nanosecond counter More...

#define	XEMACPS_INTQ1_STS_OFFSET 0x00000400U
	Interrupt Q1 Status reg. More...

#define	XEMACPS_TXQ1BASE_OFFSET 0x00000440U
	TX Q1 Base address reg. More...

#define	XEMACPS_RXQ1BASE_OFFSET 0x00000480U
	RX Q1 Base address reg. More...

#define	XEMACPS_DMA_RXQ1_BUFSIZE_OFFSET 0x000004A0U
	RX Q1 DMA buffer size reg. More...

#define	XEMACPS_MSBBUF_TXQBASE_OFFSET 0x000004C8U
	MSB Buffer TX Q Base reg. More...

#define	XEMACPS_MSBBUF_RXQBASE_OFFSET 0x000004D4U
	MSB Buffer RX Q Base reg. More...

#define	XEMACPS_INTQ1_IER_OFFSET 0x00000600U
	Interrupt Q1 Enable reg. More...

#define	XEMACPS_INTQ1_IDR_OFFSET 0x00000620U
	Interrupt Q1 Disable reg. More...

#define	XEMACPS_INTQ1_IMR_OFFSET 0x00000640U
	Interrupt Q1 Mask reg. More...

#define	XEMACPS_BD_ADDR_OFFSET 0x00000000U
	word 0/addr of BDs More...

#define	XEMACPS_BD_STAT_OFFSET 0x00000004U
	word 1/status of BDs More...

#define	XEMACPS_BD_ADDR_HI_OFFSET 0x00000008U
	word 2/addr of BDs More...

#define	XEMACPS_TXBUF_USED_MASK 0x80000000U
	Used bit. More...

#define	XEMACPS_TXBUF_WRAP_MASK 0x40000000U
	Wrap bit, last descriptor. More...

#define	XEMACPS_TXBUF_RETRY_MASK 0x20000000U
	Retry limit exceeded. More...

#define	XEMACPS_TXBUF_URUN_MASK 0x10000000U
	Transmit underrun occurred. More...

#define	XEMACPS_TXBUF_EXH_MASK 0x08000000U
	Buffers exhausted. More...

#define	XEMACPS_TXBUF_TCP_MASK 0x04000000U
	Late collision. More...

#define	XEMACPS_TXBUF_NOCRC_MASK 0x00010000U
	No CRC. More...

#define	XEMACPS_TXBUF_LAST_MASK 0x00008000U
	Last buffer. More...

#define	XEMACPS_TXBUF_LEN_MASK 0x00003FFFU
	Mask for length field. More...

#define	XEMACPS_RXBUF_BCAST_MASK 0x80000000U
	Broadcast frame. More...

#define	XEMACPS_RXBUF_MULTIHASH_MASK 0x40000000U
	Multicast hashed frame. More...

#define	XEMACPS_RXBUF_UNIHASH_MASK 0x20000000U
	Unicast hashed frame. More...

#define	XEMACPS_RXBUF_EXH_MASK 0x08000000U
	buffer exhausted More...

#define	XEMACPS_RXBUF_AMATCH_MASK 0x06000000U
	Specific address matched. More...

#define	XEMACPS_RXBUF_IDFOUND_MASK 0x01000000U
	Type ID matched. More...

#define	XEMACPS_RXBUF_IDMATCH_MASK 0x00C00000U
	ID matched mask. More...

#define	XEMACPS_RXBUF_VLAN_MASK 0x00200000U
	VLAN tagged. More...

#define	XEMACPS_RXBUF_PRI_MASK 0x00100000U
	Priority tagged. More...

#define	XEMACPS_RXBUF_VPRI_MASK 0x000E0000U
	Vlan priority. More...

#define	XEMACPS_RXBUF_CFI_MASK 0x00010000U
	CFI frame. More...

#define	XEMACPS_RXBUF_EOF_MASK 0x00008000U
	End of frame. More...

#define	XEMACPS_RXBUF_SOF_MASK 0x00004000U
	Start of frame. More...

#define	XEMACPS_RXBUF_LEN_MASK 0x00001FFFU
	Mask for length field. More...

#define	XEMACPS_RXBUF_LEN_JUMBO_MASK 0x00003FFFU
	Mask for jumbo length. More...

#define	XEMACPS_RXBUF_WRAP_MASK 0x00000002U
	Wrap bit, last BD. More...

#define	XEMACPS_RXBUF_NEW_MASK 0x00000001U
	Used bit. More...

#define	XEMACPS_RXBUF_ADD_MASK 0xFFFFFFFCU
	Mask for address. More...

#define	XEmacPs_ReadReg(BaseAddress, RegOffset) XEmacPs_In32((BaseAddress) + (u32)(RegOffset))
	Read the given register. More...

#define	XEmacPs_WriteReg(BaseAddress, RegOffset, Data) XEmacPs_Out32((BaseAddress) + (u32)(RegOffset), (u32)(Data))
	Write the given register. More...

Typedefs
typedef struct XEmacPs_Instance	XEmacPs
	The XEmacPs driver instance data. More...

typedef u32	XEmacPs_Bd [XEMACPS_BD_NUM_WORDS]
	The XEmacPs_Bd is the type for buffer descriptors (BDs). More...

Functions
void	XEmacPs_StubHandler (void)
	This is a stub for the asynchronous callbacks. More...

LONG	XEmacPs_CfgInitialize (XEmacPs InstancePtr, XEmacPs_Config CfgPtr, UINTPTR EffectiveAddress)
	Initialize a specific XEmacPs instance/driver. More...

void	XEmacPs_Start (XEmacPs *InstancePtr)
	Start the Ethernet controller as follows: More...

void	XEmacPs_Stop (XEmacPs *InstancePtr)
	Gracefully stop the Ethernet MAC as follows: More...

void	XEmacPs_Reset (XEmacPs *InstancePtr)
	Perform a graceful reset of the Ethernet MAC. More...

void	XEmacPs_SetQueuePtr (XEmacPs *InstancePtr, UINTPTR QPtr, u8 QueueNum, u16 Direction)
	This function sets the start address of the transmit/receive buffer queue. More...

XEmacPs_Config *	XEmacPs_LookupConfig (u16 DeviceId)
	Lookup the device configuration based on the unique device ID. More...

LONG	XEmacPs_SetHandler (XEmacPs InstancePtr, u32 HandlerType, void FuncPointer, void *CallBackRef)
	Install an asynchronous handler function for the given HandlerType: More...

void	XEmacPs_IntrHandler (void *XEmacPsPtr)
	Master interrupt handler for EMAC driver. More...

LONG	XEmacPs_SetOptions (XEmacPs *InstancePtr, u32 Options)
	Set options for the driver/device. More...

LONG	XEmacPs_ClearOptions (XEmacPs *InstancePtr, u32 Options)
	Clear options for the driver/device. More...

u32	XEmacPs_GetOptions (XEmacPs *InstancePtr)
	Get current option settings. More...

LONG	XEmacPs_SetMacAddress (XEmacPs InstancePtr, void AddressPtr, u8 Index)
	Set the MAC address for this driver/device. More...

LONG	XEmacPs_DeleteHash (XEmacPs InstancePtr, void AddressPtr)
	Delete 48-bit MAC addresses in hash table. More...

void	XEmacPs_GetMacAddress (XEmacPs InstancePtr, void AddressPtr, u8 Index)
	Get the MAC address for this driver/device. More...

LONG	XEmacPs_SetHash (XEmacPs InstancePtr, void AddressPtr)
	Set 48-bit MAC addresses in hash table. More...

void	XEmacPs_ClearHash (XEmacPs *InstancePtr)
	Clear the Hash registers for the mac address pointed by AddressPtr. More...

void	XEmacPs_GetHash (XEmacPs InstancePtr, void AddressPtr)
	Get the Hash address for this driver/device. More...

void	XEmacPs_SetMdioDivisor (XEmacPs *InstancePtr, XEmacPs_MdcDiv Divisor)
	Set the MDIO clock divisor. More...

void	XEmacPs_SetOperatingSpeed (XEmacPs *InstancePtr, u16 Speed)
	XEmacPs_SetOperatingSpeed sets the current operating link speed. More...

u16	XEmacPs_GetOperatingSpeed (XEmacPs *InstancePtr)
	XEmacPs_GetOperatingSpeed gets the current operating link speed. More...

LONG	XEmacPs_PhyRead (XEmacPs InstancePtr, u32 PhyAddress, u32 RegisterNum, u16 PhyDataPtr)
	Read the current value of the PHY register indicated by the PhyAddress and the RegisterNum parameters. More...

LONG	XEmacPs_PhyWrite (XEmacPs *InstancePtr, u32 PhyAddress, u32 RegisterNum, u16 PhyData)
	Write data to the specified PHY register. More...

LONG	XEmacPs_SetTypeIdCheck (XEmacPs *InstancePtr, u32 Id_Check, u8 Index)
	Set the Type ID match for this driver/device. More...

LONG	XEmacPs_SendPausePacket (XEmacPs *InstancePtr)
	Send a pause packet. More...

void	XEmacPs_DMABLengthUpdate (XEmacPs *InstancePtr, s32 BLength)
	API to update the Burst length in the DMACR register. More...

LONG	XEmacPs_BdRingCreate (XEmacPs_BdRing *RingPtr, UINTPTR PhysAddr, UINTPTR VirtAddr, u32 Alignment, u32 BdCount)
	Using a memory segment allocated by the caller, create and setup the BD list for the given DMA channel. More...

LONG	XEmacPs_BdRingClone (XEmacPs_BdRing RingPtr, XEmacPs_Bd SrcBdPtr, u8 Direction)
	Clone the given BD into every BD in the list. More...

LONG	XEmacPs_BdRingAlloc (XEmacPs_BdRing RingPtr, u32 NumBd, XEmacPs_Bd *BdSetPtr)
	Reserve locations in the BD list. More...

LONG	XEmacPs_BdRingUnAlloc (XEmacPs_BdRing RingPtr, u32 NumBd, XEmacPs_Bd BdSetPtr)
	Fully or partially undo an XEmacPs_BdRingAlloc() operation. More...

LONG	XEmacPs_BdRingToHw (XEmacPs_BdRing RingPtr, u32 NumBd, XEmacPs_Bd BdSetPtr)
	Enqueue a set of BDs to hardware that were previously allocated by XEmacPs_BdRingAlloc(). More...

u32	XEmacPs_BdRingFromHwTx (XEmacPs_BdRing RingPtr, u32 BdLimit, XEmacPs_Bd *BdSetPtr)
	Returns a set of BD(s) that have been processed by hardware. More...

u32	XEmacPs_BdRingFromHwRx (XEmacPs_BdRing RingPtr, u32 BdLimit, XEmacPs_Bd *BdSetPtr)
	Returns a set of BD(s) that have been processed by hardware. More...

LONG	XEmacPs_BdRingFree (XEmacPs_BdRing RingPtr, u32 NumBd, XEmacPs_Bd BdSetPtr)
	Frees a set of BDs that had been previously retrieved with XEmacPs_BdRingFromHw(). More...

LONG	XEmacPs_BdRingCheck (XEmacPs_BdRing *RingPtr, u8 Direction)
	Check the internal data structures of the BD ring for the provided channel. More...

void	XEmacPs_BdRingPtrReset (XEmacPs_BdRing RingPtr, void virtaddrloc)
	Reset BD ring head and tail pointers. More...

void	XEmacPs_ResetHw (u32 BaseAddr)
	This function perform the reset sequence to the given emacps interface by configuring the appropriate control bits in the emacps specific registers. More...

u32	XEmacPs_GetQxOffset (XEmacPs_QxRegOffset RegName, u8 Queue)
	The register offset of a specific queue register is returned by this function. More...

Configuration options
Device configuration options. See the XEmacPs_SetOptions(), XEmacPs_ClearOptions() and XEmacPs_GetOptions() for information on how to use options. The default state of the options are noted and are what the device and driver will be set to after calling XEmacPs_Reset() or XEmacPs_Initialize().
#define	XEMACPS_PROMISC_OPTION 0x00000001U
	Accept all incoming packets. More...

#define	XEMACPS_FRAME1536_OPTION 0x00000002U
	Frame larger than 1516 support for Tx & Rx. More...

#define	XEMACPS_VLAN_OPTION 0x00000004U
	VLAN Rx & Tx frame support. More...

#define	XEMACPS_FLOW_CONTROL_OPTION 0x00000010U
	Enable recognition of flow control frames on Rx This option defaults to enabled (set) More...

#define	XEMACPS_FCS_STRIP_OPTION 0x00000020U
	Strip FCS and PAD from incoming frames. More...

#define	XEMACPS_FCS_INSERT_OPTION 0x00000040U
	Generate FCS field and add PAD automatically for outgoing frames. More...

#define	XEMACPS_LENTYPE_ERR_OPTION 0x00000080U
	Enable Length/Type error checking for incoming frames. More...

#define	XEMACPS_TRANSMITTER_ENABLE_OPTION 0x00000100U
	Enable the transmitter. More...

#define	XEMACPS_RECEIVER_ENABLE_OPTION 0x00000200U
	Enable the receiver This option defaults to enabled (set) More...

#define	XEMACPS_BROADCAST_OPTION 0x00000400U
	Allow reception of the broadcast address This option defaults to enabled (set) More...

#define	XEMACPS_MULTICAST_OPTION 0x00000800U
	Allows reception of multicast addresses programmed into hash This option defaults to disabled (clear) More...

#define	XEMACPS_RX_CHKSUM_ENABLE_OPTION 0x00001000U
	Enable the RX checksum offload This option defaults to enabled (set) More...

#define	XEMACPS_TX_CHKSUM_ENABLE_OPTION 0x00002000U
	Enable the TX checksum offload This option defaults to enabled (set) More...

#define	XEMACPS_JUMBO_ENABLE_OPTION 0x00004000U

#define	XEMACPS_SGMII_ENABLE_OPTION 0x00008000U

#define	XEMACPS_DEFAULT_OPTIONS
	Default options set when device is initialized or reset. More...

Callback identifiers
These constants are used as parameters to XEmacPs_SetHandler()
#define	XEMACPS_HANDLER_DMASEND 1U

#define	XEMACPS_HANDLER_DMARECV 2U

#define	XEMACPS_HANDLER_ERROR 3U

Typedefs for callback functions
These callbacks are invoked in interrupt context.
typedef void(*	XEmacPs_Handler )(void *CallBackRef)
	Callback invoked when frame(s) have been sent or received in interrupt driven DMA mode. More...

typedef void(*	XEmacPs_ErrHandler )(void *CallBackRef, u8 Direction, u32 ErrorWord)
	Callback when an asynchronous error occurs. More...

Direction identifiers
These are used by several functions and callbacks that need to specify whether an operation specifies a send or receive channel.
#define	XEMACPS_SEND 1U
	send direction More...

#define	XEMACPS_RECV 2U
	receive direction More...

MDC clock division
currently supporting 8, 16, 32, 48, 64, 96, 128, 224.
enum	XEmacPs_MdcDiv

network control register bit definitions
#define	XEMACPS_NWCTRL_FLUSH_DPRAM_MASK 0x00040000U
	Flush a packet from Rx SRAM. More...

#define	XEMACPS_NWCTRL_ZEROPAUSETX_MASK 0x00000800U
	Transmit zero quantum pause frame. More...

#define	XEMACPS_NWCTRL_PAUSETX_MASK 0x00000800U
	Transmit pause frame. More...

#define	XEMACPS_NWCTRL_HALTTX_MASK 0x00000400U
	Halt transmission after current frame. More...

#define	XEMACPS_NWCTRL_STARTTX_MASK 0x00000200U
	Start tx (tx_go) More...

#define	XEMACPS_NWCTRL_STATWEN_MASK 0x00000080U
	Enable writing to stat counters. More...

#define	XEMACPS_NWCTRL_STATINC_MASK 0x00000040U
	Increment statistic registers. More...

#define	XEMACPS_NWCTRL_STATCLR_MASK 0x00000020U
	Clear statistic registers. More...

#define	XEMACPS_NWCTRL_MDEN_MASK 0x00000010U
	Enable MDIO port. More...

#define	XEMACPS_NWCTRL_TXEN_MASK 0x00000008U
	Enable transmit. More...

#define	XEMACPS_NWCTRL_RXEN_MASK 0x00000004U
	Enable receive. More...

#define	XEMACPS_NWCTRL_LOOPEN_MASK 0x00000002U
	local loopback More...

network configuration register bit definitions
#define	XEMACPS_NWCFG_BADPREAMBEN_MASK 0x20000000U
	disable rejection of non-standard preamble More...

#define	XEMACPS_NWCFG_IPDSTRETCH_MASK 0x10000000U
	enable transmit IPG More...

#define	XEMACPS_NWCFG_SGMIIEN_MASK 0x08000000U
	SGMII Enable. More...

#define	XEMACPS_NWCFG_FCSIGNORE_MASK 0x04000000U
	disable rejection of FCS error More...

#define	XEMACPS_NWCFG_HDRXEN_MASK 0x02000000U
	RX half duplex. More...

#define	XEMACPS_NWCFG_RXCHKSUMEN_MASK 0x01000000U
	enable RX checksum offload More...

#define	XEMACPS_NWCFG_PAUSECOPYDI_MASK 0x00800000U
	Do not copy pause Frames to memory. More...

#define	XEMACPS_NWCFG_DWIDTH_64_MASK 0x00200000U
	64 bit Data bus width More...

#define	XEMACPS_NWCFG_MDC_SHIFT_MASK 18U
	shift bits for MDC More...

#define	XEMACPS_NWCFG_MDCCLKDIV_MASK 0x001C0000U
	MDC Mask PCLK divisor. More...

#define	XEMACPS_NWCFG_FCSREM_MASK 0x00020000U
	Discard FCS from received frames. More...

#define	XEMACPS_NWCFG_LENERRDSCRD_MASK 0x00010000U
	RX length error discard. More...

#define	XEMACPS_NWCFG_RXOFFS_MASK 0x0000C000U
	RX buffer offset. More...

#define	XEMACPS_NWCFG_PAUSEEN_MASK 0x00002000U
	Enable pause RX. More...

#define	XEMACPS_NWCFG_RETRYTESTEN_MASK 0x00001000U
	Retry test. More...

#define	XEMACPS_NWCFG_XTADDMACHEN_MASK 0x00000200U
	External address match enable. More...

#define	XEMACPS_NWCFG_PCSSEL_MASK 0x00000800U
	PCS Select. More...

#define	XEMACPS_NWCFG_1000_MASK 0x00000400U
	1000 Mbps More...

#define	XEMACPS_NWCFG_1536RXEN_MASK 0x00000100U
	Enable 1536 byte frames reception. More...

#define	XEMACPS_NWCFG_UCASTHASHEN_MASK 0x00000080U
	Receive unicast hash frames. More...

#define	XEMACPS_NWCFG_MCASTHASHEN_MASK 0x00000040U
	Receive multicast hash frames. More...

#define	XEMACPS_NWCFG_BCASTDI_MASK 0x00000020U
	Do not receive broadcast frames. More...

#define	XEMACPS_NWCFG_COPYALLEN_MASK 0x00000010U
	Copy all frames. More...

#define	XEMACPS_NWCFG_JUMBO_MASK 0x00000008U
	Jumbo frames. More...

#define	XEMACPS_NWCFG_NVLANDISC_MASK 0x00000004U
	Receive only VLAN frames. More...

#define	XEMACPS_NWCFG_FDEN_MASK 0x00000002U
	full duplex More...

#define	XEMACPS_NWCFG_100_MASK 0x00000001U
	100 Mbps More...

#define	XEMACPS_NWCFG_RESET_MASK 0x00080000U
	reset value More...

network status register bit definitaions
#define	XEMACPS_NWSR_MDIOIDLE_MASK 0x00000004U
	PHY management idle. More...

#define	XEMACPS_NWSR_MDIO_MASK 0x00000002U
	Status of mdio_in. More...

MAC address register word 1 mask
#define	XEMACPS_LADDR_MACH_MASK 0x0000FFFFU
	Address bits[47:32] bit[31:0] are in BOTTOM. More...

DMA control register bit definitions
#define	XEMACPS_DMACR_ADDR_WIDTH_64 0x40000000U
	64 bit address bus More...

#define	XEMACPS_DMACR_TXEXTEND_MASK 0x20000000U
	Tx Extended desc mode. More...

#define	XEMACPS_DMACR_RXEXTEND_MASK 0x10000000U
	Rx Extended desc mode. More...

#define	XEMACPS_DMACR_RXBUF_MASK 0x00FF0000U
	Mask bit for RX buffer size. More...

#define	XEMACPS_DMACR_RXBUF_SHIFT 16U
	Shift bit for RX buffer size. More...

#define	XEMACPS_DMACR_TCPCKSUM_MASK 0x00000800U
	enable/disable TX checksum offload More...

#define	XEMACPS_DMACR_TXSIZE_MASK 0x00000400U
	TX buffer memory size. More...

#define	XEMACPS_DMACR_RXSIZE_MASK 0x00000300U
	RX buffer memory size. More...

#define	XEMACPS_DMACR_ENDIAN_MASK 0x00000080U
	endian configuration More...

#define	XEMACPS_DMACR_BLENGTH_MASK 0x0000001FU
	buffer burst length More...

#define	XEMACPS_DMACR_SINGLE_AHB_BURST 0x00000001U
	single AHB bursts More...

#define	XEMACPS_DMACR_INCR4_AHB_BURST 0x00000004U
	4 bytes AHB bursts More...

#define	XEMACPS_DMACR_INCR8_AHB_BURST 0x00000008U
	8 bytes AHB bursts More...

#define	XEMACPS_DMACR_INCR16_AHB_BURST 0x00000010U
	16 bytes AHB bursts More...

transmit status register bit definitions
#define	XEMACPS_TXSR_HRESPNOK_MASK 0x00000100U
	Transmit hresp not OK. More...

#define	XEMACPS_TXSR_URUN_MASK 0x00000040U
	Transmit underrun. More...

#define	XEMACPS_TXSR_TXCOMPL_MASK 0x00000020U
	Transmit completed OK. More...

#define	XEMACPS_TXSR_BUFEXH_MASK 0x00000010U
	Transmit buffs exhausted mid frame. More...

#define	XEMACPS_TXSR_TXGO_MASK 0x00000008U
	Status of go flag. More...

#define	XEMACPS_TXSR_RXOVR_MASK 0x00000004U
	Retry limit exceeded. More...

#define	XEMACPS_TXSR_FRAMERX_MASK 0x00000002U
	Collision tx frame. More...

#define	XEMACPS_TXSR_USEDREAD_MASK 0x00000001U
	TX buffer used bit set. More...

#define	XEMACPS_TXSR_ERROR_MASK

receive status register bit definitions
#define	XEMACPS_RXSR_HRESPNOK_MASK 0x00000008U
	Receive hresp not OK. More...

#define	XEMACPS_RXSR_RXOVR_MASK 0x00000004U
	Receive overrun. More...

#define	XEMACPS_RXSR_FRAMERX_MASK 0x00000002U
	Frame received OK. More...

#define	XEMACPS_RXSR_BUFFNA_MASK 0x00000001U
	RX buffer used bit set. More...

#define	XEMACPS_RXSR_ERROR_MASK

#define	XEMACPS_SR_ALL_MASK 0xFFFFFFFFU
	Mask for full register. More...

PCS control register bit definitions
#define	XEMACPS_PCS_CON_AUTO_NEG_MASK 0x00001000U
	Auto-negotiation. More...

PCS status register bit definitions
#define	XEMACPS_PCS_STATUS_LINK_STATUS_MASK 0x00000004U
	Link status. More...

Interrupt Q1 status register bit definitions
#define	XEMACPS_INTQ1SR_TXCOMPL_MASK 0x00000080U
	Transmit completed OK. More...

#define	XEMACPS_INTQ1SR_TXERR_MASK 0x00000040U
	Transmit AMBA Error. More...

#define	XEMACPS_INTQ1SR_RXCOMPL_MASK 0x00000002U
	Receive completed OK. More...

#define	XEMACPS_INTQ1_IXR_ALL_MASK

#define	XEMACPS_INTQ1_IXR_TX_MASK

#define	XEMACPS_INTQ1_IXR_RX_MASK (u32)XEMACPS_INTQ1SR_RXCOMPL_MASK

#define	XEMACPS_INTQISR_RXCOMPL_MASK XEMACPS_INTQ1SR_RXCOMPL_MASK

#define	XEMACPS_INTQISR_TXCOMPL_MASK XEMACPS_INTQ1SR_TXCOMPL_MASK

#define	XEMACPS_INTQSR_TXERR_MASK XEMACPS_INTQ1SR_TXERR_MASK

#define	XEMACPS_INTQ_IXR_ALL_MASK XEMACPS_INTQ1_IXR_ALL_MASK

interrupts bit definitions
Bits definitions are same in XEMACPS_ISR_OFFSET, XEMACPS_IER_OFFSET, XEMACPS_IDR_OFFSET, and XEMACPS_IMR_OFFSET
#define	XEMACPS_IXR_PTPPSTX_MASK 0x02000000U
	PTP Pdelay_resp TXed. More...

#define	XEMACPS_IXR_PTPPDRTX_MASK 0x01000000U
	PTP Pdelay_req TXed. More...

#define	XEMACPS_IXR_PTPPSRX_MASK 0x00800000U
	PTP Pdelay_resp RXed. More...

#define	XEMACPS_IXR_PTPPDRRX_MASK 0x00400000U
	PTP Pdelay_req RXed. More...

#define	XEMACPS_IXR_PTPSTX_MASK 0x00200000U
	PTP Sync TXed. More...

#define	XEMACPS_IXR_PTPDRTX_MASK 0x00100000U
	PTP Delay_req TXed. More...

#define	XEMACPS_IXR_PTPSRX_MASK 0x00080000U
	PTP Sync RXed. More...

#define	XEMACPS_IXR_PTPDRRX_MASK 0x00040000U
	PTP Delay_req RXed. More...

#define	XEMACPS_IXR_PAUSETX_MASK 0x00004000U
	Pause frame transmitted. More...

#define	XEMACPS_IXR_PAUSEZERO_MASK 0x00002000U
	Pause time has reached zero. More...

#define	XEMACPS_IXR_PAUSENZERO_MASK 0x00001000U
	Pause frame received. More...

#define	XEMACPS_IXR_HRESPNOK_MASK 0x00000800U
	hresp not ok More...

#define	XEMACPS_IXR_RXOVR_MASK 0x00000400U
	Receive overrun occurred. More...

#define	XEMACPS_IXR_TXCOMPL_MASK 0x00000080U
	Frame transmitted ok. More...

#define	XEMACPS_IXR_TXEXH_MASK 0x00000040U
	Transmit err occurred or no buffers. More...

#define	XEMACPS_IXR_RETRY_MASK 0x00000020U
	Retry limit exceeded. More...

#define	XEMACPS_IXR_URUN_MASK 0x00000010U
	Transmit underrun. More...

#define	XEMACPS_IXR_TXUSED_MASK 0x00000008U
	Tx buffer used bit read. More...

#define	XEMACPS_IXR_RXUSED_MASK 0x00000004U
	Rx buffer used bit read. More...

#define	XEMACPS_IXR_FRAMERX_MASK 0x00000002U
	Frame received ok. More...

#define	XEMACPS_IXR_MGMNT_MASK 0x00000001U
	PHY management complete. More...

#define	XEMACPS_IXR_ALL_MASK 0x00007FFFU
	Everything! More...

#define	XEMACPS_IXR_TX_ERR_MASK

#define	XEMACPS_IXR_RX_ERR_MASK

PHY Maintenance bit definitions
#define	XEMACPS_PHYMNTNC_OP_MASK 0x40020000U
	operation mask bits More...

#define	XEMACPS_PHYMNTNC_OP_R_MASK 0x20000000U
	read operation More...

#define	XEMACPS_PHYMNTNC_OP_W_MASK 0x10000000U
	write operation More...

#define	XEMACPS_PHYMNTNC_ADDR_MASK 0x0F800000U
	Address bits. More...

#define	XEMACPS_PHYMNTNC_REG_MASK 0x007C0000U
	register bits More...

#define	XEMACPS_PHYMNTNC_DATA_MASK 0x00000FFFU
	data bits More...

#define	XEMACPS_PHYMNTNC_PHAD_SHFT_MSK 23U
	Shift bits for PHYAD. More...

#define	XEMACPS_PHYMNTNC_PREG_SHFT_MSK 18U
	Shift bits for PHREG. More...

RX watermark bit definitions
#define	XEMACPS_RXWM_HIGH_MASK 0x0000FFFFU
	RXWM high mask. More...

#define	XEMACPS_RXWM_LOW_MASK 0xFFFF0000U
	RXWM low mask. More...

#define	XEMACPS_RXWM_LOW_SHFT_MSK 16U
	Shift for RXWM low. More...

Screening Type2 bit definitions
#define	XEMACPS_CMPA_ENABLE_MASK 0x00040000U
	Enable Compare A. More...

#define	XEMACPS_CMPA_MASK 0x0003E000U
	Compare reg number. More...

Queue Registers Offset
enum	XEmacPs_QxRegOffset

#define	MAX_QUEUES_FEASIBLE 2 /* Max queues possible on latest device */

Macro Definition Documentation

#define XEMACPS_1588_ADJ_OFFSET 0x000001D8U

1588 nanosecond adjustment counter

#define XEMACPS_1588_INC_OFFSET 0x000001DCU

1588 nanosecond increment counter

#define XEMACPS_1588_NANOSEC_OFFSET 0x000001D4U

1588 nanosecond counter

#define XEMACPS_1588_SEC_OFFSET 0x000001D0U

1588 second counter

#define XEMACPS_BD_ADDR_HI_OFFSET 0x00000008U

word 2/addr of BDs

#define XEMACPS_BD_ADDR_OFFSET 0x00000000U

word 0/addr of BDs

Referenced by XEmacPs_BdRingCheck().

#define XEMACPS_BD_ALIGNMENT 4U

Minimum buffer descriptor alignment on the local bus.

Referenced by EmacPsDmaIntrExample().

#define XEMACPS_BD_STAT_OFFSET 0x00000004U

word 1/status of BDs

Referenced by XEmacPs_BdRingFromHwRx(), and XEmacPs_BdRingFromHwTx().

#define XEmacPs_BdClear ( BdPtr ) memset((BdPtr), 0, sizeof(XEmacPs_Bd))

Zero out BD fields.

Parameters

BdPtr is the BD pointer to operate on

Returns: Nothing

Note: C-style signature: void XEmacPs_BdClear(XEmacPs_Bd* BdPtr)

Referenced by EmacPsDmaIntrExample(), and EmacPsDmaSingleFrameIntrExample().

#define XEmacPs_BdClearLast ( BdPtr )

Value:

(XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET,             \
    XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) &             \
    ~XEMACPS_TXBUF_LAST_MASK))

Tell the DMA engine that the current packet does not end with the given BD.

Parameters

BdPtr is the BD pointer to operate on

Note: C-style signature: void XEmacPs_BdClearLast(XEmacPs_Bd* BdPtr)

#define XEmacPs_BdClearTxNoCRC ( BdPtr )

Value:

(XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET,             \
    XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) &             \
    ~XEMACPS_TXBUF_NOCRC_MASK))

Clear this bit, CRC will be appended to the current frame.

This control bit must be set for the first buffer in a frame and will be ignored for the subsequent buffers of a frame.

Parameters

BdPtr is the BD pointer to operate on

Note: This bit must be clear when using the transmit checksum generation offload, otherwise checksum generation and substitution will not occur.

C-style signature: UINTPTR XEmacPs_BdClearTxNoCRC(XEmacPs_Bd* BdPtr)

#define XEmacPs_BdClearTxUsed ( BdPtr )

Value:

(XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET,             \
    XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) &             \
    ~XEMACPS_TXBUF_USED_MASK))

Software clears this bit to enable the buffer to be read by the hardware.

Hardware sets this bit for the first buffer of a frame once it has been successfully transmitted. This macro clears this bit of transmit BD.

Parameters

BdPtr is the BD pointer to operate on

Note: C-style signature: void XEmacPs_BdClearTxUsed(XEmacPs_Bd* BdPtr)

Referenced by EmacPsDmaSingleFrameIntrExample().

#define XEmacPs_BdGetBufAddr ( BdPtr ) (XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & XEMACPS_RXBUF_ADD_MASK)

Get the address (bits 0..31) of the BD's buffer address (word 0)

Parameters

BdPtr is the BD pointer to operate on

Note: C-style signature: UINTPTR XEmacPs_BdGetBufAddr(XEmacPs_Bd* BdPtr)

#define XEmacPs_BdGetLength ( BdPtr )

Value:

(XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \

XEMACPS_RXBUF_LEN_MASK)

XEmacPs_BdRead

#define XEmacPs_BdRead(BaseAddress, Offset)

Read the given Buffer Descriptor word.

Definition: xemacps_bd.h:121

XEMACPS_RXBUF_LEN_MASK

#define XEMACPS_RXBUF_LEN_MASK

Mask for length field.

Definition: xemacps_hw.h:719

XEMACPS_BD_STAT_OFFSET

#define XEMACPS_BD_STAT_OFFSET

word 1/status of BDs

Definition: xemacps_hw.h:664

Retrieve the BD length field.

For Tx channels, the returned value is the same as that written with XEmacPs_BdSetLength().

For Rx channels, the returned value is the size of the received packet.

Parameters

BdPtr is the BD pointer to operate on

Returns: Length field processed by hardware or set by XEmacPs_BdSetLength().

Note: C-style signature: UINTPTR XEmacPs_BdGetLength(XEmacPs_Bd* BdPtr) XEAMCPS_RXBUF_LEN_MASK is same as XEMACPS_TXBUF_LEN_MASK.

Referenced by EmacPsDmaSingleFrameIntrExample().

#define XEmacPs_BdGetStatus ( BdPtr ) XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET)

Retrieve the BD's Packet DMA transfer status word (word 1).

Parameters

BdPtr is the BD pointer to operate on

Returns: Status word

Note: C-style signature: u32 XEmacPs_BdGetStatus(XEmacPs_Bd* BdPtr)

Due to the BD bit layout differences in transmit and receive. User's caution is required.

#define XEmacPs_BdIsLast ( BdPtr )

Value:

((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \

XEMACPS_RXBUF_EOF_MASK)!=0U ? TRUE : FALSE)

XEmacPs_BdRead

#define XEmacPs_BdRead(BaseAddress, Offset)

Read the given Buffer Descriptor word.

Definition: xemacps_bd.h:121

XEMACPS_BD_STAT_OFFSET

#define XEMACPS_BD_STAT_OFFSET

word 1/status of BDs

Definition: xemacps_hw.h:664

XEMACPS_RXBUF_EOF_MASK

#define XEMACPS_RXBUF_EOF_MASK

End of frame.

Definition: xemacps_hw.h:717

Test whether the given BD has been marked as the last BD of a packet.

Parameters

BdPtr is the BD pointer to operate on

Returns: TRUE if BD represents the "Last" BD of a packet, FALSE otherwise

Note: C-style signature: UINTPTR XEmacPs_BdIsLast(XEmacPs_Bd* BdPtr)

#define XEmacPs_BdIsRxBcast ( BdPtr )

Value:

((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \

XEMACPS_RXBUF_BCAST_MASK)!=0U ? TRUE : FALSE)

XEmacPs_BdRead

#define XEmacPs_BdRead(BaseAddress, Offset)

Read the given Buffer Descriptor word.

Definition: xemacps_bd.h:121

XEMACPS_BD_STAT_OFFSET

#define XEMACPS_BD_STAT_OFFSET

word 1/status of BDs

Definition: xemacps_hw.h:664

XEMACPS_RXBUF_BCAST_MASK

#define XEMACPS_RXBUF_BCAST_MASK

Broadcast frame.

Definition: xemacps_hw.h:704

Determine the broadcast bit of the receive BD.

Parameters

BdPtr is the BD pointer to operate on

Note: C-style signature: UINTPTR XEmacPs_BdIsRxBcast(XEmacPs_Bd* BdPtr)

#define XEmacPs_BdIsRxCFI ( BdPtr )

Value:

((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \

XEMACPS_RXBUF_CFI_MASK)!=0U ? TRUE : FALSE)

XEmacPs_BdRead

#define XEmacPs_BdRead(BaseAddress, Offset)

Read the given Buffer Descriptor word.

Definition: xemacps_bd.h:121

XEMACPS_RXBUF_CFI_MASK

#define XEMACPS_RXBUF_CFI_MASK

CFI frame.

Definition: xemacps_hw.h:716

XEMACPS_BD_STAT_OFFSET

#define XEMACPS_BD_STAT_OFFSET

word 1/status of BDs

Definition: xemacps_hw.h:664

Determine if the received frame's Concatenation Format Indicator (CFI) of the frames VLANTCI field was set.

Parameters

BdPtr is the BD pointer to operate on

Note: C-style signature: UINTPTR XEmacPs_BdIsRxCFI(XEmacPs_Bd* BdPtr)

#define XEmacPs_BdIsRxEOF ( BdPtr )

Value:

((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \

XEMACPS_RXBUF_EOF_MASK)!=0U ? TRUE : FALSE)

XEmacPs_BdRead

#define XEmacPs_BdRead(BaseAddress, Offset)

Read the given Buffer Descriptor word.

Definition: xemacps_bd.h:121

XEMACPS_BD_STAT_OFFSET

#define XEMACPS_BD_STAT_OFFSET

word 1/status of BDs

Definition: xemacps_hw.h:664

XEMACPS_RXBUF_EOF_MASK

#define XEMACPS_RXBUF_EOF_MASK

End of frame.

Definition: xemacps_hw.h:717

Determine the End Of Frame (EOF) bit of the receive BD.

Parameters

BdPtr is the BD pointer to operate on

Note: C-style signature: UINTPTR XEmacPs_BdGetRxEOF(XEmacPs_Bd* BdPtr)

#define XEmacPs_BdIsRxMultiHash ( BdPtr )

Value:

((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \

XEMACPS_RXBUF_MULTIHASH_MASK)!=0U ? TRUE : FALSE)

XEmacPs_BdRead

#define XEmacPs_BdRead(BaseAddress, Offset)

Read the given Buffer Descriptor word.

Definition: xemacps_bd.h:121

XEMACPS_BD_STAT_OFFSET

#define XEMACPS_BD_STAT_OFFSET

word 1/status of BDs

Definition: xemacps_hw.h:664

XEMACPS_RXBUF_MULTIHASH_MASK

#define XEMACPS_RXBUF_MULTIHASH_MASK

Multicast hashed frame.

Definition: xemacps_hw.h:705

Determine the multicast hash bit of the receive BD.

Parameters

BdPtr is the BD pointer to operate on

Note: C-style signature: UINTPTR XEmacPs_BdIsRxMultiHash(XEmacPs_Bd* BdPtr)

#define XEmacPs_BdIsRxNew ( BdPtr )

Value:

((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \

XEMACPS_RXBUF_NEW_MASK)!=0U ? TRUE : FALSE)

XEmacPs_BdRead

#define XEmacPs_BdRead(BaseAddress, Offset)

Read the given Buffer Descriptor word.

Definition: xemacps_bd.h:121

XEMACPS_RXBUF_NEW_MASK

#define XEMACPS_RXBUF_NEW_MASK

Used bit.

Definition: xemacps_hw.h:723

XEMACPS_BD_ADDR_OFFSET

#define XEMACPS_BD_ADDR_OFFSET

word 0/addr of BDs

Definition: xemacps_hw.h:663

Determine the new bit of the receive BD.

Parameters

BdPtr is the BD pointer to operate on

Note: C-style signature: UINTPTR XEmacPs_BdIsRxNew(XEmacPs_Bd* BdPtr)

Referenced by XEmacPs_BdRingFromHwRx().

#define XEmacPs_BdIsRxPri ( BdPtr )

Value:

((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \

XEMACPS_RXBUF_PRI_MASK)!=0U ? TRUE : FALSE)

XEmacPs_BdRead

#define XEmacPs_BdRead(BaseAddress, Offset)

Read the given Buffer Descriptor word.

Definition: xemacps_bd.h:121

XEMACPS_BD_STAT_OFFSET

#define XEMACPS_BD_STAT_OFFSET

word 1/status of BDs

Definition: xemacps_hw.h:664

XEMACPS_RXBUF_PRI_MASK

#define XEMACPS_RXBUF_PRI_MASK

Priority tagged.

Definition: xemacps_hw.h:714

Determine if the received frame has Type ID of 8100h and null VLAN identifier(Priority tag).

Parameters

BdPtr is the BD pointer to operate on

Note: C-style signature: UINTPTR XEmacPs_BdIsRxPri(XEmacPs_Bd* BdPtr)

#define XEmacPs_BdIsRxSOF ( BdPtr )

Value:

((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \

XEMACPS_RXBUF_SOF_MASK)!=0U ? TRUE : FALSE)

XEmacPs_BdRead

#define XEmacPs_BdRead(BaseAddress, Offset)

Read the given Buffer Descriptor word.

Definition: xemacps_bd.h:121

XEMACPS_RXBUF_SOF_MASK

#define XEMACPS_RXBUF_SOF_MASK

Start of frame.

Definition: xemacps_hw.h:718

XEMACPS_BD_STAT_OFFSET

#define XEMACPS_BD_STAT_OFFSET

word 1/status of BDs

Definition: xemacps_hw.h:664

Determine the Start Of Frame (SOF) bit of the receive BD.

Parameters

BdPtr is the BD pointer to operate on

Note: C-style signature: UINTPTR XEmacPs_BdGetRxSOF(XEmacPs_Bd* BdPtr)

#define XEmacPs_BdIsRxUniHash ( BdPtr )

Value:

((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \

XEMACPS_RXBUF_UNIHASH_MASK)!=0U ? TRUE : FALSE)

XEmacPs_BdRead

#define XEmacPs_BdRead(BaseAddress, Offset)

Read the given Buffer Descriptor word.

Definition: xemacps_bd.h:121

XEMACPS_RXBUF_UNIHASH_MASK

#define XEMACPS_RXBUF_UNIHASH_MASK

Unicast hashed frame.

Definition: xemacps_hw.h:706

XEMACPS_BD_STAT_OFFSET

#define XEMACPS_BD_STAT_OFFSET

word 1/status of BDs

Definition: xemacps_hw.h:664

Determine the unicast hash bit of the receive BD.

Parameters

BdPtr is the BD pointer to operate on

Note: C-style signature: UINTPTR XEmacPs_BdIsRxUniHash(XEmacPs_Bd* BdPtr)

#define XEmacPs_BdIsRxVlan ( BdPtr )

Value:

((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \

XEMACPS_RXBUF_VLAN_MASK)!=0U ? TRUE : FALSE)

XEmacPs_BdRead

#define XEmacPs_BdRead(BaseAddress, Offset)

Read the given Buffer Descriptor word.

Definition: xemacps_bd.h:121

XEMACPS_RXBUF_VLAN_MASK

#define XEMACPS_RXBUF_VLAN_MASK

VLAN tagged.

Definition: xemacps_hw.h:713

XEMACPS_BD_STAT_OFFSET

#define XEMACPS_BD_STAT_OFFSET

word 1/status of BDs

Definition: xemacps_hw.h:664

Determine if the received frame is a VLAN Tagged frame.

Parameters

BdPtr is the BD pointer to operate on

Note: C-style signature: UINTPTR XEmacPs_BdIsRxVlan(XEmacPs_Bd* BdPtr)

#define XEmacPs_BdIsRxWrap ( BdPtr )

Value:

((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \

XEMACPS_RXBUF_WRAP_MASK)!=0U ? TRUE : FALSE)

XEmacPs_BdRead

#define XEmacPs_BdRead(BaseAddress, Offset)

Read the given Buffer Descriptor word.

Definition: xemacps_bd.h:121

XEMACPS_BD_ADDR_OFFSET

#define XEMACPS_BD_ADDR_OFFSET

word 0/addr of BDs

Definition: xemacps_hw.h:663

XEMACPS_RXBUF_WRAP_MASK

#define XEMACPS_RXBUF_WRAP_MASK

Wrap bit, last BD.

Definition: xemacps_hw.h:722

Set this bit to mark the last descriptor in the receive buffer descriptor list.

Parameters

BdPtr is the BD pointer to operate on

Note: C-style signature: void XEmacPs_BdSetRxWrap(XEmacPs_Bd* BdPtr) Determine the wrap bit of the receive BD which indicates end of the BD list.

Parameters

BdPtr is the BD pointer to operate on

Note: C-style signature: u8 XEmacPs_BdIsRxWrap(XEmacPs_Bd* BdPtr)

Referenced by XEmacPs_BdRingCheck().

#define XEmacPs_BdIsTxExh ( BdPtr )

Value:

((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \

XEMACPS_TXBUF_EXH_MASK)!=0U ? TRUE : FALSE)

XEmacPs_BdRead

#define XEmacPs_BdRead(BaseAddress, Offset)

Read the given Buffer Descriptor word.

Definition: xemacps_bd.h:121

XEMACPS_BD_STAT_OFFSET

#define XEMACPS_BD_STAT_OFFSET

word 1/status of BDs

Definition: xemacps_hw.h:664

XEMACPS_TXBUF_EXH_MASK

#define XEMACPS_TXBUF_EXH_MASK

Buffers exhausted.

Definition: xemacps_hw.h:684

Determine if a frame fails to be transmitted due to buffer is exhausted mid-frame.

Parameters

BdPtr is the BD pointer to operate on

Note: C-style signature: UINTPTR XEmacPs_BdIsTxExh(XEmacPs_Bd* BdPtr)

#define XEmacPs_BdIsTxRetry ( BdPtr )

Value:

((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \

XEMACPS_TXBUF_RETRY_MASK)!=0U ? TRUE : FALSE)

XEmacPs_BdRead

#define XEmacPs_BdRead(BaseAddress, Offset)

Read the given Buffer Descriptor word.

Definition: xemacps_bd.h:121

XEMACPS_TXBUF_RETRY_MASK

#define XEMACPS_TXBUF_RETRY_MASK

Retry limit exceeded.

Definition: xemacps_hw.h:682

XEMACPS_BD_STAT_OFFSET

#define XEMACPS_BD_STAT_OFFSET

word 1/status of BDs

Definition: xemacps_hw.h:664

Determine if a frame fails to be transmitted due to too many retries.

Parameters

BdPtr is the BD pointer to operate on

Note: C-style signature: UINTPTR XEmacPs_BdIsTxRetry(XEmacPs_Bd* BdPtr)

#define XEmacPs_BdIsTxUrun ( BdPtr )

Value:

((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \

XEMACPS_TXBUF_URUN_MASK)!=0U ? TRUE : FALSE)

XEmacPs_BdRead

#define XEmacPs_BdRead(BaseAddress, Offset)

Read the given Buffer Descriptor word.

Definition: xemacps_bd.h:121

XEMACPS_BD_STAT_OFFSET

#define XEMACPS_BD_STAT_OFFSET

word 1/status of BDs

Definition: xemacps_hw.h:664

XEMACPS_TXBUF_URUN_MASK

#define XEMACPS_TXBUF_URUN_MASK

Transmit underrun occurred.

Definition: xemacps_hw.h:683

Determine if a frame fails to be transmitted due to data can not be feteched in time or buffers are exhausted.

Parameters

BdPtr is the BD pointer to operate on

Note: C-style signature: UINTPTR XEmacPs_BdIsTxUrun(XEmacPs_Bd* BdPtr)

#define XEmacPs_BdIsTxUsed ( BdPtr )

Value:

((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \

XEMACPS_TXBUF_USED_MASK)!=0U ? TRUE : FALSE)

XEMACPS_TXBUF_USED_MASK

#define XEMACPS_TXBUF_USED_MASK

Used bit.

Definition: xemacps_hw.h:680

XEmacPs_BdRead

#define XEmacPs_BdRead(BaseAddress, Offset)

Read the given Buffer Descriptor word.

Definition: xemacps_bd.h:121

XEMACPS_BD_STAT_OFFSET

#define XEMACPS_BD_STAT_OFFSET

word 1/status of BDs

Definition: xemacps_hw.h:664

Determine the used bit of the transmit BD.

Parameters

BdPtr is the BD pointer to operate on

Note: C-style signature: UINTPTR XEmacPs_BdIsTxUsed(XEmacPs_Bd* BdPtr)

#define XEmacPs_BdIsTxWrap ( BdPtr )

Value:

((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \

XEMACPS_TXBUF_WRAP_MASK)!=0U ? TRUE : FALSE)

XEmacPs_BdRead

#define XEmacPs_BdRead(BaseAddress, Offset)

Read the given Buffer Descriptor word.

Definition: xemacps_bd.h:121

XEMACPS_BD_STAT_OFFSET

#define XEMACPS_BD_STAT_OFFSET

word 1/status of BDs

Definition: xemacps_hw.h:664

XEMACPS_TXBUF_WRAP_MASK

#define XEMACPS_TXBUF_WRAP_MASK

Wrap bit, last descriptor.

Definition: xemacps_hw.h:681

Sets this bit to mark the last descriptor in the transmit buffer descriptor list.

Parameters

BdPtr is the BD pointer to operate on

Note: C-style signature: void XEmacPs_BdSetTxWrap(XEmacPs_Bd* BdPtr) Determine the wrap bit of the transmit BD which indicates end of the BD list.

Parameters

BdPtr is the BD pointer to operate on

Note: C-style signature: u8 XEmacPs_BdGetTxWrap(XEmacPs_Bd* BdPtr)

Referenced by XEmacPs_BdRingCheck().

#define XEmacPs_BdRead	(	BaseAddress,
		Offset
	)	((u32 )((UINTPTR)((void*)(BaseAddress)) + (u32)(Offset)))

Read the given Buffer Descriptor word.

Parameters

BaseAddress	is the base address of the BD to read
Offset	is the word offset to be read

Returns: The 32-bit value of the field

Note: C-style signature: u32 XEmacPs_BdRead(UINTPTR BaseAddress, UINTPTR Offset)

Referenced by XEmacPs_BdRingCheck(), XEmacPs_BdRingFromHwRx(), and XEmacPs_BdRingFromHwTx().

#define XEmacPs_BdRingCntCalc	(	Alignment,
		Bytes
	)	(u32)((Bytes) / (sizeof(XEmacPs_Bd)))

Use this macro at initialization time to determine how many BDs will fit in a BD list within the given memory constraints.

The results of this macro can be provided to XEmacPs_BdRingCreate().

Parameters

Alignment	specifies what byte alignment the BDs must fall on and must be a power of 2 to get an accurate calculation (32, 64, 128,...)
Bytes	is the number of bytes to be used to store BDs.

Returns: Number of BDs that can fit in the given memory area

Note: C-style signature: u32 XEmacPs_BdRingCntCalc(u32 Alignment, u32 Bytes)

#define XEmacPs_BdRingGetCnt ( RingPtr ) ((RingPtr)->AllCnt)

Return the total number of BDs allocated by this channel with XEmacPs_BdRingCreate().

Parameters

RingPtr is the DMA channel to operate on.

Returns: The total number of BDs allocated for this channel.

Note: C-style signature: u32 XEmacPs_BdRingGetCnt(XEmacPs_BdRing* RingPtr)

#define XEmacPs_BdRingGetFreeCnt ( RingPtr ) ((RingPtr)->FreeCnt)

Return the number of BDs allocatable with XEmacPs_BdRingAlloc() for pre- processing.

Parameters

RingPtr is the DMA channel to operate on.

Returns: The number of BDs currently allocatable.

Note: C-style signature: u32 XEmacPs_BdRingGetFreeCnt(XEmacPs_BdRing* RingPtr)

#define XEmacPs_BdRingMemCalc	(	Alignment,
		NumBd
	)	(u32)(sizeof(XEmacPs_Bd) * (NumBd))

Use this macro at initialization time to determine how many bytes of memory is required to contain a given number of BDs at a given alignment.

Parameters

Alignment	specifies what byte alignment the BDs must fall on. This parameter must be a power of 2 to get an accurate calculation (32, 64, 128,...)
NumBd	is the number of BDs to calculate memory size requirements for

Returns: The number of bytes of memory required to create a BD list with the given memory constraints.

Note: C-style signature: u32 XEmacPs_BdRingMemCalc(u32 Alignment, u32 NumBd)

#define XEmacPs_BdRingNext	(	RingPtr,
		BdPtr
	)

Value:

(((UINTPTR)((void *)(BdPtr)) >= (RingPtr)->HighBdAddr) ?                     \
    (XEmacPs_Bd*)((void*)(RingPtr)->BaseBdAddr) :                              \
    (XEmacPs_Bd*)((UINTPTR)((void *)(BdPtr)) + (RingPtr)->Separation))

Return the next BD from BdPtr in a list.

Parameters

RingPtr	is the DMA channel to operate on.
BdPtr	is the BD to operate on.

Returns: The next BD in the list relative to the BdPtr parameter.

Note: C-style signature: XEmacPs_Bd XEmacPs_BdRingNext(XEmacPs_BdRing RingPtr, XEmacPs_Bd *BdPtr)

Referenced by XEmacPs_BdRingFromHwRx(), XEmacPs_BdRingFromHwTx(), and XEmacPs_BdRingToHw().

#define XEmacPs_BdRingPrev	(	RingPtr,
		BdPtr
	)

Value:

(((UINTPTR)(BdPtr) <= (RingPtr)->BaseBdAddr) ?                     \
    (XEmacPs_Bd*)(RingPtr)->HighBdAddr :                              \
    (XEmacPs_Bd*)((UINTPTR)(BdPtr) - (RingPtr)->Separation))

Return the previous BD from BdPtr in the list.

Parameters

RingPtr	is the DMA channel to operate on.
BdPtr	is the BD to operate on

Returns: The previous BD in the list relative to the BdPtr parameter.

Note: C-style signature: XEmacPs_Bd XEmacPs_BdRingPrev(XEmacPs_BdRing RingPtr, XEmacPs_Bd *BdPtr)

#define XEmacPs_BdSetAddressRx	(	BdPtr,
		Addr
	)

Value:

XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET,              \
    ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) &           \
    ~XEMACPS_RXBUF_ADD_MASK) | (UINTPTR)(Addr)))

Set the BD's Address field (word 0).

Parameters

BdPtr	is the BD pointer to operate on
Addr	is the value to write to BD's status field.

Note: : Due to some bits are mixed within receive BD's address field, read-modify-write is performed.

C-style signature: void XEmacPs_BdSetAddressRx(XEmacPs_Bd* BdPtr, UINTPTR Addr)

Referenced by EmacPsDmaSingleFrameIntrExample().

#define XEmacPs_BdSetAddressTx	(	BdPtr,
		Addr
	)	XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, (u32)(Addr))

Set the BD's Address field (word 0).

Parameters

BdPtr	is the BD pointer to operate on
Addr	is the value to write to BD's status field.

Note: :

C-style signature: void XEmacPs_BdSetAddressTx(XEmacPs_Bd* BdPtr, UINTPTR Addr)

Referenced by EmacPsDmaSingleFrameIntrExample().

#define XEmacPs_BdSetLast ( BdPtr )

Value:

(XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET,             \
    XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) |             \
    XEMACPS_TXBUF_LAST_MASK))

Tell the DMA engine that the given transmit BD marks the end of the current packet to be processed.

Parameters

BdPtr is the BD pointer to operate on

Note: C-style signature: void XEmacPs_BdSetLast(XEmacPs_Bd* BdPtr)

Referenced by EmacPsDmaSingleFrameIntrExample().

#define XEmacPs_BdSetLength	(	BdPtr,
		LenBytes
	)

Value:

XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET,              \
    ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) &           \
    ~XEMACPS_TXBUF_LEN_MASK) | (LenBytes)))

Set transfer length in bytes for the given BD.

The length must be set each time a BD is submitted to hardware.

Parameters

BdPtr	is the BD pointer to operate on
LenBytes	is the number of bytes to transfer.

Note: C-style signature: void XEmacPs_BdSetLength(XEmacPs_Bd* BdPtr, u32 LenBytes)

Referenced by EmacPsDmaSingleFrameIntrExample().

#define XEmacPs_BdSetStatus	(	BdPtr,
		Data
	)

Value:

XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \

XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | (Data))

XEmacPs_BdWrite

#define XEmacPs_BdWrite(BaseAddress, Offset, Data)

Write the given Buffer Descriptor word.

Definition: xemacps_bd.h:140

XEmacPs_BdRead

#define XEmacPs_BdRead(BaseAddress, Offset)

Read the given Buffer Descriptor word.

Definition: xemacps_bd.h:121

XEMACPS_BD_STAT_OFFSET

#define XEMACPS_BD_STAT_OFFSET

word 1/status of BDs

Definition: xemacps_hw.h:664

Set the BD's Status field (word 1).

Parameters

BdPtr	is the BD pointer to operate on
Data	is the value to write to BD's status field.

Note: C-style signature: void XEmacPs_BdSetStatus(XEmacPs_Bd* BdPtr, UINTPTR Data)

Referenced by EmacPsDmaIntrExample(), and EmacPsDmaSingleFrameIntrExample().

#define XEmacPs_BdSetTxNoCRC ( BdPtr )

Value:

(XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET,             \
    XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) |             \
    XEMACPS_TXBUF_NOCRC_MASK))

Sets this bit, no CRC will be appended to the current frame.

This control bit must be set for the first buffer in a frame and will be ignored for the subsequent buffers of a frame.

Parameters

BdPtr is the BD pointer to operate on

Note: This bit must be clear when using the transmit checksum generation offload, otherwise checksum generation and substitution will not occur.

C-style signature: UINTPTR XEmacPs_BdSetTxNoCRC(XEmacPs_Bd* BdPtr)

#define XEmacPs_BdSetTxUsed ( BdPtr )

Value:

(XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET,             \
    XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) |             \
    XEMACPS_TXBUF_USED_MASK))

Software sets this bit to disable the buffer to be read by the hardware.

Hardware sets this bit for the first buffer of a frame once it has been successfully transmitted. This macro sets this bit of transmit BD to avoid confusion.

Parameters

BdPtr is the BD pointer to operate on

Note: C-style signature: void XEmacPs_BdSetTxUsed(XEmacPs_Bd* BdPtr)

#define XEmacPs_BdWrite	(	BaseAddress,
		Offset,
		Data
	)	((u32 )((UINTPTR)(void*)(BaseAddress) + (u32)(Offset)) = (u32)(Data))

Write the given Buffer Descriptor word.

Parameters

BaseAddress	is the base address of the BD to write
Offset	is the word offset to be written
Data	is the 32-bit value to write to the field

Returns: None.

Note: C-style signature: void XEmacPs_BdWrite(UINTPTR BaseAddress, UINTPTR Offset, UINTPTR Data)

#define XEMACPS_BROADCAST_OPTION 0x00000400U

Allow reception of the broadcast address This option defaults to enabled (set)

Referenced by XEmacPs_ClearOptions(), and XEmacPs_SetOptions().

#define XEMACPS_CMPA_ENABLE_MASK 0x00040000U

Enable Compare A.

Referenced by EmacPsDmaSingleFrameIntrExample().

#define XEMACPS_CMPA_MASK 0x0003E000U

Compare reg number.

#define XEMACPS_DEFAULT_OPTIONS

Value:

((u32)XEMACPS_FLOW_CONTROL_OPTION |                  \
         (u32)XEMACPS_FCS_INSERT_OPTION |                    \
         (u32)XEMACPS_FCS_STRIP_OPTION |                     \
         (u32)XEMACPS_BROADCAST_OPTION |                     \
         (u32)XEMACPS_LENTYPE_ERR_OPTION |                   \
         (u32)XEMACPS_TRANSMITTER_ENABLE_OPTION |            \
         (u32)XEMACPS_RECEIVER_ENABLE_OPTION |               \
         (u32)XEMACPS_RX_CHKSUM_ENABLE_OPTION |              \
         (u32)XEMACPS_TX_CHKSUM_ENABLE_OPTION)

Default options set when device is initialized or reset.

Referenced by XEmacPs_Reset().

#define XEMACPS_DMA_RXQ1_BUFSIZE_OFFSET 0x000004A0U

RX Q1 DMA buffer size reg.

Referenced by XEmacPs_GetQxOffset().

#define XEMACPS_DMACR_ADDR_WIDTH_64 0x40000000U

64 bit address bus

Referenced by XEmacPs_Reset().

#define XEMACPS_DMACR_BLENGTH_MASK 0x0000001FU

buffer burst length

Referenced by XEmacPs_DMABLengthUpdate().

#define XEMACPS_DMACR_ENDIAN_MASK 0x00000080U

endian configuration

#define XEMACPS_DMACR_INCR16_AHB_BURST 0x00000010U

16 bytes AHB bursts

Referenced by XEmacPs_DMABLengthUpdate(), and XEmacPs_Reset().

#define XEMACPS_DMACR_INCR4_AHB_BURST 0x00000004U

4 bytes AHB bursts

Referenced by XEmacPs_DMABLengthUpdate().

#define XEMACPS_DMACR_INCR8_AHB_BURST 0x00000008U

8 bytes AHB bursts

Referenced by XEmacPs_DMABLengthUpdate().

#define XEMACPS_DMACR_OFFSET 0x00000010U

DMA Control reg.

Referenced by XEmacPs_ClearOptions(), XEmacPs_DMABLengthUpdate(), XEmacPs_Reset(), and XEmacPs_SetOptions().

#define XEMACPS_DMACR_RXBUF_MASK 0x00FF0000U

Mask bit for RX buffer size.

Referenced by XEmacPs_ClearOptions(), XEmacPs_Reset(), and XEmacPs_SetOptions().

#define XEMACPS_DMACR_RXBUF_SHIFT 16U

Shift bit for RX buffer size.

Referenced by XEmacPs_ClearOptions(), XEmacPs_Reset(), and XEmacPs_SetOptions().

#define XEMACPS_DMACR_RXEXTEND_MASK 0x10000000U

Rx Extended desc mode.

#define XEMACPS_DMACR_RXSIZE_MASK 0x00000300U

RX buffer memory size.

Referenced by XEmacPs_Reset().

#define XEMACPS_DMACR_SINGLE_AHB_BURST 0x00000001U

single AHB bursts

Referenced by XEmacPs_DMABLengthUpdate().

#define XEMACPS_DMACR_TCPCKSUM_MASK 0x00000800U

enable/disable TX checksum offload

Referenced by XEmacPs_ClearOptions(), and XEmacPs_SetOptions().

#define XEMACPS_DMACR_TXEXTEND_MASK 0x20000000U

Tx Extended desc mode.

#define XEMACPS_DMACR_TXSIZE_MASK 0x00000400U

TX buffer memory size.

Referenced by XEmacPs_Reset().

#define XEMACPS_EXCESSCOLLCNT_OFFSET 0x00000140U

Excessive Collision Frame Counter.

#define XEMACPS_FCS_INSERT_OPTION 0x00000040U

Generate FCS field and add PAD automatically for outgoing frames.

This option defaults to disabled (cleared)

#define XEMACPS_FCS_STRIP_OPTION 0x00000020U

Strip FCS and PAD from incoming frames.

Note: PAD from VLAN frames is not stripped. This option defaults to enabled (set)

Referenced by XEmacPs_ClearOptions(), and XEmacPs_SetOptions().

#define XEMACPS_FLOW_CONTROL_OPTION 0x00000010U

Enable recognition of flow control frames on Rx This option defaults to enabled (set)

Referenced by XEmacPs_ClearOptions(), and XEmacPs_SetOptions().

#define XEMACPS_FRAME1536_OPTION 0x00000002U

Frame larger than 1516 support for Tx & Rx.

This option defaults to disabled (cleared)

Referenced by XEmacPs_ClearOptions(), and XEmacPs_SetOptions().

#define XEmacPs_GetRxFrameSize	(	InstancePtr,
		BdPtr
	)

Value:

(XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \

(InstancePtr)->RxBufMask)

XEmacPs_BdRead

#define XEmacPs_BdRead(BaseAddress, Offset)

Read the given Buffer Descriptor word.

Definition: xemacps_bd.h:121

XEMACPS_BD_STAT_OFFSET

#define XEMACPS_BD_STAT_OFFSET

word 1/status of BDs

Definition: xemacps_hw.h:664

Retrieve the RX frame size.

The returned value is the size of the received packet. This API supports jumbo frame sizes if enabled.

Parameters

InstancePtr	is the pointer to XEmacps instance
BdPtr	is the BD pointer to operate on

Returns: Length field processed by hardware or set by XEmacPs_BdSetLength().

Note: C-style signature: UINTPTR XEmacPs_GetRxFrameSize(XEmacPs* InstancePtr, XEmacPs_Bd* BdPtr) RxBufMask is dependent on whether jumbo is enabled or not.

Referenced by EmacPsDmaSingleFrameIntrExample().

#define XEmacPs_GetRxRing ( InstancePtr ) ((InstancePtr)->RxBdRing)

Retrieve the Rx ring object.

This object can be used in the various Ring API functions.

Parameters

InstancePtr is the DMA channel to operate on.

Returns: RxBdRing attribute

Note: C-style signature: XEmacPs_BdRing XEmacPs_GetRxRing(XEmacPs *InstancePtr)

Referenced by EmacPsDmaIntrExample(), and EmacPsDmaSingleFrameIntrExample().

#define XEmacPs_GetRXWatermark ( InstancePtr )

Value:

XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \

XEMACPS_RXWATERMARK_OFFSET)

XEMACPS_RXWATERMARK_OFFSET

#define XEMACPS_RXWATERMARK_OFFSET

RX watermark reg.

Definition: xemacps_hw.h:143

XEmacPs_ReadReg

#define XEmacPs_ReadReg(BaseAddress, RegOffset)

Read the given register.

Definition: xemacps_hw.h:763

This macro gets RX watermark register.

Parameters

InstancePtr is a pointer to the XEmacPs instance to be worked on.

Returns: RX watermark register value

Note

Signature: void XEmacPs_GetRXWatermark(XEmacPs *InstancePtr)

#define XEmacPs_GetTxRing ( InstancePtr ) ((InstancePtr)->TxBdRing)

Retrieve the Tx ring object.

This object can be used in the various Ring API functions.

Parameters

InstancePtr is the DMA channel to operate on.

Returns: TxBdRing attribute

Note: C-style signature: XEmacPs_BdRing XEmacPs_GetTxRing(XEmacPs *InstancePtr)

Referenced by EmacPsDmaIntrExample(), and EmacPsDmaSingleFrameIntrExample().

#define XEMACPS_HASHH_OFFSET 0x00000084U

Hash High address reg.

Referenced by XEmacPs_ClearHash(), XEmacPs_DeleteHash(), XEmacPs_GetHash(), XEmacPs_ResetHw(), and XEmacPs_SetHash().

#define XEMACPS_HASHL_OFFSET 0x00000080U

Hash Low address reg.

Referenced by XEmacPs_ClearHash(), XEmacPs_DeleteHash(), XEmacPs_GetHash(), XEmacPs_ResetHw(), and XEmacPs_SetHash().

#define XEMACPS_IDR_OFFSET 0x0000002CU

Interrupt Disable reg.

Referenced by XEmacPs_Reset(), XEmacPs_ResetHw(), and XEmacPs_Stop().

#define XEMACPS_IER_OFFSET 0x00000028U

Interrupt Enable reg.

#define XEMACPS_IMR_OFFSET 0x00000030U

Interrupt Mask reg.

#define XEmacPs_IntDisable	(	InstancePtr,
		Mask
	)

Value:

XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress,             \
                         XEMACPS_IDR_OFFSET,                                     \
                         ((Mask) & XEMACPS_IXR_ALL_MASK));

Disable interrupts specified in Mask.

The corresponding interrupt for each bit set to 1 in Mask, will be enabled.

Parameters

InstancePtr	is a pointer to the instance to be worked on.
Mask	contains a bit mask of interrupts to disable. The mask can be formed using a set of bitwise or'd values.

Note: The state of the transmitter and receiver are not modified by this function. C-style signature void XEmacPs_IntDisable(XEmacPs *InstancePtr, u32 Mask)

#define XEmacPs_IntEnable	(	InstancePtr,
		Mask
	)

Value:

XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress,             \
                         XEMACPS_IER_OFFSET,                                     \
                         ((Mask) & XEMACPS_IXR_ALL_MASK));

Enable interrupts specified in Mask.

The corresponding interrupt for each bit set to 1 in Mask, will be enabled.

Parameters

InstancePtr	is a pointer to the instance to be worked on.
Mask	contains a bit mask of interrupts to enable. The mask can be formed using a set of bitwise or'd values.

Note: The state of the transmitter and receiver are not modified by this function. C-style signature void XEmacPs_IntEnable(XEmacPs *InstancePtr, u32 Mask)

Referenced by XEmacPs_Start().

#define XEMACPS_INTQ1_IDR_OFFSET 0x00000620U

Interrupt Q1 Disable reg.

Referenced by XEmacPs_GetQxOffset().

#define XEMACPS_INTQ1_IER_OFFSET 0x00000600U

Interrupt Q1 Enable reg.

Referenced by XEmacPs_GetQxOffset().

#define XEMACPS_INTQ1_IMR_OFFSET 0x00000640U

Interrupt Q1 Mask reg.

#define XEMACPS_INTQ1_STS_OFFSET 0x00000400U

Interrupt Q1 Status reg.

Referenced by XEmacPs_GetQxOffset().

#define XEMACPS_INTQ1SR_RXCOMPL_MASK 0x00000002U

Receive completed OK.

#define XEMACPS_INTQ1SR_TXCOMPL_MASK 0x00000080U

Transmit completed OK.

#define XEMACPS_INTQ1SR_TXERR_MASK 0x00000040U

Transmit AMBA Error.

#define XEmacPs_IntQiDisable	(	InstancePtr,
		Queue,
		Mask
	)

Value:

XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress,             \
                         XEmacPs_GetQxOffset(INTQI_IDR, Queue),         \
                         ((Mask) & XEMACPS_INTQ_IXR_ALL_MASK));

Disable interrupts of queue Queue specified in Mask.

The corresponding interrupt for each bit set to 1 in Mask, will be enabled.

Parameters

InstancePtr	is a pointer to the instance to be worked on.
Index	of Queue, it should be from 1.
Mask	contains a bit mask of interrupts to disable. The mask can be formed using a set of bitwise or'd values.

Note: The state of the transmitter and receiver are not modified by this function. C-style signature void XEmacPs_IntDisable(XEmacPs *InstancePtr, u8 Queue, u32 Mask)

#define XEmacPs_IntQiEnable	(	InstancePtr,
		Queue,
		Mask
	)

Value:

XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress,             \
                         XEmacPs_GetQxOffset(INTQI_IER, Queue),         \
                         ((Mask) & XEMACPS_INTQ_IXR_ALL_MASK));

Enable interrupts of queue Queue specified in Mask.

The corresponding interrupt for each bit set to 1 in Mask, will be enabled.

Parameters

InstancePtr	is a pointer to the instance to be worked on.
Indx	of Queue, it should be from 1.
Mask	contains a bit mask of interrupts to enable. The mask can be formed using a set of bitwise or'd values.

Note: The state of the transmitter and receiver are not modified by this function. C-style signature void XEmacPs_IntQiEnable(XEmacPs *InstancePtr, u8 Queue, u32 Mask)

Referenced by XEmacPs_Start().

#define XEMACPS_ISR_OFFSET 0x00000024U

Interrupt Status reg.

Referenced by XEmacPs_GetQxOffset(), XEmacPs_IntrHandler(), XEmacPs_Reset(), XEmacPs_ResetHw(), and XEmacPs_Start().

#define XEmacPs_IsRxCsum ( InstancePtr )

Value:

((XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress,             \
                          XEMACPS_NWCFG_OFFSET) & XEMACPS_NWCFG_RXCHKSUMEN_MASK) != 0U     \
         ? TRUE : FALSE)

This macro determines if the device is configured with checksum offloading on the receive channel.

Parameters

InstancePtr is a pointer to the XEmacPs instance to be worked on.

Returns

Boolean TRUE if the device is configured with checksum offloading, or FALSE otherwise.

Note

Signature: u32 XEmacPs_IsRxCsum(XEmacPs *InstancePtr)

#define XEmacPs_IsTxCsum ( InstancePtr )

Value:

((XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress,              \
                          XEMACPS_DMACR_OFFSET) & XEMACPS_DMACR_TCPCKSUM_MASK) != 0U       \
         ? TRUE : FALSE)

This macro determines if the device is configured with checksum offloading on the transmit channel.

Parameters

InstancePtr is a pointer to the XEmacPs instance to be worked on.

Returns

Boolean TRUE if the device is configured with checksum offloading, or FALSE otherwise.

Note

Signature: u32 XEmacPs_IsTxCsum(XEmacPs *InstancePtr)

#define XEMACPS_IXR_ALL_MASK 0x00007FFFU

Everything!

Referenced by XEmacPs_Reset(), XEmacPs_ResetHw(), XEmacPs_Start(), and XEmacPs_Stop().

#define XEMACPS_IXR_FRAMERX_MASK 0x00000002U

Frame received ok.

Referenced by XEmacPs_Start().

#define XEMACPS_IXR_HRESPNOK_MASK 0x00000800U

hresp not ok

#define XEMACPS_IXR_MGMNT_MASK 0x00000001U

PHY management complete.

#define XEMACPS_IXR_PAUSENZERO_MASK 0x00001000U

Pause frame received.

#define XEMACPS_IXR_PAUSETX_MASK 0x00004000U

Pause frame transmitted.

#define XEMACPS_IXR_PAUSEZERO_MASK 0x00002000U

Pause time has reached zero.

#define XEMACPS_IXR_PTPDRRX_MASK 0x00040000U

PTP Delay_req RXed.

#define XEMACPS_IXR_PTPDRTX_MASK 0x00100000U

PTP Delay_req TXed.

#define XEMACPS_IXR_PTPPDRRX_MASK 0x00400000U

PTP Pdelay_req RXed.

#define XEMACPS_IXR_PTPPDRTX_MASK 0x01000000U

PTP Pdelay_req TXed.

#define XEMACPS_IXR_PTPPSRX_MASK 0x00800000U

PTP Pdelay_resp RXed.

#define XEMACPS_IXR_PTPPSTX_MASK 0x02000000U

PTP Pdelay_resp TXed.

#define XEMACPS_IXR_PTPSRX_MASK 0x00080000U

PTP Sync RXed.

#define XEMACPS_IXR_PTPSTX_MASK 0x00200000U

PTP Sync TXed.

#define XEMACPS_IXR_RETRY_MASK 0x00000020U

Retry limit exceeded.

#define XEMACPS_IXR_RXOVR_MASK 0x00000400U

Receive overrun occurred.

#define XEMACPS_IXR_RXUSED_MASK 0x00000004U

Rx buffer used bit read.

Referenced by XEmacPs_IntrHandler().

#define XEMACPS_IXR_TXCOMPL_MASK 0x00000080U

Frame transmitted ok.

Referenced by XEmacPs_IntrHandler(), and XEmacPs_Start().

#define XEMACPS_IXR_TXEXH_MASK 0x00000040U

Transmit err occurred or no buffers.

#define XEMACPS_IXR_TXUSED_MASK 0x00000008U

Tx buffer used bit read.

#define XEMACPS_IXR_URUN_MASK 0x00000010U

Transmit underrun.

#define XEMACPS_JUMBOMAXLEN_OFFSET 0x00000048U

Jumbo max length reg.

Referenced by XEmacPs_SetOptions().

#define XEMACPS_LADDR1H_OFFSET 0x0000008CU

Specific1 addr high reg.

Referenced by XEmacPs_GetMacAddress(), and XEmacPs_SetMacAddress().

#define XEMACPS_LADDR1L_OFFSET 0x00000088U

Specific1 addr low reg.

Referenced by XEmacPs_GetMacAddress(), and XEmacPs_SetMacAddress().

#define XEMACPS_LADDR2H_OFFSET 0x00000094U

Specific2 addr high reg.

#define XEMACPS_LADDR2L_OFFSET 0x00000090U

Specific2 addr low reg.

#define XEMACPS_LADDR3H_OFFSET 0x0000009CU

Specific3 addr high reg.

#define XEMACPS_LADDR3L_OFFSET 0x00000098U

Specific3 addr low reg.

#define XEMACPS_LADDR4H_OFFSET 0x000000A4U

Specific4 addr high reg.

#define XEMACPS_LADDR4L_OFFSET 0x000000A0U

Specific4 addr low reg.

#define XEMACPS_LADDR_MACH_MASK 0x0000FFFFU

Address bits[47:32] bit[31:0] are in BOTTOM.

Referenced by XEmacPs_SetMacAddress().

#define XEMACPS_LAST_OFFSET 0x000001B4U

Last statistic counter offset, for clearing.

Referenced by XEmacPs_Reset().

#define XEMACPS_LATECOLLCNT_OFFSET 0x00000144U

Late Collision Frame Counter.

#define XEMACPS_LENTYPE_ERR_OPTION 0x00000080U

Enable Length/Type error checking for incoming frames.

When this option is set, the MAC will filter frames that have a mismatched type/length field and if XEMACPS_REPORT_RXERR_OPTION is set, the user is notified when these types of frames are encountered. When this option is cleared, the MAC will allow these types of frames to be received.

This option defaults to disabled (cleared)

Referenced by XEmacPs_ClearOptions(), and XEmacPs_SetOptions().

#define XEMACPS_MATCH1_OFFSET 0x000000A8U

Type ID1 Match reg.

Referenced by XEmacPs_SetTypeIdCheck().

#define XEMACPS_MATCH2_OFFSET 0x000000ACU

Type ID2 Match reg.

#define XEMACPS_MATCH3_OFFSET 0x000000B0U

Type ID3 Match reg.

#define XEMACPS_MATCH4_OFFSET 0x000000B4U

Type ID4 Match reg.

#define XEMACPS_MAX_HASH_BITS 64U

Maximum value for hash bits.

2**6

Referenced by XEmacPs_DeleteHash(), and XEmacPs_SetHash().

#define XEMACPS_MAX_MAC_ADDR 4U

Maxmum number of mac address supported.

Referenced by XEmacPs_GetMacAddress(), and XEmacPs_SetMacAddress().

#define XEMACPS_MAX_RXBD 128U

Size of RX buffer descriptor queues.

#define XEMACPS_MAX_TXBD 128U

Size of TX buffer descriptor queues.

#define XEMACPS_MAX_TYPE_ID 4U

Maxmum number of type id supported.

Referenced by XEmacPs_SetTypeIdCheck().

#define XEMACPS_MDIO_DIV_DFT MDC_DIV_32

Default MDIO clock divisor.

#define XEMACPS_MSBBUF_RXQBASE_OFFSET 0x000004D4U

MSB Buffer RX Q Base reg.

Referenced by XEmacPs_SetQueuePtr().

#define XEMACPS_MSBBUF_TXQBASE_OFFSET 0x000004C8U

MSB Buffer TX Q Base reg.

Referenced by XEmacPs_SetQueuePtr().

#define XEMACPS_MULTICAST_OPTION 0x00000800U

Allows reception of multicast addresses programmed into hash This option defaults to disabled (clear)

Referenced by XEmacPs_ClearOptions(), and XEmacPs_SetOptions().

#define XEMACPS_MULTICOLLCNT_OFFSET 0x0000013CU

Multiple Collision Frame Counter.

#define XEMACPS_NWCFG_1000_MASK 0x00000400U

1000 Mbps

Referenced by XEmacPs_GetOperatingSpeed(), and XEmacPs_SetOperatingSpeed().

#define XEMACPS_NWCFG_100_MASK 0x00000001U

100 Mbps

Referenced by XEmacPs_GetOperatingSpeed(), XEmacPs_Reset(), and XEmacPs_SetOperatingSpeed().

#define XEMACPS_NWCFG_1536RXEN_MASK 0x00000100U

Enable 1536 byte frames reception.

Referenced by XEmacPs_ClearOptions(), and XEmacPs_SetOptions().

#define XEMACPS_NWCFG_BADPREAMBEN_MASK 0x20000000U

disable rejection of non-standard preamble

#define XEMACPS_NWCFG_BCASTDI_MASK 0x00000020U

Do not receive broadcast frames.

Referenced by XEmacPs_ClearOptions(), and XEmacPs_SetOptions().

#define XEMACPS_NWCFG_COPYALLEN_MASK 0x00000010U

Copy all frames.

Referenced by XEmacPs_ClearOptions(), and XEmacPs_SetOptions().

#define XEMACPS_NWCFG_DWIDTH_64_MASK 0x00200000U

64 bit Data bus width

Referenced by XEmacPs_Reset().

#define XEMACPS_NWCFG_FCSIGNORE_MASK 0x04000000U

disable rejection of FCS error

#define XEMACPS_NWCFG_FCSREM_MASK 0x00020000U

Discard FCS from received frames.

Referenced by XEmacPs_ClearOptions(), and XEmacPs_SetOptions().

#define XEMACPS_NWCFG_FDEN_MASK 0x00000002U

full duplex

Referenced by XEmacPs_Reset().

#define XEMACPS_NWCFG_HDRXEN_MASK 0x02000000U

RX half duplex.

#define XEMACPS_NWCFG_IPDSTRETCH_MASK 0x10000000U

enable transmit IPG

#define XEMACPS_NWCFG_JUMBO_MASK 0x00000008U

Jumbo frames.

Referenced by XEmacPs_ClearOptions(), and XEmacPs_SetOptions().

#define XEMACPS_NWCFG_LENERRDSCRD_MASK 0x00010000U

RX length error discard.

Referenced by XEmacPs_ClearOptions(), and XEmacPs_SetOptions().

#define XEMACPS_NWCFG_MCASTHASHEN_MASK 0x00000040U

Receive multicast hash frames.

Referenced by XEmacPs_ClearOptions(), and XEmacPs_SetOptions().

#define XEMACPS_NWCFG_MDC_SHIFT_MASK 18U

shift bits for MDC

Referenced by XEmacPs_SetMdioDivisor().

#define XEMACPS_NWCFG_MDCCLKDIV_MASK 0x001C0000U

MDC Mask PCLK divisor.

Referenced by XEmacPs_Reset(), and XEmacPs_SetMdioDivisor().

#define XEMACPS_NWCFG_NVLANDISC_MASK 0x00000004U

Receive only VLAN frames.

Referenced by XEmacPs_ClearOptions(), and XEmacPs_SetOptions().

#define XEMACPS_NWCFG_OFFSET 0x00000004U

Network Config reg.

Referenced by XEmacPs_ClearOptions(), XEmacPs_GetOperatingSpeed(), XEmacPs_Reset(), XEmacPs_ResetHw(), XEmacPs_SetMdioDivisor(), XEmacPs_SetOperatingSpeed(), and XEmacPs_SetOptions().

#define XEMACPS_NWCFG_PAUSECOPYDI_MASK 0x00800000U

Do not copy pause Frames to memory.

#define XEMACPS_NWCFG_PAUSEEN_MASK 0x00002000U

Enable pause RX.

Referenced by XEmacPs_ClearOptions(), and XEmacPs_SetOptions().

#define XEMACPS_NWCFG_PCSSEL_MASK 0x00000800U

PCS Select.

Referenced by XEmacPs_ClearOptions(), and XEmacPs_SetOptions().

#define XEMACPS_NWCFG_RESET_MASK 0x00080000U

reset value

Referenced by XEmacPs_ResetHw().

#define XEMACPS_NWCFG_RETRYTESTEN_MASK 0x00001000U

Retry test.

#define XEMACPS_NWCFG_RXCHKSUMEN_MASK 0x01000000U

enable RX checksum offload

Referenced by XEmacPs_ClearOptions(), and XEmacPs_SetOptions().

#define XEMACPS_NWCFG_RXOFFS_MASK 0x0000C000U

RX buffer offset.

#define XEMACPS_NWCFG_SGMIIEN_MASK 0x08000000U

SGMII Enable.

Referenced by XEmacPs_ClearOptions(), and XEmacPs_SetOptions().

#define XEMACPS_NWCFG_UCASTHASHEN_MASK 0x00000080U

Receive unicast hash frames.

Referenced by XEmacPs_Reset().

#define XEMACPS_NWCFG_XTADDMACHEN_MASK 0x00000200U

External address match enable.

#define XEMACPS_NWCTRL_FLUSH_DPRAM_MASK 0x00040000U

Flush a packet from Rx SRAM.

Referenced by XEmacPs_IntrHandler(), and XEmacPs_ResetHw().

#define XEMACPS_NWCTRL_HALTTX_MASK 0x00000400U

Halt transmission after current frame.

Referenced by XEmacPs_ResetHw().

#define XEMACPS_NWCTRL_LOOPEN_MASK 0x00000002U

local loopback

Referenced by EmacPsUtilEnterLocalLoopback(), XEmacPs_Reset(), and XEmacPs_ResetHw().

#define XEMACPS_NWCTRL_MDEN_MASK 0x00000010U

Enable MDIO port.

Referenced by XEmacPs_Reset().

#define XEMACPS_NWCTRL_OFFSET 0x00000000U

Network Control reg.

Referenced by EmacPsUtilEnterLocalLoopback(), XEmacPs_ClearOptions(), XEmacPs_IntrHandler(), XEmacPs_Reset(), XEmacPs_ResetHw(), XEmacPs_SendPausePacket(), XEmacPs_SetOptions(), XEmacPs_Start(), and XEmacPs_Stop().

#define XEMACPS_NWCTRL_PAUSETX_MASK 0x00000800U

Transmit pause frame.

Referenced by XEmacPs_SendPausePacket().

#define XEMACPS_NWCTRL_RXEN_MASK 0x00000004U

Enable receive.

Referenced by XEmacPs_ClearOptions(), XEmacPs_Reset(), XEmacPs_ResetHw(), XEmacPs_SetOptions(), XEmacPs_Start(), and XEmacPs_Stop().

#define XEMACPS_NWCTRL_STARTTX_MASK 0x00000200U

Start tx (tx_go)

#define XEMACPS_NWCTRL_STATCLR_MASK 0x00000020U

Clear statistic registers.

Referenced by XEmacPs_Reset(), and XEmacPs_ResetHw().

#define XEMACPS_NWCTRL_STATINC_MASK 0x00000040U

Increment statistic registers.

#define XEMACPS_NWCTRL_STATWEN_MASK 0x00000080U

Enable writing to stat counters.

#define XEMACPS_NWCTRL_TXEN_MASK 0x00000008U

Enable transmit.

Referenced by XEmacPs_ClearOptions(), XEmacPs_ResetHw(), XEmacPs_SetOptions(), XEmacPs_Start(), and XEmacPs_Stop().

#define XEMACPS_NWCTRL_ZEROPAUSETX_MASK 0x00000800U

Transmit zero quantum pause frame.

#define XEMACPS_NWSR_MDIO_MASK 0x00000002U

Status of mdio_in.

#define XEMACPS_NWSR_MDIOIDLE_MASK 0x00000004U

PHY management idle.

Referenced by XEmacPs_PhyRead(), and XEmacPs_PhyWrite().

#define XEMACPS_NWSR_OFFSET 0x00000008U

Network Status reg.

Referenced by XEmacPs_PhyRead(), and XEmacPs_PhyWrite().

#define XEMACPS_OCTRXH_OFFSET 0x00000154U

Octects Received register High.

#define XEMACPS_OCTRXL_OFFSET 0x00000150U

Octects Received register Low.

#define XEMACPS_OCTTXH_OFFSET 0x00000104U

Octects transmitted High reg.

#define XEMACPS_OCTTXL_OFFSET 0x00000100U

Octects transmitted Low reg.

Referenced by XEmacPs_Reset().

#define XEMACPS_PCS_CON_AUTO_NEG_MASK 0x00001000U

Auto-negotiation.

#define XEMACPS_PCS_STATUS_LINK_STATUS_MASK 0x00000004U

Link status.

#define XEMACPS_PHYMNTNC_ADDR_MASK 0x0F800000U

Address bits.

#define XEMACPS_PHYMNTNC_DATA_MASK 0x00000FFFU

data bits

#define XEMACPS_PHYMNTNC_OFFSET 0x00000034U

Phy Maintaince reg.

Referenced by XEmacPs_PhyRead(), and XEmacPs_PhyWrite().

#define XEMACPS_PHYMNTNC_OP_MASK 0x40020000U

operation mask bits

Referenced by XEmacPs_PhyRead(), and XEmacPs_PhyWrite().

#define XEMACPS_PHYMNTNC_OP_R_MASK 0x20000000U

read operation

Referenced by XEmacPs_PhyRead().

#define XEMACPS_PHYMNTNC_OP_W_MASK 0x10000000U

write operation

Referenced by XEmacPs_PhyWrite().

#define XEMACPS_PHYMNTNC_PHAD_SHFT_MSK 23U

Shift bits for PHYAD.

Referenced by XEmacPs_PhyRead(), and XEmacPs_PhyWrite().

#define XEMACPS_PHYMNTNC_PREG_SHFT_MSK 18U

Shift bits for PHREG.

Referenced by XEmacPs_PhyRead(), and XEmacPs_PhyWrite().

#define XEMACPS_PHYMNTNC_REG_MASK 0x007C0000U

register bits

#define XEMACPS_PROMISC_OPTION 0x00000001U

Accept all incoming packets.

This option defaults to disabled (cleared)

Referenced by XEmacPs_ClearOptions(), and XEmacPs_SetOptions().

#define XEMACPS_PTP_RXNANOSEC_OFFSET 0x000001ECU

1588 PTP receive nanosecond counter

#define XEMACPS_PTP_RXSEC_OFFSET 0x000001E8U

1588 PTP receive second counter

#define XEMACPS_PTP_TXNANOSEC_OFFSET 0x000001E4U

1588 PTP transmit nanosecond counter

#define XEMACPS_PTP_TXSEC_OFFSET 0x000001E0U

1588 PTP transmit second counter

#define XEMACPS_PTPP_RXNANOSEC_OFFSET 0x000001FCU

1588 PTP peer receive nanosecond counter

#define XEMACPS_PTPP_RXSEC_OFFSET 0x000001F8U

1588 PTP peer receive second counter

#define XEMACPS_PTPP_TXNANOSEC_OFFSET 0x000001F4U

1588 PTP peer transmit nanosecond counter

#define XEMACPS_PTPP_TXSEC_OFFSET 0x000001F0U

1588 PTP peer transmit second counter

#define XEmacPs_ReadReg	(	BaseAddress,
		RegOffset
	)	XEmacPs_In32((BaseAddress) + (u32)(RegOffset))

Read the given register.

Parameters

BaseAddress	is the base address of the device
RegOffset	is the register offset to be read

Returns: The 32-bit value of the register

Note: C-style signature: u32 XEmacPs_ReadReg(u32 BaseAddress, u32 RegOffset)

Referenced by EmacPsUtilEnterLocalLoopback(), main(), XEmacPs_ClearOptions(), XEmacPs_DeleteHash(), XEmacPs_DMABLengthUpdate(), XEmacPs_GetHash(), XEmacPs_GetMacAddress(), XEmacPs_GetOperatingSpeed(), XEmacPs_IntrHandler(), XEmacPs_PhyRead(), XEmacPs_PhyWrite(), XEmacPs_Reset(), XEmacPs_ResetHw(), XEmacPs_SendPausePacket(), XEmacPs_SetHash(), XEmacPs_SetMacAddress(), XEmacPs_SetMdioDivisor(), XEmacPs_SetOperatingSpeed(), XEmacPs_SetOptions(), XEmacPs_Start(), and XEmacPs_Stop().

#define XEMACPS_RECEIVER_ENABLE_OPTION 0x00000200U

Enable the receiver This option defaults to enabled (set)

Referenced by XEmacPs_ClearOptions(), XEmacPs_Reset(), XEmacPs_SetOptions(), and XEmacPs_Start().

#define XEMACPS_RECV 2U

receive direction

Referenced by EmacPsDmaIntrExample(), EmacPsDmaSingleFrameIntrExample(), XEmacPs_BdRingCheck(), XEmacPs_BdRingClone(), XEmacPs_IntrHandler(), and XEmacPs_Reset().

#define XEMACPS_RX1024CNT_OFFSET 0x0000017CU

Error-free 1024-1518 byte Frames Received Counter.

#define XEMACPS_RX128CNT_OFFSET 0x00000170U

Error-free 128-255 byte Frames Received Counter.

#define XEMACPS_RX1519CNT_OFFSET 0x00000180U

Error-free 1519-max byte Frames Received Counter.

#define XEMACPS_RX256CNT_OFFSET 0x00000174U

Error-free 256-512 byte Frames Received Counter.

#define XEMACPS_RX512CNT_OFFSET 0x00000178U

Error-free 512-1023 byte Frames Received Counter.

#define XEMACPS_RX64CNT_OFFSET 0x00000168U

Error-free 64 byte Frames Received Counter.

#define XEMACPS_RX65CNT_OFFSET 0x0000016CU

Error-free 65-127 byte Frames Received Counter.

#define XEMACPS_RX_BUF_ALIGNMENT 4U

Minimum buffer alignment when using options that impose alignment restrictions on the buffer data on the local bus.

#define XEMACPS_RX_BUF_SIZE 1536U

Specify the receive buffer size in bytes, 64, 128, ...

10240

Referenced by XEmacPs_ClearOptions(), and XEmacPs_Reset().

#define XEMACPS_RX_BUF_UNIT 64U

Number of receive buffer bytes as a unit, this is HW setup.

Referenced by XEmacPs_ClearOptions(), XEmacPs_Reset(), and XEmacPs_SetOptions().

#define XEMACPS_RX_CHKSUM_ENABLE_OPTION 0x00001000U

Enable the RX checksum offload This option defaults to enabled (set)

Referenced by XEmacPs_ClearOptions(), and XEmacPs_SetOptions().

#define XEMACPS_RXALIGNCNT_OFFSET 0x0000019CU

Alignment Error Counter.

#define XEMACPS_RXBROADCNT_OFFSET 0x0000015CU

Error-free Broadcast Frames Received Counter.

#define XEMACPS_RXBUF_ADD_MASK 0xFFFFFFFCU

Mask for address.

#define XEMACPS_RXBUF_AMATCH_MASK 0x06000000U

Specific address matched.

#define XEMACPS_RXBUF_BCAST_MASK 0x80000000U

Broadcast frame.

#define XEMACPS_RXBUF_CFI_MASK 0x00010000U

CFI frame.

#define XEMACPS_RXBUF_EOF_MASK 0x00008000U

End of frame.

Referenced by XEmacPs_BdRingFromHwRx().

#define XEMACPS_RXBUF_EXH_MASK 0x08000000U

buffer exhausted

#define XEMACPS_RXBUF_IDFOUND_MASK 0x01000000U

Type ID matched.

#define XEMACPS_RXBUF_IDMATCH_MASK 0x00C00000U

ID matched mask.

#define XEMACPS_RXBUF_LEN_JUMBO_MASK 0x00003FFFU

Mask for jumbo length.

Referenced by XEmacPs_SetOptions().

#define XEMACPS_RXBUF_LEN_MASK 0x00001FFFU

Mask for length field.

Referenced by XEmacPs_ClearOptions(), and XEmacPs_Reset().

#define XEMACPS_RXBUF_MULTIHASH_MASK 0x40000000U

Multicast hashed frame.

#define XEMACPS_RXBUF_NEW_MASK 0x00000001U

Used bit.

Referenced by EmacPsDmaSingleFrameIntrExample().

#define XEMACPS_RXBUF_PRI_MASK 0x00100000U

Priority tagged.

#define XEMACPS_RXBUF_SOF_MASK 0x00004000U

Start of frame.

#define XEMACPS_RXBUF_UNIHASH_MASK 0x20000000U

Unicast hashed frame.

#define XEMACPS_RXBUF_VLAN_MASK 0x00200000U

VLAN tagged.

#define XEMACPS_RXBUF_VPRI_MASK 0x000E0000U

Vlan priority.

#define XEMACPS_RXBUF_WRAP_MASK 0x00000002U

Wrap bit, last BD.

Referenced by EmacPsDmaSingleFrameIntrExample().

#define XEMACPS_RXCNT_OFFSET 0x00000158U

Error-free Frames Received Counter.

Referenced by main().

#define XEMACPS_RXFCSCNT_OFFSET 0x00000190U

Frame Check Sequence Error Counter.

#define XEMACPS_RXIPCCNT_OFFSET 0x000001A8U

IP header Checksum Error Counter.

#define XEMACPS_RXJABCNT_OFFSET 0x0000018CU

Jabbers Received Counter.

#define XEMACPS_RXLENGTHCNT_OFFSET 0x00000194U

Length Field Error Counter.

#define XEMACPS_RXMULTICNT_OFFSET 0x00000160U

Error-free Multicast Frames Received Counter.

#define XEMACPS_RXORCNT_OFFSET 0x000001A4U

Receive Overrun Counter.

#define XEMACPS_RXOVRCNT_OFFSET 0x00000188U

Oversize Frames Received Counter.

#define XEMACPS_RXPAUSE_OFFSET 0x00000038U

RX Pause Time reg.

#define XEMACPS_RXPAUSECNT_OFFSET 0x00000164U

Pause Frames Received Counter.

#define XEMACPS_RXQ1BASE_OFFSET 0x00000480U

RX Q1 Base address reg.

Referenced by XEmacPs_GetQxOffset().

#define XEMACPS_RXQBASE_OFFSET 0x00000018U

RX Q Base address reg.

Referenced by XEmacPs_GetQxOffset(), XEmacPs_ResetHw(), and XEmacPs_Start().

#define XEMACPS_RXRESERRCNT_OFFSET 0x000001A0U

Receive Resource Error Counter.

#define XEMACPS_RXSR_BUFFNA_MASK 0x00000001U

RX buffer used bit set.

Referenced by XEmacPs_IntrHandler().

#define XEMACPS_RXSR_FRAMERX_MASK 0x00000002U

Frame received OK.

Referenced by XEmacPs_IntrHandler(), and XEmacPs_ResetHw().

#define XEMACPS_RXSR_HRESPNOK_MASK 0x00000008U

Receive hresp not OK.

#define XEMACPS_RXSR_OFFSET 0x00000020U

RX Status reg.

Referenced by XEmacPs_IntrHandler(), XEmacPs_Reset(), and XEmacPs_ResetHw().

#define XEMACPS_RXSR_RXOVR_MASK 0x00000004U

Receive overrun.

#define XEMACPS_RXSYMBCNT_OFFSET 0x00000198U

Symbol Error Counter.

#define XEMACPS_RXTCPCCNT_OFFSET 0x000001ACU

TCP Checksum Error Counter.

#define XEMACPS_RXUDPCCNT_OFFSET 0x000001B0U

UDP Checksum Error Counter.

#define XEMACPS_RXUNDRCNT_OFFSET 0x00000184U

Undersize Frames Received Counter.

#define XEMACPS_RXWATERMARK_OFFSET 0x0000007CU

RX watermark reg.

#define XEMACPS_RXWM_HIGH_MASK 0x0000FFFFU

RXWM high mask.

#define XEMACPS_RXWM_LOW_MASK 0xFFFF0000U

RXWM low mask.

#define XEMACPS_RXWM_LOW_SHFT_MSK 16U

Shift for RXWM low.

#define XEMACPS_SEND 1U

send direction

Referenced by EmacPsDmaIntrExample(), EmacPsDmaSingleFrameIntrExample(), XEmacPs_BdRingCheck(), XEmacPs_BdRingClone(), XEmacPs_IntrHandler(), XEmacPs_Reset(), and XEmacPs_SetQueuePtr().

#define XEmacPs_SetRXWatermark	(	InstancePtr,
		High,
		Low
	)

Value:

XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress,                \
                         XEMACPS_RXWATERMARK_OFFSET,                                        \
                         (High & XEMACPS_RXWM_HIGH_MASK) |  \
                         ((Low << XEMACPS_RXWM_LOW_SHFT_MSK) & XEMACPS_RXWM_LOW_MASK) |)

This macro sets RX watermark register.

Parameters

InstancePtr	is a pointer to the XEmacPs instance to be worked on.
High	is the non-zero RX high watermark value. When SRAM fill level is above this, a pause frame will be sent.
Low	is the non-zero RX low watermark value. When SRAM fill level is below this, a zero length pause frame will be sent IF the last pause frame sent was non-zero.

Returns: None

Note

Signature: void XEmacPs_SetRXWatermark(XEmacPs *InstancePtr, u16 High, u16 Low)

#define XEMACPS_SNGLCOLLCNT_OFFSET 0x00000138U

Single Collision Frame Counter.

#define XEMACPS_SR_ALL_MASK 0xFFFFFFFFU

Mask for full register.

Referenced by XEmacPs_Reset().

#define XEMACPS_STRETCH_OFFSET 0x000000BCU

IPG Stretch reg.

#define XEmacPs_Transmit ( InstancePtr )

Value:

XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress,          \
                         XEMACPS_NWCTRL_OFFSET,                                     \
                         (XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress,          \
                                          XEMACPS_NWCTRL_OFFSET) | XEMACPS_NWCTRL_STARTTX_MASK))

This macro triggers trasmit circuit to send data currently in TX buffer(s).

Parameters

InstancePtr is a pointer to the XEmacPs instance to be worked on.

Returns

Note

Signature: void XEmacPs_Transmit(XEmacPs *InstancePtr)

Referenced by EmacPsDmaSingleFrameIntrExample().

#define XEMACPS_TRANSMITTER_ENABLE_OPTION 0x00000100U

Enable the transmitter.

This option defaults to enabled (set)

Referenced by XEmacPs_ClearOptions(), XEmacPs_Reset(), XEmacPs_SetOptions(), and XEmacPs_Start().

#define XEMACPS_TX1024CNT_OFFSET 0x0000012CU

Error-free 1024-1518 byte Frames transmitted counter.

#define XEMACPS_TX128CNT_OFFSET 0x00000120U

Error-free 128-255 byte Frames Transmitted counter.

#define XEMACPS_TX1519CNT_OFFSET 0x00000130U

Error-free larger than 1519 byte Frames transmitted counter.

#define XEMACPS_TX256CNT_OFFSET 0x00000124U

Error-free 256-511 byte Frames transmitted counter.

#define XEMACPS_TX512CNT_OFFSET 0x00000128U

Error-free 512-1023 byte Frames transmitted counter.

#define XEMACPS_TX64CNT_OFFSET 0x00000118U

Error-free 64 byte Frames Transmitted counter.

#define XEMACPS_TX65CNT_OFFSET 0x0000011CU

Error-free 65-127 byte Frames Transmitted counter.

#define XEMACPS_TX_CHKSUM_ENABLE_OPTION 0x00002000U

Enable the TX checksum offload This option defaults to enabled (set)

Referenced by XEmacPs_ClearOptions(), and XEmacPs_SetOptions().

#define XEMACPS_TXBCCNT_OFFSET 0x0000010CU

Error-free Broadcast Frames counter.

#define XEMACPS_TXBUF_EXH_MASK 0x08000000U

Buffers exhausted.

#define XEMACPS_TXBUF_LAST_MASK 0x00008000U

Last buffer.

Referenced by XEmacPs_BdRingFromHwTx().

#define XEMACPS_TXBUF_LEN_MASK 0x00003FFFU

Mask for length field.

#define XEMACPS_TXBUF_NOCRC_MASK 0x00010000U

No CRC.

#define XEMACPS_TXBUF_RETRY_MASK 0x20000000U

Retry limit exceeded.

#define XEMACPS_TXBUF_TCP_MASK 0x04000000U

Late collision.

#define XEMACPS_TXBUF_URUN_MASK 0x10000000U

Transmit underrun occurred.

#define XEMACPS_TXBUF_USED_MASK 0x80000000U

Used bit.

Referenced by EmacPsDmaIntrExample(), EmacPsDmaSingleFrameIntrExample(), and XEmacPs_BdRingFromHwTx().

#define XEMACPS_TXBUF_WRAP_MASK 0x40000000U

Wrap bit, last descriptor.

Referenced by EmacPsDmaSingleFrameIntrExample().

#define XEMACPS_TXCNT_OFFSET 0x00000108U

Error-free Frmaes transmitted counter.

Referenced by main().

#define XEMACPS_TXCSENSECNT_OFFSET 0x0000014CU

Transmit Carrier Sense Error Counter.

#define XEMACPS_TXDEFERCNT_OFFSET 0x00000148U

Deferred Transmission Frame Counter.

#define XEMACPS_TXMCCNT_OFFSET 0x00000110U

Error-free Multicast Frame counter.

#define XEMACPS_TXPAUSE_OFFSET 0x0000003CU

TX Pause Time reg.

#define XEMACPS_TXPAUSECNT_OFFSET 0x00000114U

Pause Frames Transmitted Counter.

#define XEMACPS_TXQ1BASE_OFFSET 0x00000440U

TX Q1 Base address reg.

Referenced by XEmacPs_GetQxOffset().

#define XEMACPS_TXQBASE_OFFSET 0x0000001CU

TX Q Base address reg.

Referenced by XEmacPs_GetQxOffset(), XEmacPs_ResetHw(), and XEmacPs_Start().

#define XEMACPS_TXSR_BUFEXH_MASK 0x00000010U

Transmit buffs exhausted mid frame.

#define XEMACPS_TXSR_FRAMERX_MASK 0x00000002U

Collision tx frame.

#define XEMACPS_TXSR_HRESPNOK_MASK 0x00000100U

Transmit hresp not OK.

#define XEMACPS_TXSR_OFFSET 0x00000014U

TX Status reg.

Referenced by XEmacPs_IntrHandler(), XEmacPs_Reset(), and XEmacPs_ResetHw().

#define XEMACPS_TXSR_RXOVR_MASK 0x00000004U

Retry limit exceeded.

#define XEMACPS_TXSR_TXCOMPL_MASK 0x00000020U

Transmit completed OK.

Referenced by XEmacPs_IntrHandler(), and XEmacPs_ResetHw().

#define XEMACPS_TXSR_TXGO_MASK 0x00000008U

Status of go flag.

Referenced by XEmacPs_ResetHw().

#define XEMACPS_TXSR_URUN_MASK 0x00000040U

Transmit underrun.

#define XEMACPS_TXSR_USEDREAD_MASK 0x00000001U

TX buffer used bit set.

Referenced by XEmacPs_IntrHandler().

#define XEMACPS_TXURUNCNT_OFFSET 0x00000134U

TX under run error counter.

#define XEMACPS_VLAN_OPTION 0x00000004U

VLAN Rx & Tx frame support.

This option defaults to disabled (cleared)

Referenced by XEmacPs_ClearOptions(), and XEmacPs_SetOptions().

#define XEmacPs_WriteReg	(	BaseAddress,
		RegOffset,
		Data
	)	XEmacPs_Out32((BaseAddress) + (u32)(RegOffset), (u32)(Data))

Write the given register.

Parameters

BaseAddress	is the base address of the device
RegOffset	is the register offset to be written
Data	is the 32-bit value to write to the register

Returns: None.

Note: C-style signature: void XEmacPs_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)

Referenced by EmacPsDmaSingleFrameIntrExample(), EmacPsUtilEnterLocalLoopback(), XEmacPs_ClearHash(), XEmacPs_ClearOptions(), XEmacPs_DeleteHash(), XEmacPs_DMABLengthUpdate(), XEmacPs_IntrHandler(), XEmacPs_PhyRead(), XEmacPs_PhyWrite(), XEmacPs_Reset(), XEmacPs_ResetHw(), XEmacPs_SendPausePacket(), XEmacPs_SetHash(), XEmacPs_SetMacAddress(), XEmacPs_SetMdioDivisor(), XEmacPs_SetOperatingSpeed(), XEmacPs_SetOptions(), XEmacPs_SetQueuePtr(), XEmacPs_SetTypeIdCheck(), XEmacPs_Start(), and XEmacPs_Stop().

Typedef Documentation

typedef struct XEmacPs_Instance XEmacPs

The XEmacPs driver instance data.

The user is required to allocate a structure of this type for every XEmacPs device in the system. A pointer to a structure of this type is then passed to the driver API functions.

typedef u32 XEmacPs_Bd[XEMACPS_BD_NUM_WORDS]

The XEmacPs_Bd is the type for buffer descriptors (BDs).

typedef void(* XEmacPs_ErrHandler)(void *CallBackRef, u8 Direction, u32 ErrorWord)

Callback when an asynchronous error occurs.

To set this callback, invoke XEmacPs_SetHandler() with XEMACPS_HANDLER_ERROR in the HandlerType parameter.

Parameters

CallBackRef	is user data assigned when the callback was set.
Direction	defines either receive or transmit error(s) has occurred.
ErrorWord	definition varies with Direction

typedef void(* XEmacPs_Handler)(void *CallBackRef)

Callback invoked when frame(s) have been sent or received in interrupt driven DMA mode.

To set the send callback, invoke XEmacPs_SetHandler().

Parameters

CallBackRef is user data assigned when the callback was set.

Note: See xemacps_hw.h for bitmasks definitions and the device hardware spec for further information on their meaning.

Function Documentation

LONG XEmacPs_BdRingAlloc	(	XEmacPs_BdRing *	RingPtr,
		u32	NumBd,
		XEmacPs_Bd **	BdSetPtr
	)

Reserve locations in the BD list.

The set of returned BDs may be modified in preparation for future DMA transaction(s). Once the BDs are ready to be submitted to hardware, the user must call XEmacPs_BdRingToHw() in the same order which they were allocated here. Example:

       NumBd = 2,
       Status = XEmacPs_BdRingAlloc(MyRingPtr, NumBd, &MyBdSet),

       if (Status != XST_SUCCESS)
       {
           *Not enough BDs available for the request*
       }

       CurBd = MyBdSet,
       for (i=0; i<NumBd; i++)
       {
           * Prepare CurBd *.....

           * Onto next BD *
           CurBd = XEmacPs_BdRingNext(MyRingPtr, CurBd),
       }

       * Give list to hardware *
       Status = XEmacPs_BdRingToHw(MyRingPtr, NumBd, MyBdSet),

A more advanced use of this function may allocate multiple sets of BDs. They must be allocated and given to hardware in the correct sequence:

       * Legal *
       XEmacPs_BdRingAlloc(MyRingPtr, NumBd1, &MySet1),
       XEmacPs_BdRingToHw(MyRingPtr, NumBd1, MySet1),

       * Legal *
       XEmacPs_BdRingAlloc(MyRingPtr, NumBd1, &MySet1),
       XEmacPs_BdRingAlloc(MyRingPtr, NumBd2, &MySet2),
       XEmacPs_BdRingToHw(MyRingPtr, NumBd1, MySet1),
       XEmacPs_BdRingToHw(MyRingPtr, NumBd2, MySet2),

       * Not legal *
       XEmacPs_BdRingAlloc(MyRingPtr, NumBd1, &MySet1),
       XEmacPs_BdRingAlloc(MyRingPtr, NumBd2, &MySet2),
       XEmacPs_BdRingToHw(MyRingPtr, NumBd2, MySet2),
       XEmacPs_BdRingToHw(MyRingPtr, NumBd1, MySet1),

Use the API defined in xemacps_bd.h to modify individual BDs. Traversal of the BD set can be done using XEmacPs_BdRingNext() and XEmacPs_BdRingPrev().

Parameters

RingPtr	is a pointer to the BD ring instance to be worked on.
NumBd	is the number of BDs to allocate
BdSetPtr	is an output parameter, it points to the first BD available for modification.

Returns

XST_SUCCESS if the requested number of BDs was returned in the BdSetPtr parameter.
XST_FAILURE if there were not enough free BDs to satisfy the request.

Note: This function should not be preempted by another XEmacPs_Bd function call that modifies the BD space. It is the caller's responsibility to provide a mutual exclusion mechanism.; Do not modify more BDs than the number requested with the NumBd parameter. Doing so will lead to data corruption and system instability.

References XEmacPs_BdRing::FreeCnt, XEmacPs_BdRing::FreeHead, and XEmacPs_BdRing::PreCnt.

Referenced by EmacPsDmaSingleFrameIntrExample().

LONG XEmacPs_BdRingCheck	(	XEmacPs_BdRing *	RingPtr,
		u8	Direction
	)

Check the internal data structures of the BD ring for the provided channel.

The following checks are made:

Is the BD ring linked correctly in physical address space.
Do the internal pointers point to BDs in the ring.
Do the internal counters add up.

The channel should be stopped prior to calling this function.

Parameters

RingPtr	is a pointer to the instance to be worked on.
Direction	is either XEMACPS_SEND or XEMACPS_RECV that indicates which direction.

Returns

XST_SUCCESS if the set of BDs was freed.
XST_DMA_SG_NO_LIST if the list has not been created.
XST_IS_STARTED if the channel is not stopped.
XST_DMA_SG_LIST_ERROR if a problem is found with the internal data structures. If this value is returned, the channel should be reset to avoid data corruption or system instability.

Note: This function should not be preempted by another XEmacPs_Bd function call that modifies the BD space. It is the caller's responsibility to provide a mutual exclusion mechanism.

References XEmacPs_BdRing::AllCnt, XEmacPs_BdRing::BaseBdAddr, XEmacPs_BdRing::FreeCnt, XEmacPs_BdRing::FreeHead, XEmacPs_BdRing::HighBdAddr, XEmacPs_BdRing::HwCnt, XEmacPs_BdRing::HwHead, XEmacPs_BdRing::HwTail, XEmacPs_BdRing::PhysBaseAddr, XEmacPs_BdRing::PostCnt, XEmacPs_BdRing::PostHead, XEmacPs_BdRing::PreCnt, XEmacPs_BdRing::PreHead, XEmacPs_BdRing::RunState, XEmacPs_BdRing::Separation, XEMACPS_BD_ADDR_OFFSET, XEmacPs_BdIsRxWrap, XEmacPs_BdIsTxWrap, XEmacPs_BdRead, XEMACPS_RECV, and XEMACPS_SEND.

LONG XEmacPs_BdRingClone	(	XEmacPs_BdRing *	RingPtr,
		XEmacPs_Bd *	SrcBdPtr,
		u8	Direction
	)

Clone the given BD into every BD in the list.

every field of the source BD is replicated in every BD of the list.

This function can be called only when all BDs are in the free group such as they are immediately after initialization with XEmacPs_BdRingCreate(). This prevents modification of BDs while they are in use by hardware or the user.

Parameters

RingPtr	is the pointer of BD ring instance to be worked on.
SrcBdPtr	is the source BD template to be cloned into the list. This BD will be modified.
Direction	is either XEMACPS_SEND or XEMACPS_RECV that indicates which direction.

Returns

XST_SUCCESS if the list was modified.
XST_DMA_SG_NO_LIST if a list has not been created.
XST_DMA_SG_LIST_ERROR if some of the BDs in this channel are under hardware or user control.
XST_DEVICE_IS_STARTED if the DMA channel has not been stopped.

References XEmacPs_BdRing::AllCnt, XEmacPs_BdRing::BaseBdAddr, XEmacPs_BdRing::FreeCnt, XEmacPs_BdRing::RunState, XEmacPs_BdRing::Separation, XEMACPS_RECV, and XEMACPS_SEND.

Referenced by EmacPsDmaIntrExample().

LONG XEmacPs_BdRingCreate	(	XEmacPs_BdRing *	RingPtr,
		UINTPTR	PhysAddr,
		UINTPTR	VirtAddr,
		u32	Alignment,
		u32	BdCount
	)

Using a memory segment allocated by the caller, create and setup the BD list for the given DMA channel.

Parameters

RingPtr	is the instance to be worked on.
PhysAddr	is the physical base address of user memory region.
VirtAddr	is the virtual base address of the user memory region. If address translation is not being utilized, then VirtAddr should be equivalent to PhysAddr.
Alignment	governs the byte alignment of individual BDs. This function will enforce a minimum alignment of 4 bytes with no maximum as long as it is specified as a power of 2.
BdCount	is the number of BDs to setup in the user memory region. It is assumed the region is large enough to contain the BDs.

Returns

XST_SUCCESS if initialization was successful
XST_NO_FEATURE if the provided instance is a non DMA type channel.
XST_INVALID_PARAM under any of the following conditions: 1) PhysAddr and/or VirtAddr are not aligned to the given Alignment parameter. 2) Alignment parameter does not meet minimum requirements or is not a power of 2 value. 3) BdCount is 0.
XST_DMA_SG_LIST_ERROR if the memory segment containing the list spans over address 0x00000000 in virtual address space.

Note: Make sure to pass in the right alignment value.

References XEmacPs_BdRing::AllCnt, XEmacPs_BdRing::BaseBdAddr, XEmacPs_BdRing::BdaRestart, XEmacPs_BdRing::FreeCnt, XEmacPs_BdRing::FreeHead, XEmacPs_BdRing::HighBdAddr, XEmacPs_BdRing::HwCnt, XEmacPs_BdRing::HwHead, XEmacPs_BdRing::HwTail, XEmacPs_BdRing::Length, XEmacPs_BdRing::PhysBaseAddr, XEmacPs_BdRing::PostCnt, XEmacPs_BdRing::PostHead, XEmacPs_BdRing::PreCnt, XEmacPs_BdRing::PreHead, XEmacPs_BdRing::RunState, and XEmacPs_BdRing::Separation.

Referenced by EmacPsDmaIntrExample().

LONG XEmacPs_BdRingFree	(	XEmacPs_BdRing *	RingPtr,
		u32	NumBd,
		XEmacPs_Bd *	BdSetPtr
	)

Frees a set of BDs that had been previously retrieved with XEmacPs_BdRingFromHw().

Parameters

RingPtr	is a pointer to the instance to be worked on.
NumBd	is the number of BDs to free.
BdSetPtr	is the head of a list of BDs returned by XEmacPs_BdRingFromHw().

Returns

XST_SUCCESS if the set of BDs was freed.
XST_DMA_SG_LIST_ERROR if this function was called out of sequence with XEmacPs_BdRingFromHw().

Note: This function should not be preempted by another XEmacPs_Bd function call that modifies the BD space. It is the caller's responsibility to provide a mutual exclusion mechanism.

References XEmacPs_BdRing::FreeCnt, XEmacPs_BdRing::PostCnt, and XEmacPs_BdRing::PostHead.

Referenced by EmacPsDmaSingleFrameIntrExample().

u32 XEmacPs_BdRingFromHwRx	(	XEmacPs_BdRing *	RingPtr,
		u32	BdLimit,
		XEmacPs_Bd **	BdSetPtr
	)

Returns a set of BD(s) that have been processed by hardware.

The returned BDs may be examined to determine the outcome of the DMA transaction(s). Once the BDs have been examined, the user must call XEmacPs_BdRingFree() in the same order which they were retrieved here. Example:

       NumBd = XEmacPs_BdRingFromHwRx(MyRingPtr, MaxBd, &MyBdSet),

       if (NumBd == 0)
       {
          *hardware has nothing ready for us yet*
       }

       CurBd = MyBdSet,
       for (i=0; i<NumBd; i++)
       {
          * Examine CurBd for post processing *.....

          * Onto next BD *
          CurBd = XEmacPs_BdRingNext(MyRingPtr, CurBd),
          }

          XEmacPs_BdRingFree(MyRingPtr, NumBd, MyBdSet),  * Return list *
       }

A more advanced use of this function may allocate multiple sets of BDs. They must be retrieved from hardware and freed in the correct sequence:

       * Legal *
       XEmacPs_BdRingFromHwRx(MyRingPtr, NumBd1, &MySet1),
       XEmacPs_BdRingFree(MyRingPtr, NumBd1, MySet1),

       * Legal *
       XEmacPs_BdRingFromHwRx(MyRingPtr, NumBd1, &MySet1),
       XEmacPs_BdRingFromHwRx(MyRingPtr, NumBd2, &MySet2),
       XEmacPs_BdRingFree(MyRingPtr, NumBd1, MySet1),
       XEmacPs_BdRingFree(MyRingPtr, NumBd2, MySet2),

       * Not legal *
       XEmacPs_BdRingFromHwRx(MyRingPtr, NumBd1, &MySet1),
       XEmacPs_BdRingFromHwRx(MyRingPtr, NumBd2, &MySet2),
       XEmacPs_BdRingFree(MyRingPtr, NumBd2, MySet2),
       XEmacPs_BdRingFree(MyRingPtr, NumBd1, MySet1),

If hardware has only partially completed a packet spanning multiple BDs, then none of the BDs for that packet will be included in the results.

Parameters

RingPtr	is a pointer to the instance to be worked on.
BdLimit	is the maximum number of BDs to return in the set.
BdSetPtr	is an output parameter, it points to the first BD available for examination.

Returns: The number of BDs processed by hardware. A value of 0 indicates that no data is available. No more than BdLimit BDs will be returned.

Note: Treat BDs returned by this function as read-only.; This function should not be preempted by another XEmacPs_Bd function call that modifies the BD space. It is the caller's responsibility to provide a mutual exclusion mechanism.

References XEmacPs_BdRing::HwCnt, XEmacPs_BdRing::HwHead, XEmacPs_BdRing::HwTail, XEmacPs_BdRing::PostCnt, XEMACPS_BD_STAT_OFFSET, XEmacPs_BdIsRxNew, XEmacPs_BdRead, XEmacPs_BdRingNext, and XEMACPS_RXBUF_EOF_MASK.

Referenced by EmacPsDmaSingleFrameIntrExample().

u32 XEmacPs_BdRingFromHwTx	(	XEmacPs_BdRing *	RingPtr,
		u32	BdLimit,
		XEmacPs_Bd **	BdSetPtr
	)

Returns a set of BD(s) that have been processed by hardware.

The returned BDs may be examined to determine the outcome of the DMA transaction(s). Once the BDs have been examined, the user must call XEmacPs_BdRingFree() in the same order which they were retrieved here. Example:

       NumBd = XEmacPs_BdRingFromHwTx(MyRingPtr, MaxBd, &MyBdSet),
       if (NumBd == 0)
       {
          * hardware has nothing ready for us yet*
       }

       CurBd = MyBdSet,
       for (i=0; i<NumBd; i++)
       {
          * Examine CurBd for post processing *.....

          * Onto next BD *
          CurBd = XEmacPs_BdRingNext(MyRingPtr, CurBd),
          }

          XEmacPs_BdRingFree(MyRingPtr, NumBd, MyBdSet),  *Return list*
       }

A more advanced use of this function may allocate multiple sets of BDs. They must be retrieved from hardware and freed in the correct sequence:

       * Legal *
       XEmacPs_BdRingFromHwTx(MyRingPtr, NumBd1, &MySet1),
       XEmacPs_BdRingFree(MyRingPtr, NumBd1, MySet1),

       * Legal *
       XEmacPs_BdRingFromHwTx(MyRingPtr, NumBd1, &MySet1),
       XEmacPs_BdRingFromHwTx(MyRingPtr, NumBd2, &MySet2),
       XEmacPs_BdRingFree(MyRingPtr, NumBd1, MySet1),
       XEmacPs_BdRingFree(MyRingPtr, NumBd2, MySet2),

       * Not legal *
       XEmacPs_BdRingFromHwTx(MyRingPtr, NumBd1, &MySet1),
       XEmacPs_BdRingFromHwTx(MyRingPtr, NumBd2, &MySet2),
       XEmacPs_BdRingFree(MyRingPtr, NumBd2, MySet2),
       XEmacPs_BdRingFree(MyRingPtr, NumBd1, MySet1),

If hardware has only partially completed a packet spanning multiple BDs, then none of the BDs for that packet will be included in the results.

Parameters

RingPtr	is a pointer to the instance to be worked on.
BdLimit	is the maximum number of BDs to return in the set.
BdSetPtr	is an output parameter, it points to the first BD available for examination.

Returns: The number of BDs processed by hardware. A value of 0 indicates that no data is available. No more than BdLimit BDs will be returned.

Note: Treat BDs returned by this function as read-only.; This function should not be preempted by another XEmacPs_Bd function call that modifies the BD space. It is the caller's responsibility to provide a mutual exclusion mechanism.

References XEmacPs_BdRing::HwCnt, XEmacPs_BdRing::HwHead, XEmacPs_BdRing::HwTail, XEmacPs_BdRing::PostCnt, XEMACPS_BD_STAT_OFFSET, XEmacPs_BdRead, XEmacPs_BdRingNext, XEMACPS_TXBUF_LAST_MASK, and XEMACPS_TXBUF_USED_MASK.

Referenced by EmacPsDmaSingleFrameIntrExample().

void XEmacPs_BdRingPtrReset	(	XEmacPs_BdRing *	RingPtr,
		void *	virtaddrloc
	)

Reset BD ring head and tail pointers.

Parameters

RingPtr	is the instance to be worked on.
virtaddrloc	is the virtual base address of the user memory region.

Note: Should be called after XEmacPs_Stop(); C-style signature: void XEmacPs_BdRingPtrReset(XEmacPs_BdRing * RingPtr, void *virtaddrloc)

References XEmacPs_BdRing::FreeHead, XEmacPs_BdRing::HwHead, XEmacPs_BdRing::HwTail, XEmacPs_BdRing::PostHead, and XEmacPs_BdRing::PreHead.

LONG XEmacPs_BdRingToHw	(	XEmacPs_BdRing *	RingPtr,
		u32	NumBd,
		XEmacPs_Bd *	BdSetPtr
	)

Enqueue a set of BDs to hardware that were previously allocated by XEmacPs_BdRingAlloc().

Once this function returns, the argument BD set goes under hardware control. Any changes made to these BDs after this point will corrupt the BD list leading to data corruption and system instability.

The set will be rejected if the last BD of the set does not mark the end of a packet (see XEmacPs_BdSetLast()).

Parameters

RingPtr	is a pointer to the instance to be worked on.
NumBd	is the number of BDs in the set.
BdSetPtr	is the first BD of the set to commit to hardware.

Returns

XST_SUCCESS if the set of BDs was accepted and enqueued to hardware.
XST_FAILURE if the set of BDs was rejected because the last BD of the set did not have its "last" bit set.
XST_DMA_SG_LIST_ERROR if this function was called out of sequence with XEmacPs_BdRingAlloc().

Note: This function should not be preempted by another XEmacPs_Bd function call that modifies the BD space. It is the caller's responsibility to provide a mutual exclusion mechanism.

References XEmacPs_BdRing::HwCnt, XEmacPs_BdRing::HwTail, XEmacPs_BdRing::PreCnt, XEmacPs_BdRing::PreHead, and XEmacPs_BdRingNext.

Referenced by EmacPsDmaSingleFrameIntrExample().

LONG XEmacPs_BdRingUnAlloc	(	XEmacPs_BdRing *	RingPtr,
		u32	NumBd,
		XEmacPs_Bd *	BdSetPtr
	)

Fully or partially undo an XEmacPs_BdRingAlloc() operation.

Use this function if all the BDs allocated by XEmacPs_BdRingAlloc() could not be transferred to hardware with XEmacPs_BdRingToHw().

This function helps out in situations when an unrelated error occurs after BDs have been allocated but before they have been given to hardware. An example of this type of error would be an OS running out of resources.

This function is not the same as XEmacPs_BdRingFree(). The Free function returns BDs to the free list after they have been processed by hardware, while UnAlloc returns them before being processed by hardware.

There are two scenarios where this function can be used. Full UnAlloc or Partial UnAlloc. A Full UnAlloc means all the BDs Alloc'd will be returned:

   Status = XEmacPs_BdRingAlloc(MyRingPtr, 10, &BdPtr),
       ...
   if (Error)
   {
       Status = XEmacPs_BdRingUnAlloc(MyRingPtr, 10, &BdPtr),
   }

A partial UnAlloc means some of the BDs Alloc'd will be returned:

   Status = XEmacPs_BdRingAlloc(MyRingPtr, 10, &BdPtr),
   BdsLeft = 10,
   CurBdPtr = BdPtr,

   while (BdsLeft)
   {
      if (Error)
      {
         Status = XEmacPs_BdRingUnAlloc(MyRingPtr, BdsLeft, CurBdPtr),
      }

      CurBdPtr = XEmacPs_BdRingNext(MyRingPtr, CurBdPtr),
      BdsLeft--,
   }

A partial UnAlloc must include the last BD in the list that was Alloc'd.

Parameters

RingPtr	is a pointer to the instance to be worked on.
NumBd	is the number of BDs to allocate
BdSetPtr	is an output parameter, it points to the first BD available for modification.

Returns

XST_SUCCESS if the BDs were unallocated.
XST_FAILURE if NumBd parameter was greater that the number of BDs in the preprocessing state.

Note: This function should not be preempted by another XEmacPs_Bd function call that modifies the BD space. It is the caller's responsibility to provide a mutual exclusion mechanism.

References XEmacPs_BdRing::FreeCnt, XEmacPs_BdRing::FreeHead, and XEmacPs_BdRing::PreCnt.

LONG XEmacPs_CfgInitialize	(	XEmacPs *	InstancePtr,
		XEmacPs_Config *	CfgPtr,
		UINTPTR	EffectiveAddress
	)

Initialize a specific XEmacPs instance/driver.

The initialization entails:

Initialize fields of the XEmacPs instance structure
Reset hardware and apply default options
Configure the DMA channels

The PHY is setup independently from the device. Use the MII or whatever other interface may be present for setup.

Parameters

InstancePtr	is a pointer to the instance to be worked on.
CfgPtr	is the device configuration structure containing required hardware build data.
EffectiveAddress	is the base address of the device. If address translation is not utilized, this parameter can be passed in using CfgPtr->Config.BaseAddress to specify the physical base address.

Returns

XST_SUCCESS if initialization was successful

References XEmacPs_Config::BaseAddress, XEmacPs_Config::DeviceId, XEmacPs_Config::IsCacheCoherent, XEmacPs_Config::S100MDiv0, XEmacPs_Config::S100MDiv1, XEmacPs_Config::S10MDiv0, XEmacPs_Config::S10MDiv1, XEmacPs_Config::S1GDiv0, XEmacPs_Config::S1GDiv1, XEmacPs_Reset(), and XEmacPs_StubHandler().

Referenced by EmacPsDmaIntrExample().

void XEmacPs_ClearHash ( XEmacPs * InstancePtr )

Clear the Hash registers for the mac address pointed by AddressPtr.

Parameters

InstancePtr is a pointer to the instance to be worked on.

References XEmacPs_Config::BaseAddress, XEMACPS_HASHH_OFFSET, XEMACPS_HASHL_OFFSET, and XEmacPs_WriteReg.

Referenced by XEmacPs_Reset().

LONG XEmacPs_ClearOptions	(	XEmacPs *	InstancePtr,
		u32	Options
	)

Clear options for the driver/device.

Parameters

InstancePtr	is a pointer to the instance to be worked on.
Options	are the options to clear. Multiple options can be cleared by OR'ing XEMACPS_*_OPTIONS constants together. Options not specified are not affected.

Returns

XST_SUCCESS if the options were set successfully
XST_DEVICE_IS_STARTED if the device has not yet been stopped

Note: See xemacps.h for a description of the available options.

References XEmacPs_Config::BaseAddress, XEMACPS_BROADCAST_OPTION, XEMACPS_DMACR_OFFSET, XEMACPS_DMACR_RXBUF_MASK, XEMACPS_DMACR_RXBUF_SHIFT, XEMACPS_DMACR_TCPCKSUM_MASK, XEMACPS_FCS_STRIP_OPTION, XEMACPS_FLOW_CONTROL_OPTION, XEMACPS_FRAME1536_OPTION, XEMACPS_LENTYPE_ERR_OPTION, XEMACPS_MULTICAST_OPTION, XEMACPS_NWCFG_1536RXEN_MASK, XEMACPS_NWCFG_BCASTDI_MASK, XEMACPS_NWCFG_COPYALLEN_MASK, XEMACPS_NWCFG_FCSREM_MASK, XEMACPS_NWCFG_JUMBO_MASK, XEMACPS_NWCFG_LENERRDSCRD_MASK, XEMACPS_NWCFG_MCASTHASHEN_MASK, XEMACPS_NWCFG_NVLANDISC_MASK, XEMACPS_NWCFG_OFFSET, XEMACPS_NWCFG_PAUSEEN_MASK, XEMACPS_NWCFG_PCSSEL_MASK, XEMACPS_NWCFG_RXCHKSUMEN_MASK, XEMACPS_NWCFG_SGMIIEN_MASK, XEMACPS_NWCTRL_OFFSET, XEMACPS_NWCTRL_RXEN_MASK, XEMACPS_NWCTRL_TXEN_MASK, XEMACPS_PROMISC_OPTION, XEmacPs_ReadReg, XEMACPS_RECEIVER_ENABLE_OPTION, XEMACPS_RX_BUF_SIZE, XEMACPS_RX_BUF_UNIT, XEMACPS_RX_CHKSUM_ENABLE_OPTION, XEMACPS_RXBUF_LEN_MASK, XEMACPS_TRANSMITTER_ENABLE_OPTION, XEMACPS_TX_CHKSUM_ENABLE_OPTION, XEMACPS_VLAN_OPTION, and XEmacPs_WriteReg.

Referenced by XEmacPs_Reset().

LONG XEmacPs_DeleteHash	(	XEmacPs *	InstancePtr,
		void *	AddressPtr
	)

Delete 48-bit MAC addresses in hash table.

The device must be stopped before calling this function.

Parameters

InstancePtr	is a pointer to the instance to be worked on.
AddressPtr	is a pointer to a 6-byte MAC address.

Returns

XST_SUCCESS if the HASH MAC address was deleted successfully
XST_DEVICE_IS_STARTED if the device has not yet been stopped
XST_INVALID_PARAM if the HASH MAC address passed in does not meet requirement after calculation

Note: Having Aptr be unsigned type prevents the following operations from sign extending.

References XEmacPs_Config::BaseAddress, XEMACPS_HASHH_OFFSET, XEMACPS_HASHL_OFFSET, XEMACPS_MAX_HASH_BITS, XEmacPs_ReadReg, and XEmacPs_WriteReg.

void XEmacPs_DMABLengthUpdate	(	XEmacPs *	InstancePtr,
		s32	BLength
	)

API to update the Burst length in the DMACR register.

Parameters

InstancePtr	is a pointer to the XEmacPs instance to be worked on.
BLength	is the length in bytes for the dma burst.

Returns: None

References XEmacPs_Config::BaseAddress, XEMACPS_DMACR_BLENGTH_MASK, XEMACPS_DMACR_INCR16_AHB_BURST, XEMACPS_DMACR_INCR4_AHB_BURST, XEMACPS_DMACR_INCR8_AHB_BURST, XEMACPS_DMACR_OFFSET, XEMACPS_DMACR_SINGLE_AHB_BURST, XEmacPs_ReadReg, and XEmacPs_WriteReg.

void XEmacPs_GetHash	(	XEmacPs *	InstancePtr,
		void *	AddressPtr
	)

Get the Hash address for this driver/device.

Parameters

InstancePtr	is a pointer to the instance to be worked on.
AddressPtr	is an output parameter, and is a pointer to a buffer into which the current HASH MAC address will be copied.

References XEmacPs_Config::BaseAddress, XEMACPS_HASHH_OFFSET, XEMACPS_HASHL_OFFSET, and XEmacPs_ReadReg.

void XEmacPs_GetMacAddress	(	XEmacPs *	InstancePtr,
		void *	AddressPtr,
		u8	Index
	)

Get the MAC address for this driver/device.

Parameters

InstancePtr	is a pointer to the instance to be worked on.
AddressPtr	is an output parameter, and is a pointer to a buffer into which the current MAC address will be copied.
Index	is a index to which MAC (1-4) address.

References XEmacPs_Config::BaseAddress, XEMACPS_LADDR1H_OFFSET, XEMACPS_LADDR1L_OFFSET, XEMACPS_MAX_MAC_ADDR, and XEmacPs_ReadReg.

u16 XEmacPs_GetOperatingSpeed ( XEmacPs * InstancePtr )

XEmacPs_GetOperatingSpeed gets the current operating link speed.

This may be the value set by XEmacPs_SetOperatingSpeed() or a hardware default.

Parameters

InstancePtr references the TEMAC channel on which to operate.

Returns: XEmacPs_GetOperatingSpeed returns the link speed in units of megabits per second.

Note

References XEmacPs_Config::BaseAddress, XEMACPS_NWCFG_1000_MASK, XEMACPS_NWCFG_100_MASK, XEMACPS_NWCFG_OFFSET, and XEmacPs_ReadReg.

u32 XEmacPs_GetOptions ( XEmacPs * InstancePtr )

Get current option settings.

Parameters

InstancePtr is a pointer to the instance to be worked on.

Returns: A bitmask of XTE_*_OPTION constants. Any bit set to 1 is to be interpreted as a set option.

Note: See xemacps.h for a description of the available options.

u32 XEmacPs_GetQxOffset	(	XEmacPs_QxRegOffset	RegName,
		u8	Queue
	)

The register offset of a specific queue register is returned by this function.

Parameters

RegName	Basename of the register
Queue	Corresponsing Queue

Returns: Register offset

References XEMACPS_DMA_RXQ1_BUFSIZE_OFFSET, XEMACPS_INTQ1_IDR_OFFSET, XEMACPS_INTQ1_IER_OFFSET, XEMACPS_INTQ1_STS_OFFSET, XEMACPS_ISR_OFFSET, XEMACPS_RXQ1BASE_OFFSET, XEMACPS_RXQBASE_OFFSET, XEMACPS_TXQ1BASE_OFFSET, and XEMACPS_TXQBASE_OFFSET.

Referenced by XEmacPs_IntrHandler(), XEmacPs_Reset(), and XEmacPs_SetQueuePtr().

void XEmacPs_IntrHandler ( void * XEmacPsPtr )

Master interrupt handler for EMAC driver.

This routine will query the status of the device, bump statistics, and invoke user callbacks.

This routine must be connected to an interrupt controller using OS/BSP specific methods.

Parameters

XEmacPsPtr is a pointer to the XEMACPS instance that has caused the interrupt.

References XEmacPs_Config::BaseAddress, XEmacPs_GetQxOffset(), XEMACPS_ISR_OFFSET, XEMACPS_IXR_RXUSED_MASK, XEMACPS_IXR_TXCOMPL_MASK, XEMACPS_NWCTRL_FLUSH_DPRAM_MASK, XEMACPS_NWCTRL_OFFSET, XEmacPs_ReadReg, XEMACPS_RECV, XEMACPS_RXSR_BUFFNA_MASK, XEMACPS_RXSR_FRAMERX_MASK, XEMACPS_RXSR_OFFSET, XEMACPS_SEND, XEMACPS_TXSR_OFFSET, XEMACPS_TXSR_TXCOMPL_MASK, XEMACPS_TXSR_USEDREAD_MASK, and XEmacPs_WriteReg.

Referenced by EmacPsDmaIntrExample().

XEmacPs_Config * XEmacPs_LookupConfig ( u16 DeviceId )

Lookup the device configuration based on the unique device ID.

The table contains the configuration info for each device in the system.

Parameters

DeviceId is the unique device ID of the device being looked up.

Returns: A pointer to the configuration table entry corresponding to the given device ID, or NULL if no match is found.

Referenced by EmacPsDmaIntrExample().

LONG XEmacPs_PhyRead	(	XEmacPs *	InstancePtr,
		u32	PhyAddress,
		u32	RegisterNum,
		u16 *	PhyDataPtr
	)

Read the current value of the PHY register indicated by the PhyAddress and the RegisterNum parameters.

The MAC provides the driver with the ability to talk to a PHY that adheres to the Media Independent Interface (MII) as defined in the IEEE 802.3 standard.

Prior to PHY access with this function, the user should have setup the MDIO clock with XEmacPs_SetMdioDivisor().

Parameters

InstancePtr	is a pointer to the XEmacPs instance to be worked on.
PhyAddress	is the address of the PHY to be read (supports multiple PHYs)
RegisterNum	is the register number, 0-31, of the specific PHY register to read
PhyDataPtr	is an output parameter, and points to a 16-bit buffer into which the current value of the register will be copied.

Returns

XST_SUCCESS if the PHY was read from successfully
XST_EMAC_MII_BUSY if there is another PHY operation in progress

Note

This function is not thread-safe. The user must provide mutually exclusive access to this function if there are to be multiple threads that can call it.

There is the possibility that this function will not return if the hardware is broken (i.e., it never sets the status bit indicating that the read is done). If this is of concern to the user, the user should provide a mechanism suitable to their needs for recovery.

For the duration of this function, all host interface reads and writes are blocked to the current XEmacPs instance.

References XEmacPs_Config::BaseAddress, XEMACPS_NWSR_MDIOIDLE_MASK, XEMACPS_NWSR_OFFSET, XEMACPS_PHYMNTNC_OFFSET, XEMACPS_PHYMNTNC_OP_MASK, XEMACPS_PHYMNTNC_OP_R_MASK, XEMACPS_PHYMNTNC_PHAD_SHFT_MSK, XEMACPS_PHYMNTNC_PREG_SHFT_MSK, XEmacPs_ReadReg, and XEmacPs_WriteReg.

LONG XEmacPs_PhyWrite	(	XEmacPs *	InstancePtr,
		u32	PhyAddress,
		u32	RegisterNum,
		u16	PhyData
	)

Write data to the specified PHY register.

The Ethernet driver does not require the device to be stopped before writing to the PHY. Although it is probably a good idea to stop the device, it is the responsibility of the application to deem this necessary. The MAC provides the driver with the ability to talk to a PHY that adheres to the Media Independent Interface (MII) as defined in the IEEE 802.3 standard.

Prior to PHY access with this function, the user should have setup the MDIO clock with XEmacPs_SetMdioDivisor().

Parameters

InstancePtr	is a pointer to the XEmacPs instance to be worked on.
PhyAddress	is the address of the PHY to be written (supports multiple PHYs)
RegisterNum	is the register number, 0-31, of the specific PHY register to write
PhyData	is the 16-bit value that will be written to the register

Returns

XST_SUCCESS if the PHY was written to successfully. Since there is no error status from the MAC on a write, the user should read the PHY to verify the write was successful.
XST_EMAC_MII_BUSY if there is another PHY operation in progress

Note

This function is not thread-safe. The user must provide mutually exclusive access to this function if there are to be multiple threads that can call it.

There is the possibility that this function will not return if the hardware is broken (i.e., it never sets the status bit indicating that the write is done). If this is of concern to the user, the user should provide a mechanism suitable to their needs for recovery.

For the duration of this function, all host interface reads and writes are blocked to the current XEmacPs instance.

References XEmacPs_Config::BaseAddress, XEMACPS_NWSR_MDIOIDLE_MASK, XEMACPS_NWSR_OFFSET, XEMACPS_PHYMNTNC_OFFSET, XEMACPS_PHYMNTNC_OP_MASK, XEMACPS_PHYMNTNC_OP_W_MASK, XEMACPS_PHYMNTNC_PHAD_SHFT_MSK, XEMACPS_PHYMNTNC_PREG_SHFT_MSK, XEmacPs_ReadReg, and XEmacPs_WriteReg.

void XEmacPs_Reset ( XEmacPs * InstancePtr )

Perform a graceful reset of the Ethernet MAC.

Resets the DMA channels, the transmitter, and the receiver.

Steps to reset

Stops transmit and receive channels
Stops DMA
Configure transmit and receive buffer size to default
Clear transmit and receive status register and counters
Clear all interrupt sources
Clear phy (if there is any previously detected) address
Clear MAC addresses (1-4) as well as Type IDs and hash value

All options are placed in their default state. Any frames in the descriptor lists will remain in the lists. The side effect of doing this is that after a reset and following a restart of the device, frames were in the list before the reset may be transmitted or received.

The upper layer software is responsible for re-configuring (if necessary) and restarting the MAC after the reset. Note also that driver statistics are not cleared on reset. It is up to the upper layer software to clear the statistics if needed.

When a reset is required, the driver notifies the upper layer software of this need through the ErrorHandler callback and specific status codes. The upper layer software is responsible for calling this Reset function and then re-configuring the device.

Parameters

InstancePtr is a pointer to the instance to be worked on.

References XEmacPs_Config::BaseAddress, XEmacPs_ClearHash(), XEmacPs_ClearOptions(), XEMACPS_DEFAULT_OPTIONS, XEMACPS_DMACR_ADDR_WIDTH_64, XEMACPS_DMACR_INCR16_AHB_BURST, XEMACPS_DMACR_OFFSET, XEMACPS_DMACR_RXBUF_MASK, XEMACPS_DMACR_RXBUF_SHIFT, XEMACPS_DMACR_RXSIZE_MASK, XEMACPS_DMACR_TXSIZE_MASK, XEmacPs_GetQxOffset(), XEMACPS_IDR_OFFSET, XEMACPS_ISR_OFFSET, XEMACPS_IXR_ALL_MASK, XEMACPS_LAST_OFFSET, XEMACPS_NWCFG_100_MASK, XEMACPS_NWCFG_DWIDTH_64_MASK, XEMACPS_NWCFG_FDEN_MASK, XEMACPS_NWCFG_MDCCLKDIV_MASK, XEMACPS_NWCFG_OFFSET, XEMACPS_NWCFG_UCASTHASHEN_MASK, XEMACPS_NWCTRL_LOOPEN_MASK, XEMACPS_NWCTRL_MDEN_MASK, XEMACPS_NWCTRL_OFFSET, XEMACPS_NWCTRL_RXEN_MASK, XEMACPS_NWCTRL_STATCLR_MASK, XEMACPS_OCTTXL_OFFSET, XEmacPs_ReadReg, XEMACPS_RECEIVER_ENABLE_OPTION, XEMACPS_RECV, XEMACPS_RX_BUF_SIZE, XEMACPS_RX_BUF_UNIT, XEMACPS_RXBUF_LEN_MASK, XEMACPS_RXSR_OFFSET, XEMACPS_SEND, XEmacPs_SetMacAddress(), XEmacPs_SetOptions(), XEmacPs_SetQueuePtr(), XEmacPs_SetTypeIdCheck(), XEMACPS_SR_ALL_MASK, XEmacPs_Stop(), XEMACPS_TRANSMITTER_ENABLE_OPTION, XEMACPS_TXSR_OFFSET, and XEmacPs_WriteReg.

Referenced by XEmacPs_CfgInitialize().

void XEmacPs_ResetHw ( u32 BaseAddr )

This function perform the reset sequence to the given emacps interface by configuring the appropriate control bits in the emacps specific registers.

the emacps reset sequence involves the following steps Disable all the interuupts Clear the status registers Disable Rx and Tx engines Update the Tx and Rx descriptor queue registers with reset values Update the other relevant control registers with reset value

Parameters

BaseAddr of the interface

Returns: N/A

Note: This function will not modify the slcr registers that are relevant for emacps controller

References XEMACPS_HASHH_OFFSET, XEMACPS_HASHL_OFFSET, XEMACPS_IDR_OFFSET, XEMACPS_ISR_OFFSET, XEMACPS_IXR_ALL_MASK, XEMACPS_NWCFG_OFFSET, XEMACPS_NWCFG_RESET_MASK, XEMACPS_NWCTRL_FLUSH_DPRAM_MASK, XEMACPS_NWCTRL_HALTTX_MASK, XEMACPS_NWCTRL_LOOPEN_MASK, XEMACPS_NWCTRL_OFFSET, XEMACPS_NWCTRL_RXEN_MASK, XEMACPS_NWCTRL_STATCLR_MASK, XEMACPS_NWCTRL_TXEN_MASK, XEmacPs_ReadReg, XEMACPS_RXQBASE_OFFSET, XEMACPS_RXSR_FRAMERX_MASK, XEMACPS_RXSR_OFFSET, XEMACPS_TXQBASE_OFFSET, XEMACPS_TXSR_OFFSET, XEMACPS_TXSR_TXCOMPL_MASK, XEMACPS_TXSR_TXGO_MASK, and XEmacPs_WriteReg.

LONG XEmacPs_SendPausePacket ( XEmacPs * InstancePtr )

Send a pause packet.

Parameters

InstancePtr is a pointer to the instance to be worked on.

Returns

XST_SUCCESS if pause frame transmission was initiated
XST_DEVICE_IS_STOPPED if the device has not been started.

References XEmacPs_Config::BaseAddress, XEMACPS_NWCTRL_OFFSET, XEMACPS_NWCTRL_PAUSETX_MASK, XEmacPs_ReadReg, and XEmacPs_WriteReg.

LONG XEmacPs_SetHandler	(	XEmacPs *	InstancePtr,
		u32	HandlerType,
		void *	FuncPointer,
		void *	CallBackRef
	)

Install an asynchronous handler function for the given HandlerType:

Parameters

InstancePtr	is a pointer to the instance to be worked on.
HandlerType	indicates what interrupt handler type is. XEMACPS_HANDLER_DMASEND, XEMACPS_HANDLER_DMARECV and XEMACPS_HANDLER_ERROR.
FuncPointer	is the pointer to the callback function
CallBackRef	is the upper layer callback reference passed back when when the callback function is invoked.

Returns

None.

Note: There is no assert on the CallBackRef since the driver doesn't know what it is.

Referenced by EmacPsDmaIntrExample().

LONG XEmacPs_SetHash	(	XEmacPs *	InstancePtr,
		void *	AddressPtr
	)

Set 48-bit MAC addresses in hash table.

The device must be stopped before calling this function.

The hash address register is 64 bits long and takes up two locations in the memory map. The least significant bits are stored in hash register bottom and the most significant bits in hash register top.

The unicast hash enable and the multicast hash enable bits in the network configuration register enable the reception of hash matched frames. The destination address is reduced to a 6 bit index into the 64 bit hash register using the following hash function. The hash function is an XOR of every sixth bit of the destination address.

hash_index[05] = da[05]^da[11]^da[17]^da[23]^da[29]^da[35]^da[41]^da[47]
hash_index[04] = da[04]^da[10]^da[16]^da[22]^da[28]^da[34]^da[40]^da[46]
hash_index[03] = da[03]^da[09]^da[15]^da[21]^da[27]^da[33]^da[39]^da[45]
hash_index[02] = da[02]^da[08]^da[14]^da[20]^da[26]^da[32]^da[38]^da[44]
hash_index[01] = da[01]^da[07]^da[13]^da[19]^da[25]^da[31]^da[37]^da[43]
hash_index[00] = da[00]^da[06]^da[12]^da[18]^da[24]^da[30]^da[36]^da[42]

da[0] represents the least significant bit of the first byte received, that is, the multicast/unicast indicator, and da[47] represents the most significant bit of the last byte received.

If the hash index points to a bit that is set in the hash register then the frame will be matched according to whether the frame is multicast or unicast.

A multicast match will be signaled if the multicast hash enable bit is set, da[0] is logic 1 and the hash index points to a bit set in the hash register.

A unicast match will be signaled if the unicast hash enable bit is set, da[0] is logic 0 and the hash index points to a bit set in the hash register.

To receive all multicast frames, the hash register should be set with all ones and the multicast hash enable bit should be set in the network configuration register.

Parameters

InstancePtr	is a pointer to the instance to be worked on.
AddressPtr	is a pointer to a 6-byte MAC address.

Returns

XST_SUCCESS if the HASH MAC address was set successfully
XST_DEVICE_IS_STARTED if the device has not yet been stopped
XST_INVALID_PARAM if the HASH MAC address passed in does not meet requirement after calculation

Note: Having Aptr be unsigned type prevents the following operations from sign extending.

References XEmacPs_Config::BaseAddress, XEMACPS_HASHH_OFFSET, XEMACPS_HASHL_OFFSET, XEMACPS_MAX_HASH_BITS, XEmacPs_ReadReg, and XEmacPs_WriteReg.

LONG XEmacPs_SetMacAddress	(	XEmacPs *	InstancePtr,
		void *	AddressPtr,
		u8	Index
	)

Set the MAC address for this driver/device.

The address is a 48-bit value. The device must be stopped before calling this function.

Parameters

InstancePtr	is a pointer to the instance to be worked on.
AddressPtr	is a pointer to a 6-byte MAC address.
Index	is a index to which MAC (1-4) address.

Returns

XST_SUCCESS if the MAC address was set successfully
XST_DEVICE_IS_STARTED if the device has not yet been stopped

References XEmacPs_Config::BaseAddress, XEMACPS_LADDR1H_OFFSET, XEMACPS_LADDR1L_OFFSET, XEMACPS_LADDR_MACH_MASK, XEMACPS_MAX_MAC_ADDR, XEmacPs_ReadReg, and XEmacPs_WriteReg.

Referenced by EmacPsDmaIntrExample(), and XEmacPs_Reset().

void XEmacPs_SetMdioDivisor	(	XEmacPs *	InstancePtr,
		XEmacPs_MdcDiv	Divisor
	)

Set the MDIO clock divisor.

Calculating the divisor:

             f[HOSTCLK]
  f[MDC] = -----------------
           (1 + Divisor) * 2

where f[HOSTCLK] is the bus clock frequency in MHz, and f[MDC] is the MDIO clock frequency in MHz to the PHY. Typically, f[MDC] should not exceed 2.5 MHz. Some PHYs can tolerate faster speeds which means faster access. Here is the table to show values to generate MDC,

000 : divide pclk by   8 (pclk up to  20 MHz)
001 : divide pclk by  16 (pclk up to  40 MHz)
010 : divide pclk by  32 (pclk up to  80 MHz)
011 : divide pclk by  48 (pclk up to 120 MHz)
100 : divide pclk by  64 (pclk up to 160 MHz)
101 : divide pclk by  96 (pclk up to 240 MHz)
110 : divide pclk by 128 (pclk up to 320 MHz)
111 : divide pclk by 224 (pclk up to 540 MHz)

Parameters

InstancePtr	is a pointer to the instance to be worked on.
Divisor	is the divisor to set. Range is 0b000 to 0b111.

References XEmacPs_Config::BaseAddress, XEMACPS_NWCFG_MDC_SHIFT_MASK, XEMACPS_NWCFG_MDCCLKDIV_MASK, XEMACPS_NWCFG_OFFSET, XEmacPs_ReadReg, and XEmacPs_WriteReg.

Referenced by EmacPsDmaIntrExample().

void XEmacPs_SetOperatingSpeed	(	XEmacPs *	InstancePtr,
		u16	Speed
	)

XEmacPs_SetOperatingSpeed sets the current operating link speed.

For any traffic to be passed, this speed must match the current MII/GMII/SGMII/RGMII link speed.

Parameters

InstancePtr	references the TEMAC channel on which to operate.
Speed	is the speed to set in units of Mbps. Valid values are 10, 100, or 1000. XEmacPs_SetOperatingSpeed ignores invalid values.

Note

References XEmacPs_Config::BaseAddress, XEMACPS_NWCFG_1000_MASK, XEMACPS_NWCFG_100_MASK, XEMACPS_NWCFG_OFFSET, XEmacPs_ReadReg, and XEmacPs_WriteReg.

Referenced by EmacPsDmaIntrExample().

LONG XEmacPs_SetOptions	(	XEmacPs *	InstancePtr,
		u32	Options
	)

Set options for the driver/device.

The driver should be stopped with XEmacPs_Stop() before changing options.

Parameters

InstancePtr	is a pointer to the instance to be worked on.
Options	are the options to set. Multiple options can be set by OR'ing XTE_*_OPTIONS constants together. Options not specified are not affected.

Returns

XST_SUCCESS if the options were set successfully
XST_DEVICE_IS_STARTED if the device has not yet been stopped

Note: See xemacps.h for a description of the available options.

Referenced by EmacPsDmaIntrExample(), and XEmacPs_Reset().

void XEmacPs_SetQueuePtr	(	XEmacPs *	InstancePtr,
		UINTPTR	QPtr,
		u8	QueueNum,
		u16	Direction
	)

This function sets the start address of the transmit/receive buffer queue.

Parameters

InstancePtr	is a pointer to the instance to be worked on.
QPtr	is the address of the Queue to be written
QueueNum	is the Buffer Queue Index
Direction	indicates Transmit/Receive

Note: The buffer queue addresses has to be set before starting the transfer, so this function has to be called in prior to XEmacPs_Start()

References XEmacPs_Config::BaseAddress, XEmacPs_GetQxOffset(), XEMACPS_MSBBUF_RXQBASE_OFFSET, XEMACPS_MSBBUF_TXQBASE_OFFSET, XEMACPS_SEND, and XEmacPs_WriteReg.

Referenced by EmacPsDmaSingleFrameIntrExample(), and XEmacPs_Reset().

LONG XEmacPs_SetTypeIdCheck	(	XEmacPs *	InstancePtr,
		u32	Id_Check,
		u8	Index
	)

Set the Type ID match for this driver/device.

The register is a 32-bit value. The device must be stopped before calling this function.

Parameters

InstancePtr	is a pointer to the instance to be worked on.
Id_Check	is type ID to be configured.
Index	is a index to which Type ID (1-4).

Returns

XST_SUCCESS if the MAC address was set successfully
XST_DEVICE_IS_STARTED if the device has not yet been stopped

References XEmacPs_Config::BaseAddress, XEMACPS_MATCH1_OFFSET, XEMACPS_MAX_TYPE_ID, and XEmacPs_WriteReg.

Referenced by XEmacPs_Reset().

void XEmacPs_Start ( XEmacPs * InstancePtr )

Start the Ethernet controller as follows:

Enable transmitter if XTE_TRANSMIT_ENABLE_OPTION is set
Enable receiver if XTE_RECEIVER_ENABLE_OPTION is set
Start the SG DMA send and receive channels and enable the device interrupt

Parameters

InstancePtr is a pointer to the instance to be worked on.

Returns: N/A

Note: Hardware is configured with scatter-gather DMA, the driver expects to start the scatter-gather channels and expects that the user has previously set up the buffer descriptor lists.

This function makes use of internal resources that are shared between the Start, Stop, and Set/ClearOptions functions. So if one task might be setting device options while another is trying to start the device, the user is required to provide protection of this shared data (typically using a semaphore).

This function must not be preempted by an interrupt that may service the device.

References XEmacPs_Config::BaseAddress, XEmacPs_BdRing::BaseBdAddr, XEmacPs_IntEnable, XEmacPs_IntQiEnable, XEMACPS_ISR_OFFSET, XEMACPS_IXR_ALL_MASK, XEMACPS_IXR_FRAMERX_MASK, XEMACPS_IXR_TXCOMPL_MASK, XEMACPS_NWCTRL_OFFSET, XEMACPS_NWCTRL_RXEN_MASK, XEMACPS_NWCTRL_TXEN_MASK, XEmacPs_ReadReg, XEMACPS_RECEIVER_ENABLE_OPTION, XEMACPS_RXQBASE_OFFSET, XEMACPS_TRANSMITTER_ENABLE_OPTION, XEMACPS_TXQBASE_OFFSET, and XEmacPs_WriteReg.

Referenced by EmacPsDmaSingleFrameIntrExample().

void XEmacPs_Stop ( XEmacPs * InstancePtr )

Gracefully stop the Ethernet MAC as follows:

Disable all interrupts from this device
Stop DMA channels
Disable the tansmitter and receiver

Device options currently in effect are not changed.

This function will disable all interrupts. Default interrupts settings that had been enabled will be restored when XEmacPs_Start() is called.

Parameters

InstancePtr is a pointer to the instance to be worked on.

Note: This function makes use of internal resources that are shared between the Start, Stop, SetOptions, and ClearOptions functions. So if one task might be setting device options while another is trying to start the device, the user is required to provide protection of this shared data (typically using a semaphore).

Stopping the DMA channels causes this function to block until the DMA operation is complete.

References XEmacPs_Config::BaseAddress, XEMACPS_IDR_OFFSET, XEMACPS_IXR_ALL_MASK, XEMACPS_NWCTRL_OFFSET, XEMACPS_NWCTRL_RXEN_MASK, XEMACPS_NWCTRL_TXEN_MASK, XEmacPs_ReadReg, and XEmacPs_WriteReg.

Referenced by EmacPsDmaIntrExample(), EmacPsDmaSingleFrameIntrExample(), and XEmacPs_Reset().

void XEmacPs_StubHandler ( void )

This is a stub for the asynchronous callbacks.

The stub is here in case the upper layer forgot to set the handler(s). On initialization, all handlers are set to this callback. It is considered an error for this handler to be invoked.

Referenced by XEmacPs_CfgInitialize().

Data Structures

Macros

Typedefs

Functions

Configuration options

Callback identifiers

Typedefs for callback functions

Direction identifiers

MDC clock division

network control register bit definitions

network configuration register bit definitions

network status register bit definitaions

MAC address register word 1 mask

DMA control register bit definitions

transmit status register bit definitions

receive status register bit definitions

PCS control register bit definitions

PCS status register bit definitions

Interrupt Q1 status register bit definitions

interrupts bit definitions

PHY Maintenance bit definitions

RX watermark bit definitions

Screening Type2 bit definitions

Queue Registers Offset

Macro Definition Documentation

Typedef Documentation

Function Documentation