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emacps
Vitis Drivers API Documentation
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emacps
Vitis Drivers API Documentation
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This typedef contains configuration information for a device. More...
#include <xemacps.h>
Data Fields | |
| char * | Name |
| Unique name of the device. More... | |
| UINTPTR | BaseAddress |
| Physical base address of IPIF registers. More... | |
| u8 | IsCacheCoherent |
| Applicable only to A53 in EL1 mode; describes whether Cache Coherent or not. More... | |
| u16 | IntrId |
| Interrupt number. More... | |
| UINTPTR | IntrParent |
| Parent interrupt controller address. More... | |
| u32 | RefClk |
| Input clock. More... | |
| char * | PhyType |
| PhyType indicates which type of PHY interface is used (MII, GMII, RGMII, etc. More... | |
| u32 | PhyAddr |
| PHY address for MDIO register access. More... | |
| UINTPTR | MdioProducerBaseAddr |
| GEM Base address of MDIO Master. More... | |
| u32 | GmiitoRgmiiConvPhyAddr |
| GMII-to-RGMII converter PHY address. More... | |
| u16 | S1GDiv0 |
| 1Gbps Clock Divider 0 More... | |
| u8 | S1GDiv1 |
| 1Gbps Clock Divider 1 More... | |
| u16 | S100MDiv0 |
| 100Mbps Clock Divider 0 More... | |
| u8 | S100MDiv1 |
| 100Mbps Clock Divider 1 More... | |
| u16 | S10MDiv0 |
| 10Mbps Clock Divider 0 More... | |
| u8 | S10MDiv1 |
| 10Mbps Clock Divider 1 More... | |
This typedef contains configuration information for a device.
| UINTPTR XEmacPs_Config::BaseAddress |
Physical base address of IPIF registers.
Referenced by EmacPsDmaIntrExample(), EmacPsDmaSingleFrameIntrExample(), EmacPsUtilEnterLocalLoopback(), main(), XEmacPs_CfgInitialize(), XEmacPs_ClearHash(), XEmacPs_ClearOptions(), XEmacPs_DeleteHash(), XEmacPs_DMABLengthUpdate(), XEmacPs_GetHash(), XEmacPs_GetMacAddress(), XEmacPs_GetOperatingSpeed(), XEmacPs_IntrHandler(), XEmacPs_IsCommonMdioPresent(), XEmacPs_PhyRead(), XEmacPs_PhyWrite(), XEmacPs_Reset(), XEmacPs_SendPausePacket(), XEmacPs_SetHash(), XEmacPs_SetMacAddress(), XEmacPs_SetMdioDivisor(), XEmacPs_SetOperatingSpeed(), XEmacPs_SetOptions(), XEmacPs_SetQueuePtr(), XEmacPs_SetTypeIdCheck(), XEmacPs_SetupPCS(), XEmacPs_Start(), XEmacPs_Stop(), and XEmacPsClkSetup().
| u32 XEmacPs_Config::GmiitoRgmiiConvPhyAddr |
GMII-to-RGMII converter PHY address.
Referenced by XEmacPs_CfgInitialize().
| u16 XEmacPs_Config::IntrId |
Interrupt number.
Referenced by EmacPsDmaIntrExample(), and XEmacPs_CfgInitialize().
| UINTPTR XEmacPs_Config::IntrParent |
Parent interrupt controller address.
Referenced by EmacPsDmaIntrExample(), and XEmacPs_CfgInitialize().
| u8 XEmacPs_Config::IsCacheCoherent |
Applicable only to A53 in EL1 mode; describes whether Cache Coherent or not.
Referenced by EmacPsDmaSingleFrameIntrExample(), and XEmacPs_CfgInitialize().
| UINTPTR XEmacPs_Config::MdioProducerBaseAddr |
GEM Base address of MDIO Master.
Referenced by XEmacPs_CfgInitialize(), XEmacPs_IsCommonMdioPresent(), XEmacPs_PhyRead(), XEmacPs_PhyWrite(), XEmacPs_Reset(), and XEmacPs_SetMdioDivisor().
| char* XEmacPs_Config::Name |
Unique name of the device.
Referenced by XEmacPs_LookupConfig().
| u32 XEmacPs_Config::PhyAddr |
PHY address for MDIO register access.
Referenced by XEmacPs_CfgInitialize().
| char* XEmacPs_Config::PhyType |
PhyType indicates which type of PHY interface is used (MII, GMII, RGMII, etc.
Referenced by XEmacPs_CfgInitialize().
| u32 XEmacPs_Config::RefClk |
Input clock.
Referenced by XEmacPs_CfgInitialize(), XEmacPs_Start(), and XEmacPs_Stop().
| u16 XEmacPs_Config::S100MDiv0 |
100Mbps Clock Divider 0
Referenced by XEmacPs_CfgInitialize().
| u8 XEmacPs_Config::S100MDiv1 |
100Mbps Clock Divider 1
Referenced by XEmacPs_CfgInitialize().
| u16 XEmacPs_Config::S10MDiv0 |
10Mbps Clock Divider 0
Referenced by XEmacPs_CfgInitialize().
| u8 XEmacPs_Config::S10MDiv1 |
10Mbps Clock Divider 1
Referenced by XEmacPs_CfgInitialize().
| u16 XEmacPs_Config::S1GDiv0 |
1Gbps Clock Divider 0
Referenced by XEmacPs_CfgInitialize(), and XEmacPsClkSetup().
| u8 XEmacPs_Config::S1GDiv1 |
1Gbps Clock Divider 1
Referenced by XEmacPs_CfgInitialize(), and XEmacPsClkSetup().
