Vitis Drivers API Documentation
gpiops Documentation

The Xilinx PS GPIO driver. This driver supports the Xilinx PS GPIO Controller.

The GPIO Controller supports the following features:

  • 6 banks
  • Masked writes (There are no masked reads)
  • Bypass mode
  • Configurable Interrupts (Level/Edge)

This driver is intended to be RTOS and processor independent. Any needs for dynamic memory management, threads or thread mutual exclusion, virtual memory, or cache control must be satisfied by the layer above this driver.

Here is GPIO Bank and Pin mapping information for different platforms. Zynq: PS GPIO contain 4 banks and 118 pins Bank 0 MIO pins 0 - 31 Bank 1 MIO pins 32 - 53 Bank 2 MIO pins 54 - 85 Bank 3 EMIO signals 86 - 117

Zynq Ultrascale+ MP: PS GPIO contain 6 banks and 174 pins Bank 0 MIO pins 0 - 25 Bank 1 MIO pins 26 - 51 Bank 2 MIO pins 52 - 77 Bank 3 EMIO signals 78 - 109 Bank 4 EMIO signals 110 - 141 Bank 5 EMIO signals 142 - 173

Versal: Two GPIOPS instances PMC GPIO and PS GPIO PMC GPIO contain 4 banks and 116 pins Bank 0 MIO pins 0 - 25 Bank 1 MIO pins 26 - 51 Bank 3 EMIO signals 52 - 83 Bank 4 EMIO signals 84 - 115 PS GPIO contains 2 banks and 58 pins Bank 0 MIO pins 0 - 25 Bank 3 EMIO signals 26-57

This driver supports all the features listed above, if applicable.

Driver Description

The device driver enables higher layer software (e.g., an application) to communicate to the GPIO.


The driver provides interrupt management functions and an interrupt handler. Users of this driver need to provide callback functions. An interrupt handler example is available with the driver.


This driver is not thread safe. Any needs for threads or thread mutual exclusion must be satisfied by the layer above this driver.


Asserts are used within all Xilinx drivers to enforce constraints on argument values. Asserts can be turned off on a system-wide basis by defining, at compile time, the NDEBUG identifier. By default, asserts are turned on and it is recommended that users leave asserts on during development.

Building the driver

The XGpioPs driver is composed of several source files. This allows the user to build and link only those parts of the driver that are necessary.

Ver   Who  Date     Changes

1.00a sv 01/15/10 First Release 1.01a sv 04/15/12 Removed the APIs XGpioPs_SetMode, XGpioPs_SetModePin XGpioPs_GetMode, XGpioPs_GetModePin as they are not relevant to Zynq device.The interrupts are disabled for output pins on all banks during initialization. 1.02a hk 08/22/13 Added low level reset API 2.1 hk 04/29/14 Use Input data register DATA_RO for read. CR# 771667. 2.2 sk 10/13/14 Used Pin number in Bank instead of pin number passed to APIs. CR# 822636 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance. 3.1 kvn 04/13/15 Add support for Zynq Ultrascale+ MP. CR# 856980. ms 03/17/17 Added readme.txt file in examples folder for doxygen generation. ms 04/05/17 Added tabspace for return statements in functions of gpiops examples for proper documentation while generating doxygen. 3.3 ms 04/17/17 Added notes about gpio input and output pin description for zcu102 and zc702 boards in polled and interrupt example, configured Interrupt pin to input pin for proper functioning of interrupt example. 3.4 aru 08/17/18 Resolved MISRA-C mandatory violations. CR# 1007751 3.5 sne 03/01/19 Fixes violations according to MISRAC-2012 in safety mode and modified the code such as Use of mixed mode arithmetic,Declared the pointer param as Pointer to const,Casting operation to a pointer, Literal value requires a U suffix. 3.5 sne 03/14/19 Added Versal support. 3.6 mus 04/05/19 Replaced XPLAT_versal macro with XPLAT_VERSAL, to be in sync with standalone BSP 3.6 sne 06/12/19 Fixed IAR compiler warning. 3.6 sne 08/14/19 Added interrupt handler support on versal. 3.7 sne 12/04/19 Reverted versal examples support. 3.8 sne 08/28/20 Modify Makefile to support parallel make execution. 3.8 sne 09/17/20 Added description for Versal PS and PMC GPIO pins. 3.9 sne 03/15/21 Fixed MISRA-C violations. 3.11 sg 02/23/23 Update bank and pin mapping information.