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mipicsiss
Vitis Drivers API Documentation
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mipicsiss
Vitis Drivers API Documentation
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MIPI CSI Rx Subsystem configuration structure. More...
#include <xcsiss.h>
Data Fields | |
| UINTPTR | BaseAddr |
BaseAddress is the physical base address of the subsystem address range More... | |
| UINTPTR | HighAddr |
HighAddress is the physical MAX address of the subsystem address range More... | |
| u32 | LanesPresent |
| Number of PPI Lanes in the design. More... | |
| u32 | PixelCount |
| Number of Pixels per clock 1,2,4. More... | |
| u32 | PixelFormat |
| The pixel format selected from all RGB, RAW and YUV422 8bit options. More... | |
| u32 | VcNo |
| Number of Virtual Channels supported by system. More... | |
| u32 | CsiBuffDepth |
| Line buffer Depth set. More... | |
| u32 | IsEmbNonImgPresent |
| Flag for presence of Embedded Non Image data. More... | |
| u32 | IsDphyRegIntfcPresent |
| Flag for DPHY register interface presence. More... | |
| u32 | DphyLineRate |
| DPHY Line Rate ranging from 80-1500 Mbps. More... | |
| u32 | EnableCrc |
| CRC Calculation optimization enabled. More... | |
| u32 | EnableActiveLanes |
| Active Lanes programming optimization enabled. More... | |
| u8 | EnableCSIv20 |
| CSI v2.0 support enabled. More... | |
| u8 | EnableVCx |
| VCx feature support enabled. More... | |
| CsiRxSsSubCore | CsiInfo |
| CSI sub-core configuration. More... | |
| CsiRxSsSubCore | DphyInfo |
| DPHY sub-core configuration. More... | |
| CsiRxSsSubCore | MipiRxPhyInfo |
| MIPI RX PHY sub-core configuration. More... | |
| u16 | IntrId |
| Interrupt ID. More... | |
| UINTPTR | IntrParent |
| Bit[0] Interrupt Parent. More... | |
MIPI CSI Rx Subsystem configuration structure.
This structure contains the configuration information for the MIPI CSI Rx Subsystem. Each subsystem device should have a configuration structure associated that defines the MAX supported sub-cores within subsystem.
| UINTPTR XCsiSs_Config::BaseAddr |
BaseAddress is the physical base address
of the subsystem address range
Referenced by CsiSs_IntrExample(), CsiSs_SelfTestExample(), InitializeCsiRxSs(), and XCsiSs_CfgInitialize().
| u32 XCsiSs_Config::CsiBuffDepth |
Line buffer Depth set.
| CsiRxSsSubCore XCsiSs_Config::CsiInfo |
CSI sub-core configuration.
| CsiRxSsSubCore XCsiSs_Config::DphyInfo |
DPHY sub-core configuration.
| u32 XCsiSs_Config::DphyLineRate |
DPHY Line Rate ranging from 80-1500 Mbps.
| u32 XCsiSs_Config::EnableActiveLanes |
Active Lanes programming optimization enabled.
| u32 XCsiSs_Config::EnableCrc |
CRC Calculation optimization enabled.
| u8 XCsiSs_Config::EnableCSIv20 |
CSI v2.0 support enabled.
| u8 XCsiSs_Config::EnableVCx |
VCx feature support enabled.
Referenced by XCsiSs_GetVCInfo(), XCsiSs_GetVCSelection(), and XCsiSs_SetVCSelection().
| UINTPTR XCsiSs_Config::HighAddr |
HighAddress is the physical MAX address
of the subsystem address range
| u16 XCsiSs_Config::IntrId |
Interrupt ID.
Referenced by CsiSs_IntrExample(), and main().
| UINTPTR XCsiSs_Config::IntrParent |
Bit[0] Interrupt Parent.
Referenced by CsiSs_IntrExample(), and main().
| u32 XCsiSs_Config::IsDphyRegIntfcPresent |
Flag for DPHY register interface presence.
Referenced by XCsiSs_Activate(), XCsiSs_CfgInitialize(), and XCsiSs_ReportCoreInfo().
| u32 XCsiSs_Config::IsEmbNonImgPresent |
Flag for presence of Embedded Non Image data.
| u32 XCsiSs_Config::LanesPresent |
Number of PPI Lanes in the design.
Referenced by XCsiSs_GetLaneInfo().
| CsiRxSsSubCore XCsiSs_Config::MipiRxPhyInfo |
MIPI RX PHY sub-core configuration.
| u32 XCsiSs_Config::PixelCount |
Number of Pixels per clock 1,2,4.
| u32 XCsiSs_Config::PixelFormat |
The pixel format selected from all RGB, RAW and YUV422 8bit options.
Referenced by SetColorDepth().
| u32 XCsiSs_Config::VcNo |
Number of Virtual Channels supported by system.
This can range from 1 - 4 to ALL
Referenced by XCsiSs_GetVCSelection(), and XCsiSs_SetVCSelection().
