Data Structures
struct	XNandPs_Config
	This typedef contains configuration information for the flash device. More...

struct	XNandPs_Geometry
	Flash geometry. More...

struct	XNandPs_Features
	ONFI Features and Optional commands supported See parameter page byte 6-7 and 8-9. More...

struct	XNandPs_BbtDesc
	Bad block table descriptor. More...

struct	XNandPs_BadBlockPattern
	Bad block pattern. More...

struct	XNandPs_EccConfig
	ECC configuration structure. More...

struct	XNandPsTag
	The XNandPs driver instance data. More...

struct	XNandPs_CommandFormat
	NAND Command format structures. More...

struct	__attribute__
	ONFI 1.0 support. More...

Macros
#define	XNANDPS_MAX_TARGETS 1
	Max number of targets supported. More...

#define	XNANDPS_MAX_BLOCKS 32768
	Max number of Blocks. More...

#define	XNANDPS_MAX_PAGE_SIZE 16384
	Max page size of NAND flash. More...

#define	XNANDPS_MAX_SPARE_SIZE 512
	Max spare bytes of a NAND flash page. More...

#define	XNANDPS_MAX_LUNS 8
	Max number of LUNs. More...

#define	XNANDPS_MAX_PAGES_PER_BLOCK 512
	Max number pages per block. More...

#define	XNANDPS_ECC_BLOCK_SIZE 512
	ECC block size. More...

#define	XNANDPS_ECC_BYTES 3
	ECC bytes per ECC block. More...

#define	XNANDPS_PAGE_SIZE_512 512
	Page size 512. More...

#define	XNANDPS_PAGE_SIZE_1024 1024
	Page size 1024. More...

#define	XNANDPS_PAGE_SIZE_2048 2048
	Page size 2048. More...

#define	XNANDPS_PAGE_SIZE_4096 4096
	Page size 4096. More...

#define	XNANDPS_PAGE_SIZE_8192 8192
	Page size 8192. More...

#define	XNANDPS_SPARE_SIZE_8 8
	Spare bytes size 8. More...

#define	XNANDPS_SPARE_SIZE_16 16
	Spare bytes size 16. More...

#define	XNANDPS_SPARE_SIZE_32 32
	Spare bytes size 32. More...

#define	XNANDPS_SPARE_SIZE_64 64
	Spare bytes size 64. More...

#define	XNANDPS_SPARE_SIZE_128 128
	Spare bytes size 128. More...

#define	XNANDPS_SPARE_SIZE_256 256
	Spare bytes size 256. More...

#define	XNANDPS_FLASH_WIDTH_8 8
	NAND Flash width 8-bit. More...

#define	XNANDPS_FLASH_WIDTH_16 16
	NAND Flash width 16-bit. More...

#define	XNANDPS_END_CMD_NONE 0
	No End command. More...

#define	XNANDPS_END_CMD_INVALID 0
	End command invalid. More...

#define	XNANDPS_CMD_PHASE 1
	End command in command phase. More...

#define	XNANDPS_DATA_PHASE 2
	End command in data phase. More...

#define	XNANDPS_PAGE_NOT_VALID -1
	Page is not valid in command phase. More...

#define	XNANDPS_COLUMN_NOT_VALID -1
	Column is not valid in command phase. More...

#define	XNANDPS_AXI_DATA_WIDTH 4
	AXI Data width for last transaction while reading and writing. More...

#define	XNANDPS_START_CMD_SHIFT 3
	Start command shift. More...

#define	XNANDPS_END_CMD_SHIFT 11
	End command shift. More...

#define	XNANDPS_END_CMD_VALID_SHIFT 20
	End command valid shift. More...

#define	XNANDPS_ADDR_CYCLES_SHIFT 21
	Address cycles shift. More...

#define	XNANDPS_CHIP_ADDR_SHIFT 24
	Chip address shift. More...

#define	XNANDPS_ECC_LAST_SHIFT 10
	Ecc last shift. More...

#define	XNANDPS_CLEAR_CS_SHIFT 21
	clear chip select shift More...

#define	XNANDPS_COMMAND_PHASE_MASK 0x00000000
	Command phase mask. More...

#define	XNANDPS_DATA_PHASE_MASK 0x00080000
	Data phase mask. More...

#define	XNANDPS_ECC_CORRECT_BYTE_MASK 0x1FF
	ECC error correction byte position mask, bits[11:3] of error code. More...

#define	XNANDPS_ECC_CORRECT_BIT_MASK 0x7
	ECC error correction bit position mask, bits[0:2] of error code. More...

#define	XNANDPS_CLR_CONFIG
	Interrupt settings. More...

#define	XNANDPS_ECC_MEMCFG
	ECC memory configuration settings. More...

#define	XNANDPS_ECC_CMD1
	ECC command 1 settings. More...

#define	XNANDPS_ECC_CMD2
	ECC command 2 settings. More...

#define	XNANDPS_CLR_CS (0x1 << XNANDPS_CLEAR_CS_SHIFT)
	set Clear chip select More...

#define	XNANDPS_ECC_LAST (0x1 << XNANDPS_ECC_LAST_SHIFT)
	set Ecc last More...

#define	OneHot(Value) (!((Value) & (Value - 1)))
	OneHot is used to check if one and only one bit is set. More...

#define	XNANDPS_BLOCK_GOOD 0x0
	Block is good. More...

#define	XNANDPS_BLOCK_BAD 0x1
	Block is bad. More...

#define	XNANDPS_BLOCK_RESERVED 0x2
	Reserved block. More...

#define	XNANDPS_BLOCK_FACTORY_BAD 0x3
	Factory marked bad block. More...

#define	XNANDPS_FLASH_BLOCK_GOOD 0x3
	Block is good. More...

#define	XNANDPS_FLASH_BLOCK_BAD 0x2
	Block is bad. More...

#define	XNANDPS_FLASH_BLOCK_RESERVED 0x1
	Reserved block. More...

#define	XNANDPS_FLASH_BLOCK_FACTORY_BAD 0x0
	Factory marked bad block. More...

#define	XNANDPS_BBT_SCAN_2ND_PAGE 0x00000001
	Scan the second page for bad block information. More...

#define	XNANDPS_BBT_DESC_PAGE_OFFSET 0
	Page offset of Bad Block Table Desc. More...

#define	XNANDPS_BBT_DESC_SIG_OFFSET 8
	Bad Block Table signature offset. More...

#define	XNANDPS_BBT_DESC_VER_OFFSET 12
	Bad block Table version offset. More...

#define	XNANDPS_BBT_DESC_SIG_LEN 4
	Bad block Table signature length. More...

#define	XNANDPS_BBT_DESC_MAX_BLOCKS 4
	Bad block Table max blocks. More...

#define	XNANDPS_BBT_BLOCK_SHIFT 2
	Block shift value for a block in BBT. More...

#define	XNANDPS_BBT_ENTRY_NUM_BLOCKS 4
	Num of blocks in one BBT entry. More...

#define	XNANDPS_BB_PATTERN_OFFSET_SMALL_PAGE 5
	Bad block pattern offset in a page. More...

#define	XNANDPS_BB_PATTERN_LENGTH_SMALL_PAGE 1
	Bad block pattern length. More...

#define	XNANDPS_BB_PATTERN_OFFSET_LARGE_PAGE 0
	Bad block pattern offset in a large page. More...

#define	XNANDPS_BB_PATTERN_LENGTH_LARGE_PAGE 2
	Bad block pattern length. More...

#define	XNANDPS_BB_PATTERN 0xFF
	Bad block pattern to search in a page. More...

#define	XNANDPS_BLOCK_TYPE_MASK 0x03
	Block type mask. More...

#define	XNANDPS_BLOCK_SHIFT_MASK 0x06
	Block shift mask for a Bad Block Table entry byte. More...

#define	XNandPs_BbtBlockShift(Block) ((Block * 2) & XNANDPS_BLOCK_SHIFT_MASK)
	This macro returns the Block shift value corresponding to a Block. More...

#define	XNANDPS_MEMC_STATUS_OFFSET 0x000
	Controller status reg, RO. More...

#define	XNANDPS_MEMC_IF_CONFIG_OFFSET 0x004
	Interface config reg, RO. More...

#define	XNANDPS_MEMC_SET_CONFIG_OFFSET 0x008
	Set configuration reg, WO. More...

#define	XNANDPS_MEMC_CLR_CONFIG_OFFSET 0x00C
	Clear config reg, WO. More...

#define	XNANDPS_DIRECT_CMD_OFFSET 0x010
	Direct command reg, WO. More...

#define	XNANDPS_SET_CYCLES_OFFSET 0x014
	Set cycles register, WO. More...

#define	XNANDPS_SET_OPMODE_OFFSET 0x018
	Set opmode register, WO. More...

#define	XNANDPS_REFRESH_PERIOD_0_OFFSET 0x020
	Refresh period_0 reg, RW. More...

#define	XNANDPS_REFRESH_PERIOD_1_OFFSET 0x024
	Refresh period_1 reg, RW. More...

#define	XNANDPS_IF0_CHIP_0_CONFIG_OFFSET 0x100
	Interface 0 chip 0 config. More...

#define	XNANDPS_IF0_CHIP_1_CONFIG_OFFSET 0x120
	Interface 0 chip 1 config. More...

#define	XNANDPS_IF0_CHIP_2_CONFIG_OFFSET 0x140
	Interface 0 chip 2 config. More...

#define	XNANDPS_IF0_CHIP_3_CONFIG_OFFSET 0x160
	Interface 0 chip 3 config. More...

#define	XNANDPS_IF1_CHIP_0_CONFIG_OFFSET 0x180
	Interface 1 chip 0 config. More...

#define	XNANDPS_IF1_CHIP_1_CONFIG_OFFSET 0x1A0
	Interface 1 chip 1 config. More...

#define	XNANDPS_IF1_CHIP_2_CONFIG_OFFSET 0x1C0
	Interface 1 chip 2 config. More...

#define	XNANDPS_IF1_CHIP_3_CONFIG_OFFSET 0x1E0
	Interface 1 chip 3 config. More...

#define	XNANDPS_FLASH_CYCLES(addr) (0x000 + addr)
	NAND & SRAM cycle,RO. More...

#define	XNANDPS_OPMODE(addr) (0x004 + addr)
	Chip opmode reg, RO. More...

#define	XNANDPS_USER_STATUS_OFFSET 0x200
	User status reg, RO. More...

#define	XNANDPS_USER_CONFIG_OFFSET 0x204
	User config reg, WO. More...

#define	XNANDPS_IF0_ECC_OFFSET 0x300
	Interface 0 ECC register. More...

#define	XNANDPS_IF1_ECC_OFFSET 0x400
	Interface 1 ECC register. More...

#define	XNANDPS_ECC_STATUS_OFFSET(addr) (0x000 + addr)
	ECC status register. More...

#define	XNANDPS_ECC_MEMCFG_OFFSET(addr) (0x004 + addr)
	ECC mem config reg. More...

#define	XNANDPS_ECC_MEMCMD1_OFFSET(addr) (0x008 + addr)
	ECC mem com1 reg. More...

#define	XNANDPS_ECC_MEMCMD2_OFFSET(addr) (0x00C + addr)
	ECC mem com2 reg. More...

#define	XNANDPS_ECC_ADDR0_OFFSET(addr) (0x010 + addr)
	ECC address0 reg. More...

#define	XNANDPS_ECC_ADDR1_OFFSET(addr) (0x014 + addr)
	ECC address1 reg. More...

#define	XNANDPS_ECC_VALUE0_OFFSET(addr) (0x018 + addr)
	ECC value 0 reg. More...

#define	XNANDPS_ECC_VALUE1_OFFSET(addr) (0x01C + addr)
	ECC value 1 reg. More...

#define	XNANDPS_ECC_VALUE2_OFFSET(addr) (0x020 + addr)
	ECC value 2 reg. More...

#define	XNANDPS_ECC_VALUE3_OFFSET(addr) (0x024 + addr)
	ECC value 3 reg. More...

#define	XNANDPS_ECC_VALUE4_OFFSET(addr) (0x028 + addr)
	ECC value 4 reg. More...

#define	XNANDPS_INTGTEST_OFFSET 0xE00
	Integration test offset. More...

#define	XNANDPS_PERIPH_ID0_OFFSET 0xFE0
	Peripheral id0 register. More...

#define	XNANDPS_PERIPH_ID1_OFFSET 0xFE4
	Peripheral id1 register. More...

#define	XNANDPS_PERIPH_ID2_OFFSET 0xFE8
	Peripheral id2 register. More...

#define	XNANDPS_PERIPH_ID3_OFFSET 0xFEC
	Peripheral id3 register. More...

#define	XNANDPS_PCELL_ID0_OFFSET 0xFF0
	Primecell id0 register. More...

#define	XNANDPS_PCELL_ID1_OFFSET 0xFF4
	Primecell id1 register. More...

#define	XNANDPS_PCELL_ID2_OFFSET 0xFF8
	Primecell id2 register. More...

#define	XNANDPS_PCELL_ID3_OFFSET 0xFFC
	Primecell id3 register. More...

#define	ONFI_CMD_READ1 0x00
	ONFI Read command (1st cycle) More...

#define	ONFI_CMD_READ2 0x30
	ONFI Read command (2nd cycle) More...

#define	ONFI_CMD_CHANGE_READ_COLUMN1 0x05
	ONFI Change Read Column command (1st cycle) More...

#define	ONFI_CMD_CHANGE_READ_COLUMN2 0xE0
	ONFI Change Read Column command (2nd cycle) More...

#define	ONFI_CMD_BLOCK_ERASE1 0x60
	ONFI Block Erase (1st cycle) More...

#define	ONFI_CMD_BLOCK_ERASE2 0xD0
	ONFI Block Erase (2nd cycle) More...

#define	ONFI_CMD_READ_STATUS 0x70
	ONFI Read status command. More...

#define	ONFI_CMD_PAGE_PROG1 0x80
	ONFI Page Program command (1st cycle) More...

#define	ONFI_CMD_PAGE_PROG2 0x10
	ONFI Page Program command (2nd cycle) More...

#define	ONFI_CMD_CHANGE_WRITE_COLUMN 0x85
	ONFI Change Write Column command. More...

#define	ONFI_CMD_READ_ID 0x90
	ONFI Read ID command. More...

#define	ONFI_CMD_READ_PARAM_PAGE 0xEC
	ONFI Read Parameter Page command. More...

#define	ONFI_CMD_RESET 0xFF
	ONFI Reset command. More...

#define	ONFI_CMD_COPYBACK_READ1 0x00
	ONFI Copyback Read command (1st cycle) More...

#define	ONFI_CMD_COPYBACK_READ2 0x35
	ONFI Copyback Read command (2nd cycle) More...

#define	ONFI_CMD_READ_CACHE_ENHANCED1 0x00
	ONFI Read cache enhanced command (1st cycle) More...

#define	ONFI_CMD_READ_CACHE_ENHANCED2 0x31
	ONFI Read cache enhanced command (2nd cycle) More...

#define	ONFI_CMD_READ_CACHE 0x31
	ONFI Read cache command. More...

#define	ONFI_CMD_READ_CACHE_END 0x3F
	ONFI Read cache end command. More...

#define	ONFI_CMD_BLOCK_ERASE_INTERLEAVED2 0xD1
	ONFI Block Erase interleaved command (2nd cycle) More...

#define	ONFI_CMD_READ_STATUS_ENHANCED 0x78
	ONFI Read Status enhanced command. More...

#define	ONFI_CMD_PAGE_PROGRAM_INTERLEAVED2 0x11
	ONFI Page Program interleaved command (2nd cycle) More...

#define	ONFI_CMD_PAGE_CACHE_PROGRAM1 0x80
	ONFI Page cache program (1st cycle) More...

#define	ONFI_CMD_PAGE_CACHE_PROGRAM2 0x15
	ONFI Page cache program (2nd cycle) More...

#define	ONFI_CMD_COPYBACK_PROGRAM1 0x85
	ONFI Copyback program command (1st cycle) More...

#define	ONFI_CMD_COPYBACK_PROGRAM2 0x10
	ONFI Copyback program command (2nd cycle) More...

#define	ONFI_CMD_COPYBACK_PROGRAM_INTERLEAVED2 0x11
	ONFI Copyback program interleaved command (2nd cycle) More...

#define	ONFI_CMD_READ_UNIQUEID 0xED
	ONFI Read Unique ID command. More...

#define	ONFI_CMD_GET_FEATURES 0xEE
	ONFI Get features command. More...

#define	ONFI_CMD_SET_FEATURES 0xEF
	ONFI Set features command. More...

#define	ONFI_STATUS_FAIL 0x01
	ONFI Status Register : FAIL. More...

#define	ONFI_STATUS_FAILC 0x02
	ONFI Status Register : FAILC. More...

#define	ONFI_STATUS_ARDY 0x20
	ONFI Status Register : ARDY. More...

#define	ONFI_STATUS_RDY 0x40
	ONFI Status Register : RDY. More...

#define	ONFI_STATUS_WP 0x80
	ONFI Status Register : WR. More...

#define	ONFI_ID_LEN 4
	ONFI ID Length. More...

#define	ONFI_CRC_INIT 0x4F4E
	ONFI CRC16 Inititialization constant. More...

#define	ONFI_CRC_POLYNOM 0x8005
	ONFI CRC16 polynomial. More...

#define	ONFI_CRC_ORDER 16
	ONFI CRC16 order. More...

#define	ONFI_PARAM_PAGE_LEN 256
	ONFI Parameter page length. More...

#define	ONFI_CRC_LEN 254
	ONFI CRC16 length. More...

#define	ONFI_SIGNATURE_LEN 4
	ONFI Signature Length. More...

Typedefs
typedef struct XNandPsTag	XNandPs
	The XNandPs driver instance data. More...

Enumerations
enum	XNandPs_EccMode { XNANDPS_ECC_NONE = 0, XNANDPS_ECC_SW, XNANDPS_ECC_HW, XNANDPS_ECC_ONDIE }

enum	OnfiCommandsEnum { READ = 0, CHANGE_READ_COLUMN, BLOCK_ERASE, READ_STATUS, PAGE_PROGRAM, CHANGE_WRITE_COLUMN, READ_ID, READ_PARAM_PAGE, RESET, GET_FEATURES, SET_FEATURES, READ_CACHE_RANDOM, READ_CACHE_END_SEQ, PAGE_CACHE_PROGRAM }
	This enum defines the onfi commands. More...

Functions
void	XNandPs_SendCommand (XNandPs InstancePtr, XNandPs_CommandFormat Command, int Page, int Column)
	This function sends a NAND command to the flash device. More...

void	XNandPs_InitBbtDesc (XNandPs *InstancePtr)
	This function initializes the Bad Block Table(BBT) descriptors with a predefined pattern for searching Bad Block Table(BBT) in flash. More...

int	XNandPs_ScanBbt (XNandPs *InstancePtr)
	This function reads the Bad Block Table(BBT) if present in flash. More...

u8	Onfi_CmdReadStatus (XNandPs *InstancePtr)
	This function sends read status command to the flash device. More...

int	Onfi_NandInit (XNandPs *InstancePtr)
	This function initializes the NAND flash and gets the geometry information. More...

int	XNandPs_CfgInitialize (XNandPs InstancePtr, XNandPs_Config ConfigPtr, u32 SmcBaseAddr, u32 FlashBaseAddr)
	This function initializes a specific XNandPs device/instance. More...

int	XNandPs_Read (XNandPs InstancePtr, u64 Offset, u32 Length, void DestPtr, u8 *UserSparePtr)
	This function reads the data from the Flash device and copies it into the specified user buffer. More...

int	XNandPs_ReadCache (XNandPs InstancePtr, u64 Offset, u32 Length, void DestPtr, u8 *UserSparePtr)
	This function reads the data from the Flash device using read page cache command and copies it into the specified user buffer. More...

int	XNandPs_Write (XNandPs InstancePtr, u64 Offset, u32 Length, void SrcPtr, u8 *UserSparePtr)
	This function programs the flash device(s) with data specified in the user buffer. More...

int	XNandPs_WriteCache (XNandPs InstancePtr, u64 Offset, u32 Length, void SrcPtr, u8 *UserSparePtr)
	This function programs the flash device(s) with data specified in the user buffer using program cache command. More...

int	XNandPs_ReadSpareBytes (XNandPs InstancePtr, u32 Page, u8 Buf)
	This function reads the spare area of a page. More...

int	XNandPs_WriteSpareBytes (XNandPs InstancePtr, u32 Page, u8 Buf)
	This function write to the spare area of a page. More...

int	XNandPs_EraseBlock (XNandPs *InstancePtr, u32 BlockNum)
	This function erases a specific block in the NAND device. More...

XNandPs_Config *	XNandPs_LookupConfig (u16 DeviceId)
	This function looks up the device configuration based on the unique device ID. More...

int	XNandPs_IsBlockBad (XNandPs *InstancePtr, u32 Block)
	This function checks whether a block is bad or not. More...

int	XNandPs_MarkBlockBad (XNandPs *InstancePtr, u32 Block)
	This function marks a block as bad in the RAM based Bad Block Table(BBT). More...

Variables
u32	NandOob16 [] = {13, 14, 15}
	Ecc position for 16 bytes spare area. More...

u32	NandOob32 [] = {26, 27, 28, 29, 30, 31}
	Ecc position for 32 bytes spare area. More...

u32	NandOob64 []
	Ecc position for 64 bytes spare area. More...

XNandPs_CommandFormat	OnfiCommands []
	ONFI commands. More...

XNandPs_Config	XNandPs_ConfigTable [XPAR_XNANDPS_NUM_INSTANCES]
	This table contains configuration information for each System Monitor/ADC device in the system. More...

XNandPs_CommandFormat	OnfiCommands []
	This structure defines the onfi command format sent to the flash. More...

XNandPs_Config	XNandPs_ConfigTable []
	This table contains configuration information for each System Monitor/ADC device in the system. More...

Memory controller status register bit definitions and masks
#define	XNANDPS_MEMC_STATUS_STATE_MASK 0x00000001
	Memory controller operating state mask. More...

#define	XNANDPS_MEMC_STATUS_INT_EN0_MASK 0x00000002
	Memory controller interface 0 interrupt enable mask. More...

#define	XNANDPS_MEMC_STATUS_INT_EN1_MASK 0x00000004
	Memory controller interface 1 interrupt enable mask. More...

#define	XNANDPS_MEMC_STATUS_INT_STATUS0_MASK 0x00000008
	Memory controller interface 0 interrupt status mask. More...

#define	XNANDPS_MEMC_STATUS_INT_STATUS1_MASK 0x00000010
	Memory controller interface 1 interrupt status mask. More...

#define	XNANDPS_MEMC_STATUS_RAW_INT_STATUS0_MASK 0x00000020
	Memory controller interface 0 raw interrupt status mask. More...

#define	XNANDPS_MEMC_STATUS_RAW_INT_STATUS1_MASK 0x00000040
	Memory controller interface 1 raw interrupt status mask. More...

#define	XNANDPS_MEMC_STATUS_ECC_INT_EN0_MASK 0x00000080
	Memory controller interface 0 ECC interrupt enable mask. More...

#define	XNANDPS_MEMC_STATUS_ECC_INT_EN1_MASK 0x00000100
	Memory controller interface 1 ECC interrupt enable mask. More...

#define	XNANDPS_MEMC_STATUS_ECC_INT0_MASK 0x00000200
	Memory controller interface 0 ECC interrupt status mask. More...

#define	XNANDPS_MEMC_STATUS_ECC_INT1_MASK 0x00000400
	Memory controller interface 1 ECC interrupt status mask. More...

#define	XNANDPS_MEMC_STATUS_RAW_ECC_INT0_MASK 0x00000800
	Memory controller interface 0 raw ECC interrupt status mask. More...

#define	XNANDPS_MEMC_STATUS_RAW_ECC_INT1_MASK 0x00001000
	Memory controller interface 1 raw ECC interrupt status mask. More...

Memory interface configurartion register bit definitions and masks
#define	XNANDPS_MEMC_IF_CONFIG_MEMORY_TYPE0_MASK 0x00000003
	Memory controller interface 0 type mask. More...

#define	XNANDPS_MEMC_IF_CONFIG_MEMORY_CHIPS0_MASK 0x0000000C
	Memory controller interface 0 chip select mask. More...

#define	XNANDPS_MEMC_IF_CONFIG_MEMORY_WIDTH0_MASK 0x00000030
	Memory controller interface 0 data width mask. More...

#define	XNANDPS_MEMC_IF_CONFIG_REMAP0_MASK 0x00000040
	Memory controller interface 0 remap0 mask. More...

#define	XNANDPS_MEMC_IF_CONFIG_MEMORY_TYPE1_MASK 0x00000300
	Memory controller interface 1 type mask. More...

#define	XNANDPS_MEMC_IF_CONFIG_MEMORY_CHIPS1_MASK 0x00000C00
	Memory controller interface 1 chip select mask. More...

#define	XNANDPS_MEMC_IF_CONFIG_MEMORY_WIDTH1_MASK 0x00003000
	Memory controller interface 1 data width mask. More...

#define	XNANDPS_MEMC_IF_CONFIG_REMAP1_MASK 0x00004000
	Memory controller interface 1 remap0 mask. More...

#define	XNANDPS_MEMC_IF_CONFIG_EX_MONITORS_MASK 0x00030000
	Memory controller interface exclusive masks mask. More...

Set configuration register bit definitions and masks
#define	XNANDPS_MEMC_SET_CONFIG_INT_ENABLE0_MASK 0x00000001
	Memory controller interfce0 interrupt enable mask. More...

#define	XNANDPS_MEMC_SET_CONFIG_INT_ENABLE1_MASK 0x00000002
	Memory controller interfce1 interrupt enable mask. More...

#define	XNANDPS_MEMC_SET_CONFIG_LOW_POWER_REQ_MASK 0x00000004
	Memory controller low power state mask. More...

#define	XNANDPS_MEMC_SET_CONFIG_ECC_INT_ENABLE0_MASK 0x00000020
	Memory controller interfce0 ECC interrupt enable mask. More...

#define	XNANDPS_MEMC_SET_CONFIG_ECC_INT_ENABLE1_MASK 0x00000040
	Memory controller interfce1 ECC interrupt enable mask. More...

Clear configuration register bit definitions and masks
#define	XNANDPS_MEMC_CLR_CONFIG_INT_DISABLE0_MASK 0x00000001
	Memory controller interface 0 interrupt disable mask. More...

#define	XNANDPS_MEMC_CLR_CONFIG_INT_DISABLE1_MASK 0x00000002
	Memory controller interface 1 interrupt disable mask. More...

#define	XNANDPS_MEMC_CLR_CONFIG_LOW_POWER_EXIT_MASK 0x00000004
	Memory controller low power exit mask. More...

#define	XNANDPS_MEMC_CLR_CONFIG_INT_CLR0_MASK 0x00000008
	Memory controller interface0 interrupt clear mask. More...

#define	XNANDPS_MEMC_CLR_CONFIG_INT_CLR1_MASK 0x00000010
	Memory controller interface1 interrupt clear mask. More...

#define	XNANDPS_MEMC_CLR_CONFIG_ECC_INT_DISABLE0_MASK 0x00000020
	Memory controller interface0 ECC interrupt disable mask. More...

#define	XNANDPS_MEMC_CLR_CONFIG_ECC_INT_DISABLE1_MASK 0x00000040
	Memory controller interface1 ECC interrupt disable mask. More...

Clear configuration register bit definitions and masks and shift
#define	XNANDPS_DIRECT_CMD_ADDR_MASK 0x000FFFFF
	Direct command address mask. More...

#define	XNANDPS_DIRECT_CMD_SET_CRE_MASK 0x00100000
	Direct command set cre mask. More...

#define	XNANDPS_DIRECT_CMD_TYPE_MASK 0x00600000
	Direct command type mask. More...

#define	XNANDPS_DIRECT_CMD_CHIP_SELECT_MASK 0x03800000
	Direct command chip select mask. More...

#define	XNANDPS_DIRECT_CMD_SET_CRE_SHIFT 20
	Direct command set_cre shift. More...

#define	XNANDPS_DIRECT_CMD_CMD_TYPE_SHIFT 21
	Direct command cmd_type shift. More...

#define	XNANDPS_DIRECT_CMD_CHIP_SELECT_SHIFT 23
	Direct command chip select shift. More...

Set cycles register bit definitions and masks and shift
#define	XNANDPS_SET_CYCLES_SET_T0_MASK 0x0000000F
	Set cycles set_t0 mask. More...

#define	XNANDPS_SET_CYCLES_SET_T1_MASK 0x000000F0
	Set cycles set_t1 mask. More...

#define	XNANDPS_SET_CYCLES_SET_T2_MASK 0x00000700
	Set cycles set_t2 mask. More...

#define	XNANDPS_SET_CYCLES_SET_T3_MASK 0x00003800
	Set cycles set_t3 mask. More...

#define	XNANDPS_SET_CYCLES_SET_T4_MASK 0x0001C000
	Set cycles set_t4 mask. More...

#define	XNANDPS_SET_CYCLES_SET_T5_MASK 0x000E0000
	Set cycles set_t5 mask. More...

#define	XNANDPS_SET_CYCLES_SET_T6_MASK 0x00F00000
	Set cycles set_t6 mask. More...

#define	XNANDPS_SET_CYCLES_SET_T0_SHIFT 0
	Set cycles set_t0 shift. More...

#define	XNANDPS_SET_CYCLES_SET_T1_SHIFT 4
	Set cycles set_t1 shift. More...

#define	XNANDPS_SET_CYCLES_SET_T2_SHIFT 8
	Set cycles set_t2 shift. More...

#define	XNANDPS_SET_CYCLES_SET_T3_SHIFT 11
	Set cycles set_t3 shift. More...

#define	XNANDPS_SET_CYCLES_SET_T4_SHIFT 14
	Set cycles set_t4 shift. More...

#define	XNANDPS_SET_CYCLES_SET_T5_SHIFT 17
	Set cycles set_t5 shift. More...

#define	XNANDPS_SET_CYCLES_SET_T6_SHIFT 20
	Set cycles set_t6 shift. More...

Set opmode register bit definitions and masks
#define	XNANDPS_SET_OPMODE_SET_MW_MASK 0x00000003
	Set opmode set memory width mask. More...

#define	XNANDPS_SET_OPMODE_SET_RD_SYNC_MASK 0x00000004
	Set opmode set rd_sync mask. More...

#define	XNANDPS_SET_OPMODE_SET_RD_BL_MASK 0x00000038
	Set opmode set rd_bl mask. More...

#define	XNANDPS_SET_OPMODE_SET_WR_SYNC_MASK 0x00000040
	Set opmode set wr_sync mask. More...

#define	XNANDPS_SET_OPMODE_SET_WR_BL_MASK 0x00000380
	Set opmode set wr_bl mask. More...

#define	XNANDPS_SET_OPMODE_SET_BAA_MASK 0x00000400
	Set opmode set baa mask. More...

#define	XNANDPS_SET_OPMODE_SET_ADV_MASK 0x00000800
	Set opmode set adv mask. More...

#define	XNANDPS_SET_OPMODE_SET_BLS_MASK 0x00001000
	Set opmode set bls mask. More...

#define	XNANDPS_SET_OPMODE_SET_BURST_ALIGN_MASK 0x0000E000
	Set opmode set burst align mask. More...

#define	XNANDPS_SET_OPMODE_MW_8_BITS 0x0
	Set opmode memory width value for 8-bit flash. More...

#define	XNANDPS_SET_OPMODE_MW_16_BITS 0x1
	Set opmode memory width value for 16-bit flash. More...

#define	XNANDPS_SET_OPMODE_MW_32_BITS 0x2
	Set opmode memory width value for 32-bit flash. More...

Refresh period register bit definitions and masks
#define	XNANDPS_REFRESH_PERIOD_0_MASK 0x0000000F
	Interface 0 refresh period mask. More...

#define	XNANDPS_REFRESH_PERIOD_1_MASK 0x0000000F
	Interface 1 refresh period mask. More...

Opmode register bit definitions and masks
#define	XNANDPS_OPMODE_MW_MASK 0x00000003
	Opmode Memory width mask. More...

#define	XNANDPS_OPMODE_RD_SYNC_MASK 0x00000004
	Opmode rd_sync mask. More...

#define	XNANDPS_OPMODE_RD_BL_MASK 0x00000038
	Opmode rd_bl mask. More...

#define	XNANDPS_OPMODE_WR_SYNC_MASK 0x00000040
	Opmode wr_sync mask. More...

#define	XNANDPS_OPMODE_WR_BL_MASK 0x00000380
	Opmode BAA mask. More...

#define	XNANDPS_OPMODE_BAA_MASK 0x00000400
	Opmode ADV mask. More...

#define	XNANDPS_OPMODE_ADV_MASK 0x00000800
	Opmode BLS mask. More...

#define	XNANDPS_OPMODE_BLS_MASK 0x00001000
	Opmode Burst align mask. More...

#define	XNANDPS_OPMODE_BURST_ALIGN_MASK 0x0000E000
	Opmode Address mask. More...

#define	XNANDPS_OPMODE_ADDRESS_MASK 0x00FF0000
	Opmode Address match mask. More...

#define	XNANDPS_OPMODE_ADDRESS_MATCH_MASK 0xFF000000

User status register bit definitions and masks
#define	XNANDPS_USER_STATUS_MASK 0x000000FF
	User status mask. More...

User config register bit definitions and masks
#define	XNANDPS_USER_CONFIG_MASK 0x000000FF
	User config mask. More...

ECC status register bit definitions and masks
#define	XNANDPS_ECC_STATUS_RAW_INT_STATUS_MASK 0x0000003F
	Ecc status raw_int_status mask. More...

#define	XNANDPS_ECC_STATUS_MASK 0x00000040
	Ecc status ecc_status mask. More...

#define	XNANDPS_ECC_LAST_MASK 0x00000180
	Ecc status ecc_last mask. More...

#define	XNANDPS_ECC_READ_NOT_WRITE_MASK 0x00000200
	Ecc status ecc_read_not_write mask. More...

#define	XNANDPS_ECC_VALID_MASK 0x00007C00
	Ecc status ecc_valid mask. More...

#define	XNANDPS_ECC_FAIL_MASK 0x000F8000
	Ecc status ecc_fail mask. More...

#define	XNANDPS_ECC_CAN_CORRECT_MASK 0x01F00000
	Ecc status ecc_can_correct mask. More...

#define	XNANDPS_ECC_READ_MASK 0x37000000
	Ecc status ecc_read mask. More...

ECC mem config register bit definitions and masks and shifts
#define	XNANDPS_ECC_MEMCFG_PAGE_SIZE_MASK 0x00000003
	Ecc cfg page_size mask. More...

#define	XNANDPS_ECC_MEMCFG_ECC_MODE_MASK 0x0000000C
	Ecc cfg ecc_mode mask. More...

#define	XNANDPS_ECC_MEMCFG_ECC_READ_END_MASK 0x00000010
	Ecc cfg ecc_read_end mask. More...

#define	XNANDPS_ECC_MEMCFG_ECC_JUMP_MASK 0x00000060
	Ecc cfg ecc_jump mask. More...

#define	XNANDPS_ECC_MEMCFG_IGNORE_ADD8_MASK 0x00000080
	Ecc cfg ecc_ignore_add_eight mask. More...

#define	XNANDPS_ECC_MEMCFG_ECC_INT_PASS_MASK 0x00000100
	Ecc cfg ecc_int_pass mask. More...

#define	XNANDPS_ECC_MEMCFG_ECC_INT_ABORT_MASK 0x00000200
	Ecc cfg ecc_int_abort mask. More...

#define	XNANDPS_ECC_MEMCFG_ECC_EXTRA_BLOCK_MASK 0x00000400
	Ecc cfg ecc_extra_block mask. More...

#define	XNANDPS_ECC_MEMCFG_ECC_EXTRA_BLOCK_SIZE_MASK 0x00001800
	Ecc cfg ecc_extra_block_size mask. More...

#define	XNANDPS_ECC_MEMCFG_PAGE_SIZE_SHIFT 0
	Ecc cfg page_size shift. More...

#define	XNANDPS_ECC_MEMCFG_ECC_MODE_SHIFT 2
	Ecc cfg ecc_mode shift. More...

#define	XNANDPS_ECC_MEMCFG_ECC_READ_END_SHIFT 4
	Ecc cfg ecc_read_end shift. More...

#define	XNANDPS_ECC_MEMCFG_ECC_JUMP_SHIFT 5
	Ecc cfg ecc_jump shift. More...

#define	XNANDPS_ECC_MEMCFG_IGNORE_ADD8_SHIFT 7
	Ecc cfg ecc_ignore_add_eight shift. More...

#define	XNANDPS_ECC_MEMCFG_ECC_INT_PASS_SHIFT 8
	Ecc cfg ecc_int_pass shift. More...

#define	XNANDPS_ECC_MEMCFG_ECC_INT_ABORT_SHIFT 9
	Ecc cfg ecc_int_abort shift. More...

#define	XNANDPS_ECC_MEMCFG_ECC_EXTRA_BLOCK_SHIFT 10
	Ecc cfg ecc_extra_block shift. More...

#define	XNANDPS_ECC_MEMCFG_ECC_EXTRA_BLOCK_SIZE_SHIFT 11
	Ecc cfg ecc_extra_block_size shift. More...

#define	XNANDPS_ECC_MEMCFG_PAGE_SIZE_512 0x1
	ECC cfg page size value for 512 byte page. More...

#define	XNANDPS_ECC_MEMCFG_PAGE_SIZE_1024 0x2
	ECC cfg page size value for 1024 byte page. More...

#define	XNANDPS_ECC_MEMCFG_PAGE_SIZE_2048 0x3
	ECC cfg page size value for 2048 byte page. More...

Macro Definition Documentation

#define OneHot ( Value ) (!((Value) & (Value - 1)))

OneHot is used to check if one and only one bit is set.

This Macro returns 1 if the value passed is OneHot.

#define ONFI_CMD_BLOCK_ERASE1 0x60

ONFI Block Erase (1st cycle)

Referenced by XNandPs_SendCommand().

#define ONFI_CMD_BLOCK_ERASE2 0xD0

ONFI Block Erase (2nd cycle)

#define ONFI_CMD_BLOCK_ERASE_INTERLEAVED2 0xD1

ONFI Block Erase interleaved command (2nd cycle)

#define ONFI_CMD_CHANGE_READ_COLUMN1 0x05

ONFI Change Read Column command (1st cycle)

Referenced by XNandPs_ReadCache().

#define ONFI_CMD_CHANGE_READ_COLUMN2 0xE0

ONFI Change Read Column command (2nd cycle)

Referenced by XNandPs_ReadCache().

#define ONFI_CMD_CHANGE_WRITE_COLUMN 0x85

ONFI Change Write Column command.

#define ONFI_CMD_COPYBACK_PROGRAM1 0x85

ONFI Copyback program command (1st cycle)

#define ONFI_CMD_COPYBACK_PROGRAM2 0x10

ONFI Copyback program command (2nd cycle)

#define ONFI_CMD_COPYBACK_PROGRAM_INTERLEAVED2 0x11

ONFI Copyback program interleaved command (2nd cycle)

#define ONFI_CMD_COPYBACK_READ1 0x00

ONFI Copyback Read command (1st cycle)

#define ONFI_CMD_COPYBACK_READ2 0x35

ONFI Copyback Read command (2nd cycle)

#define ONFI_CMD_GET_FEATURES 0xEE

ONFI Get features command.

#define ONFI_CMD_PAGE_CACHE_PROGRAM1 0x80

ONFI Page cache program (1st cycle)

Referenced by XNandPs_ReadCache().

#define ONFI_CMD_PAGE_CACHE_PROGRAM2 0x15

ONFI Page cache program (2nd cycle)

#define ONFI_CMD_PAGE_PROG1 0x80

ONFI Page Program command (1st cycle)

Referenced by XNandPs_SendCommand().

#define ONFI_CMD_PAGE_PROG2 0x10

ONFI Page Program command (2nd cycle)

#define ONFI_CMD_PAGE_PROGRAM_INTERLEAVED2 0x11

ONFI Page Program interleaved command (2nd cycle)

#define ONFI_CMD_READ1 0x00

ONFI Read command (1st cycle)

Referenced by XNandPs_SendCommand().

#define ONFI_CMD_READ2 0x30

ONFI Read command (2nd cycle)

#define ONFI_CMD_READ_CACHE 0x31

ONFI Read cache command.

#define ONFI_CMD_READ_CACHE_END 0x3F

ONFI Read cache end command.

#define ONFI_CMD_READ_CACHE_ENHANCED1 0x00

ONFI Read cache enhanced command (1st cycle)

Referenced by XNandPs_ReadCache().

#define ONFI_CMD_READ_CACHE_ENHANCED2 0x31

ONFI Read cache enhanced command (2nd cycle)

Referenced by XNandPs_ReadCache().

#define ONFI_CMD_READ_ID 0x90

ONFI Read ID command.

#define ONFI_CMD_READ_PARAM_PAGE 0xEC

ONFI Read Parameter Page command.

#define ONFI_CMD_READ_STATUS 0x70

ONFI Read status command.

#define ONFI_CMD_READ_STATUS_ENHANCED 0x78

ONFI Read Status enhanced command.

#define ONFI_CMD_READ_UNIQUEID 0xED

ONFI Read Unique ID command.

#define ONFI_CMD_RESET 0xFF

ONFI Reset command.

#define ONFI_CMD_SET_FEATURES 0xEF

ONFI Set features command.

#define ONFI_CRC_INIT 0x4F4E

ONFI CRC16 Inititialization constant.

#define ONFI_CRC_LEN 254

ONFI CRC16 length.

#define ONFI_CRC_ORDER 16

ONFI CRC16 order.

#define ONFI_CRC_POLYNOM 0x8005

ONFI CRC16 polynomial.

#define ONFI_ID_LEN 4

ONFI ID Length.

Referenced by Onfi_NandInit().

#define ONFI_PARAM_PAGE_LEN 256

ONFI Parameter page length.

#define ONFI_SIGNATURE_LEN 4

ONFI Signature Length.

#define ONFI_STATUS_ARDY 0x20

ONFI Status Register : ARDY.

#define ONFI_STATUS_FAIL 0x01

ONFI Status Register : FAIL.

Referenced by XNandPs_ReadCache(), XNandPs_ReadSpareBytes(), and XNandPs_WriteSpareBytes().

#define ONFI_STATUS_FAILC 0x02

ONFI Status Register : FAILC.

#define ONFI_STATUS_RDY 0x40

ONFI Status Register : RDY.

#define ONFI_STATUS_WP 0x80

ONFI Status Register : WR.

Referenced by XNandPs_EraseBlock(), XNandPs_Write(), and XNandPs_WriteCache().

#define XNANDPS_ADDR_CYCLES_SHIFT 21

Address cycles shift.

Referenced by XNandPs_ReadSpareBytes(), and XNandPs_SendCommand().

#define XNANDPS_AXI_DATA_WIDTH 4

AXI Data width for last transaction while reading and writing.

Referenced by XNandPs_ReadSpareBytes(), and XNandPs_WriteSpareBytes().

#define XNANDPS_BB_PATTERN 0xFF

Bad block pattern to search in a page.

Referenced by XNandPs_InitBbtDesc().

#define XNANDPS_BB_PATTERN_LENGTH_LARGE_PAGE 2

Bad block pattern length.

Referenced by XNandPs_InitBbtDesc().

#define XNANDPS_BB_PATTERN_LENGTH_SMALL_PAGE 1

Bad block pattern length.

Referenced by XNandPs_InitBbtDesc().

#define XNANDPS_BB_PATTERN_OFFSET_LARGE_PAGE 0

Bad block pattern offset in a large page.

Referenced by XNandPs_InitBbtDesc().

#define XNANDPS_BB_PATTERN_OFFSET_SMALL_PAGE 5

Bad block pattern offset in a page.

Referenced by XNandPs_InitBbtDesc().

#define XNANDPS_BBT_BLOCK_SHIFT 2

Block shift value for a block in BBT.

Referenced by XNandPs_IsBlockBad(), and XNandPs_MarkBlockBad().

#define XNANDPS_BBT_DESC_MAX_BLOCKS 4

Bad block Table max blocks.

Referenced by XNandPs_InitBbtDesc().

#define XNANDPS_BBT_DESC_PAGE_OFFSET 0

Page offset of Bad Block Table Desc.

Referenced by XNandPs_InitBbtDesc().

#define XNANDPS_BBT_DESC_SIG_LEN 4

Bad block Table signature length.

Referenced by XNandPs_InitBbtDesc().

#define XNANDPS_BBT_DESC_SIG_OFFSET 8

Bad Block Table signature offset.

Referenced by XNandPs_InitBbtDesc().

#define XNANDPS_BBT_DESC_VER_OFFSET 12

Bad block Table version offset.

Referenced by XNandPs_InitBbtDesc().

#define XNANDPS_BBT_ENTRY_NUM_BLOCKS 4

Num of blocks in one BBT entry.

#define XNANDPS_BBT_SCAN_2ND_PAGE 0x00000001

Scan the second page for bad block information.

Referenced by XNandPs_InitBbtDesc().

#define XNandPs_BbtBlockShift ( Block ) ((Block * 2) & XNANDPS_BLOCK_SHIFT_MASK)

This macro returns the Block shift value corresponding to a Block.

Parameters

Block is the block number.

Returns: Block shift value

Note: None.

Referenced by XNandPs_IsBlockBad(), and XNandPs_MarkBlockBad().

#define XNANDPS_BLOCK_BAD 0x1

Block is bad.

Referenced by XNandPs_MarkBlockBad().

#define XNANDPS_BLOCK_FACTORY_BAD 0x3

Factory marked bad block.

#define XNANDPS_BLOCK_GOOD 0x0

Block is good.

Referenced by XNandPs_IsBlockBad().

#define XNANDPS_BLOCK_RESERVED 0x2

Reserved block.

#define XNANDPS_BLOCK_SHIFT_MASK 0x06

Block shift mask for a Bad Block Table entry byte.

#define XNANDPS_BLOCK_TYPE_MASK 0x03

Block type mask.

Referenced by XNandPs_IsBlockBad(), and XNandPs_MarkBlockBad().

#define XNANDPS_CHIP_ADDR_SHIFT 24

Chip address shift.

#define XNANDPS_CLEAR_CS_SHIFT 21

clear chip select shift

Referenced by XNandPs_SendCommand().

#define XNANDPS_CLR_CONFIG

Value:

((XNANDPS_MEMC_CLR_CONFIG_INT_DISABLE1_MASK)    | \
         (XNANDPS_MEMC_CLR_CONFIG_INT_CLR1_MASK)        | \
         (XNANDPS_MEMC_CLR_CONFIG_ECC_INT_DISABLE1_MASK))

Interrupt settings.

Referenced by XNandPs_CfgInitialize().

#define XNANDPS_CLR_CS (0x1 << XNANDPS_CLEAR_CS_SHIFT)

set Clear chip select

Referenced by XNandPs_ReadSpareBytes(), and XNandPs_WriteSpareBytes().

#define XNANDPS_CMD_PHASE 1

End command in command phase.

Referenced by XNandPs_SendCommand().

#define XNANDPS_COLUMN_NOT_VALID -1

Column is not valid in command phase.

Referenced by Onfi_CmdReadStatus(), XNandPs_EraseBlock(), XNandPs_ReadCache(), and XNandPs_SendCommand().

#define XNANDPS_COMMAND_PHASE_MASK 0x00000000

Command phase mask.

Referenced by XNandPs_ReadSpareBytes(), and XNandPs_SendCommand().

#define XNANDPS_DATA_PHASE 2

End command in data phase.

Referenced by XNandPs_SendCommand().

#define XNANDPS_DATA_PHASE_MASK 0x00080000

Data phase mask.

Referenced by XNandPs_SendCommand().

#define XNANDPS_DIRECT_CMD_ADDR_MASK 0x000FFFFF

Direct command address mask.

#define XNANDPS_DIRECT_CMD_CHIP_SELECT_MASK 0x03800000

Direct command chip select mask.

#define XNANDPS_DIRECT_CMD_CHIP_SELECT_SHIFT 23

Direct command chip select shift.

#define XNANDPS_DIRECT_CMD_CMD_TYPE_SHIFT 21

Direct command cmd_type shift.

#define XNANDPS_DIRECT_CMD_OFFSET 0x010

Direct command reg, WO.

#define XNANDPS_DIRECT_CMD_SET_CRE_MASK 0x00100000

Direct command set cre mask.

#define XNANDPS_DIRECT_CMD_SET_CRE_SHIFT 20

Direct command set_cre shift.

#define XNANDPS_DIRECT_CMD_TYPE_MASK 0x00600000

Direct command type mask.

#define XNANDPS_ECC_ADDR0_OFFSET ( addr ) (0x010 + addr)

ECC address0 reg.

#define XNANDPS_ECC_ADDR1_OFFSET ( addr ) (0x014 + addr)

ECC address1 reg.

#define XNANDPS_ECC_BLOCK_SIZE 512

ECC block size.

#define XNANDPS_ECC_BYTES 3

ECC bytes per ECC block.

#define XNANDPS_ECC_CAN_CORRECT_MASK 0x01F00000

Ecc status ecc_can_correct mask.

#define XNANDPS_ECC_CMD1

Value:

((0x80 << XNANDPS_ECC_MEMCOMMAND1_WR_CMD_SHIFT) | \
         (0x00 << XNANDPS_ECC_MEMCOMMAND1_RD_CMD_SHIFT)  | \
         (0x30 << XNANDPS_ECC_MEMCOMMAND1_RD_CMD_END_SHIFT) | \
         (0x1 << XNANDPS_ECC_MEMCOMMAND1_RD_CMD_END_VALID_SHIFT))

ECC command 1 settings.

Referenced by XNandPs_Read().

#define XNANDPS_ECC_CMD2

Value:

((0x85 << XNANDPS_ECC_MEMCOMMAND2_WR_COL_CHANGE_SHIFT) | \
         (0x05 << XNANDPS_ECC_MEMCOMMAND2_RD_COL_CHANGE_SHIFT)  | \
         (0xE0 << XNANDPS_ECC_MEMCOMMAND2_RD_COL_CHANGE_END_SHIFT) | \
         (0x1 << XNANDPS_ECC_MEMCOMMAND2_RD_COL_CHANGE_END_VALID_SHIFT))

ECC command 2 settings.

Referenced by XNandPs_Read().

#define XNANDPS_ECC_CORRECT_BIT_MASK 0x7

ECC error correction bit position mask, bits[0:2] of error code.

#define XNANDPS_ECC_CORRECT_BYTE_MASK 0x1FF

ECC error correction byte position mask, bits[11:3] of error code.

#define XNANDPS_ECC_FAIL_MASK 0x000F8000

Ecc status ecc_fail mask.

#define XNANDPS_ECC_LAST (0x1 << XNANDPS_ECC_LAST_SHIFT)

set Ecc last

#define XNANDPS_ECC_LAST_MASK 0x00000180

Ecc status ecc_last mask.

#define XNANDPS_ECC_LAST_SHIFT 10

Ecc last shift.

Referenced by XNandPs_SendCommand().

#define XNANDPS_ECC_MEMCFG

Value:

((0x1 << XNANDPS_ECC_MEMCFG_ECC_MODE_SHIFT) | \
         (0x1 << XNANDPS_ECC_MEMCFG_ECC_READ_END_SHIFT)  | \
         (0x0 << XNANDPS_ECC_MEMCFG_ECC_JUMP_SHIFT))

ECC memory configuration settings.

#define XNANDPS_ECC_MEMCFG_ECC_EXTRA_BLOCK_MASK 0x00000400

Ecc cfg ecc_extra_block mask.

#define XNANDPS_ECC_MEMCFG_ECC_EXTRA_BLOCK_SHIFT 10

Ecc cfg ecc_extra_block shift.

#define XNANDPS_ECC_MEMCFG_ECC_EXTRA_BLOCK_SIZE_MASK 0x00001800

Ecc cfg ecc_extra_block_size mask.

#define XNANDPS_ECC_MEMCFG_ECC_EXTRA_BLOCK_SIZE_SHIFT 11

Ecc cfg ecc_extra_block_size shift.

#define XNANDPS_ECC_MEMCFG_ECC_INT_ABORT_MASK 0x00000200

Ecc cfg ecc_int_abort mask.

#define XNANDPS_ECC_MEMCFG_ECC_INT_ABORT_SHIFT 9

Ecc cfg ecc_int_abort shift.

#define XNANDPS_ECC_MEMCFG_ECC_INT_PASS_MASK 0x00000100

Ecc cfg ecc_int_pass mask.

#define XNANDPS_ECC_MEMCFG_ECC_INT_PASS_SHIFT 8

Ecc cfg ecc_int_pass shift.

#define XNANDPS_ECC_MEMCFG_ECC_JUMP_MASK 0x00000060

Ecc cfg ecc_jump mask.

#define XNANDPS_ECC_MEMCFG_ECC_JUMP_SHIFT 5

Ecc cfg ecc_jump shift.

#define XNANDPS_ECC_MEMCFG_ECC_MODE_MASK 0x0000000C

Ecc cfg ecc_mode mask.

#define XNANDPS_ECC_MEMCFG_ECC_MODE_SHIFT 2

Ecc cfg ecc_mode shift.

#define XNANDPS_ECC_MEMCFG_ECC_READ_END_MASK 0x00000010

Ecc cfg ecc_read_end mask.

#define XNANDPS_ECC_MEMCFG_ECC_READ_END_SHIFT 4

Ecc cfg ecc_read_end shift.

#define XNANDPS_ECC_MEMCFG_IGNORE_ADD8_MASK 0x00000080

Ecc cfg ecc_ignore_add_eight mask.

#define XNANDPS_ECC_MEMCFG_IGNORE_ADD8_SHIFT 7

Ecc cfg ecc_ignore_add_eight shift.

#define XNANDPS_ECC_MEMCFG_OFFSET ( addr ) (0x004 + addr)

ECC mem config reg.

#define XNANDPS_ECC_MEMCFG_PAGE_SIZE_1024 0x2

ECC cfg page size value for 1024 byte page.

#define XNANDPS_ECC_MEMCFG_PAGE_SIZE_2048 0x3

ECC cfg page size value for 2048 byte page.

#define XNANDPS_ECC_MEMCFG_PAGE_SIZE_512 0x1

ECC cfg page size value for 512 byte page.

#define XNANDPS_ECC_MEMCFG_PAGE_SIZE_MASK 0x00000003

Ecc cfg page_size mask.

#define XNANDPS_ECC_MEMCFG_PAGE_SIZE_SHIFT 0

Ecc cfg page_size shift.

#define XNANDPS_ECC_MEMCMD1_OFFSET ( addr ) (0x008 + addr)

ECC mem com1 reg.

#define XNANDPS_ECC_MEMCMD2_OFFSET ( addr ) (0x00C + addr)

ECC mem com2 reg.

#define XNANDPS_ECC_READ_MASK 0x37000000

Ecc status ecc_read mask.

#define XNANDPS_ECC_READ_NOT_WRITE_MASK 0x00000200

Ecc status ecc_read_not_write mask.

#define XNANDPS_ECC_STATUS_MASK 0x00000040

Ecc status ecc_status mask.

#define XNANDPS_ECC_STATUS_OFFSET ( addr ) (0x000 + addr)

ECC status register.

#define XNANDPS_ECC_STATUS_RAW_INT_STATUS_MASK 0x0000003F

Ecc status raw_int_status mask.

#define XNANDPS_ECC_VALID_MASK 0x00007C00

Ecc status ecc_valid mask.

#define XNANDPS_ECC_VALUE0_OFFSET ( addr ) (0x018 + addr)

ECC value 0 reg.

#define XNANDPS_ECC_VALUE1_OFFSET ( addr ) (0x01C + addr)

ECC value 1 reg.

#define XNANDPS_ECC_VALUE2_OFFSET ( addr ) (0x020 + addr)

ECC value 2 reg.

#define XNANDPS_ECC_VALUE3_OFFSET ( addr ) (0x024 + addr)

ECC value 3 reg.

#define XNANDPS_ECC_VALUE4_OFFSET ( addr ) (0x028 + addr)

ECC value 4 reg.

#define XNANDPS_END_CMD_INVALID 0

End command invalid.

#define XNANDPS_END_CMD_NONE 0

No End command.

#define XNANDPS_END_CMD_SHIFT 11

End command shift.

Referenced by XNandPs_ReadSpareBytes(), and XNandPs_SendCommand().

#define XNANDPS_END_CMD_VALID_SHIFT 20

End command valid shift.

Referenced by XNandPs_ReadSpareBytes(), and XNandPs_SendCommand().

#define XNANDPS_FLASH_BLOCK_BAD 0x2

Block is bad.

#define XNANDPS_FLASH_BLOCK_FACTORY_BAD 0x0

Factory marked bad block.

#define XNANDPS_FLASH_BLOCK_GOOD 0x3

Block is good.

#define XNANDPS_FLASH_BLOCK_RESERVED 0x1

Reserved block.

#define XNANDPS_FLASH_CYCLES ( addr ) (0x000 + addr)

NAND & SRAM cycle,RO.

#define XNANDPS_FLASH_WIDTH_16 16

NAND Flash width 16-bit.

Referenced by Onfi_CmdReadStatus(), Onfi_NandInit(), and XNandPs_SendCommand().

#define XNANDPS_FLASH_WIDTH_8 8

NAND Flash width 8-bit.

Referenced by Onfi_NandInit().

#define XNANDPS_IF0_CHIP_0_CONFIG_OFFSET 0x100

Interface 0 chip 0 config.

#define XNANDPS_IF0_CHIP_1_CONFIG_OFFSET 0x120

Interface 0 chip 1 config.

#define XNANDPS_IF0_CHIP_2_CONFIG_OFFSET 0x140

Interface 0 chip 2 config.

#define XNANDPS_IF0_CHIP_3_CONFIG_OFFSET 0x160

Interface 0 chip 3 config.

#define XNANDPS_IF0_ECC_OFFSET 0x300

Interface 0 ECC register.

#define XNANDPS_IF1_CHIP_0_CONFIG_OFFSET 0x180

Interface 1 chip 0 config.

#define XNANDPS_IF1_CHIP_1_CONFIG_OFFSET 0x1A0

Interface 1 chip 1 config.

#define XNANDPS_IF1_CHIP_2_CONFIG_OFFSET 0x1C0

Interface 1 chip 2 config.

#define XNANDPS_IF1_CHIP_3_CONFIG_OFFSET 0x1E0

Interface 1 chip 3 config.

#define XNANDPS_IF1_ECC_OFFSET 0x400

Interface 1 ECC register.

#define XNANDPS_INTGTEST_OFFSET 0xE00

Integration test offset.

#define XNANDPS_MAX_BLOCKS 32768

Max number of Blocks.

Referenced by Onfi_NandInit().

#define XNANDPS_MAX_LUNS 8

Max number of LUNs.

Referenced by Onfi_NandInit().

#define XNANDPS_MAX_PAGE_SIZE 16384

Max page size of NAND flash.

Referenced by Onfi_NandInit().

#define XNANDPS_MAX_PAGES_PER_BLOCK 512

Max number pages per block.

Referenced by Onfi_NandInit().

#define XNANDPS_MAX_SPARE_SIZE 512

Max spare bytes of a NAND flash page.

Referenced by Onfi_NandInit().

#define XNANDPS_MAX_TARGETS 1

Max number of targets supported.

Referenced by Onfi_NandInit().

#define XNANDPS_MEMC_CLR_CONFIG_ECC_INT_DISABLE0_MASK 0x00000020

Memory controller interface0 ECC interrupt disable mask.

#define XNANDPS_MEMC_CLR_CONFIG_ECC_INT_DISABLE1_MASK 0x00000040

Memory controller interface1 ECC interrupt disable mask.

#define XNANDPS_MEMC_CLR_CONFIG_INT_CLR0_MASK 0x00000008

Memory controller interface0 interrupt clear mask.

#define XNANDPS_MEMC_CLR_CONFIG_INT_CLR1_MASK 0x00000010

Memory controller interface1 interrupt clear mask.

Referenced by XNandPs_EraseBlock(), XNandPs_Read(), XNandPs_ReadCache(), XNandPs_ReadSpareBytes(), and XNandPs_WriteSpareBytes().

#define XNANDPS_MEMC_CLR_CONFIG_INT_DISABLE0_MASK 0x00000001

Memory controller interface 0 interrupt disable mask.

#define XNANDPS_MEMC_CLR_CONFIG_INT_DISABLE1_MASK 0x00000002

Memory controller interface 1 interrupt disable mask.

#define XNANDPS_MEMC_CLR_CONFIG_LOW_POWER_EXIT_MASK 0x00000004

Memory controller low power exit mask.

#define XNANDPS_MEMC_CLR_CONFIG_OFFSET 0x00C

Clear config reg, WO.

Referenced by XNandPs_CfgInitialize(), XNandPs_EraseBlock(), XNandPs_Read(), XNandPs_ReadCache(), XNandPs_ReadSpareBytes(), and XNandPs_WriteSpareBytes().

#define XNANDPS_MEMC_IF_CONFIG_EX_MONITORS_MASK 0x00030000

Memory controller interface exclusive masks mask.

#define XNANDPS_MEMC_IF_CONFIG_MEMORY_CHIPS0_MASK 0x0000000C

Memory controller interface 0 chip select mask.

#define XNANDPS_MEMC_IF_CONFIG_MEMORY_CHIPS1_MASK 0x00000C00

Memory controller interface 1 chip select mask.

#define XNANDPS_MEMC_IF_CONFIG_MEMORY_TYPE0_MASK 0x00000003

Memory controller interface 0 type mask.

#define XNANDPS_MEMC_IF_CONFIG_MEMORY_TYPE1_MASK 0x00000300

Memory controller interface 1 type mask.

#define XNANDPS_MEMC_IF_CONFIG_MEMORY_WIDTH0_MASK 0x00000030

Memory controller interface 0 data width mask.

#define XNANDPS_MEMC_IF_CONFIG_MEMORY_WIDTH1_MASK 0x00003000

Memory controller interface 1 data width mask.

#define XNANDPS_MEMC_IF_CONFIG_OFFSET 0x004

Interface config reg, RO.

#define XNANDPS_MEMC_IF_CONFIG_REMAP0_MASK 0x00000040

Memory controller interface 0 remap0 mask.

#define XNANDPS_MEMC_IF_CONFIG_REMAP1_MASK 0x00004000

Memory controller interface 1 remap0 mask.

#define XNANDPS_MEMC_SET_CONFIG_ECC_INT_ENABLE0_MASK 0x00000020

Memory controller interfce0 ECC interrupt enable mask.

#define XNANDPS_MEMC_SET_CONFIG_ECC_INT_ENABLE1_MASK 0x00000040

Memory controller interfce1 ECC interrupt enable mask.

#define XNANDPS_MEMC_SET_CONFIG_INT_ENABLE0_MASK 0x00000001

Memory controller interfce0 interrupt enable mask.

#define XNANDPS_MEMC_SET_CONFIG_INT_ENABLE1_MASK 0x00000002

Memory controller interfce1 interrupt enable mask.

#define XNANDPS_MEMC_SET_CONFIG_LOW_POWER_REQ_MASK 0x00000004

Memory controller low power state mask.

#define XNANDPS_MEMC_SET_CONFIG_OFFSET 0x008

Set configuration reg, WO.

#define XNANDPS_MEMC_STATUS_ECC_INT0_MASK 0x00000200

Memory controller interface 0 ECC interrupt status mask.

#define XNANDPS_MEMC_STATUS_ECC_INT1_MASK 0x00000400

Memory controller interface 1 ECC interrupt status mask.

#define XNANDPS_MEMC_STATUS_ECC_INT_EN0_MASK 0x00000080

Memory controller interface 0 ECC interrupt enable mask.

#define XNANDPS_MEMC_STATUS_ECC_INT_EN1_MASK 0x00000100

Memory controller interface 1 ECC interrupt enable mask.

#define XNANDPS_MEMC_STATUS_INT_EN0_MASK 0x00000002

Memory controller interface 0 interrupt enable mask.

#define XNANDPS_MEMC_STATUS_INT_EN1_MASK 0x00000004

Memory controller interface 1 interrupt enable mask.

#define XNANDPS_MEMC_STATUS_INT_STATUS0_MASK 0x00000008

Memory controller interface 0 interrupt status mask.

#define XNANDPS_MEMC_STATUS_INT_STATUS1_MASK 0x00000010

Memory controller interface 1 interrupt status mask.

#define XNANDPS_MEMC_STATUS_OFFSET 0x000

Controller status reg, RO.

#define XNANDPS_MEMC_STATUS_RAW_ECC_INT0_MASK 0x00000800

Memory controller interface 0 raw ECC interrupt status mask.

#define XNANDPS_MEMC_STATUS_RAW_ECC_INT1_MASK 0x00001000

Memory controller interface 1 raw ECC interrupt status mask.

#define XNANDPS_MEMC_STATUS_RAW_INT_STATUS0_MASK 0x00000020

Memory controller interface 0 raw interrupt status mask.

#define XNANDPS_MEMC_STATUS_RAW_INT_STATUS1_MASK 0x00000040

Memory controller interface 1 raw interrupt status mask.

#define XNANDPS_MEMC_STATUS_STATE_MASK 0x00000001

Memory controller operating state mask.

#define XNANDPS_OPMODE ( addr ) (0x004 + addr)

Chip opmode reg, RO.

#define XNANDPS_OPMODE_ADDRESS_MASK 0x00FF0000

Opmode Address match mask.

#define XNANDPS_OPMODE_ADV_MASK 0x00000800

Opmode BLS mask.

#define XNANDPS_OPMODE_BAA_MASK 0x00000400

Opmode ADV mask.

#define XNANDPS_OPMODE_BLS_MASK 0x00001000

Opmode Burst align mask.

#define XNANDPS_OPMODE_BURST_ALIGN_MASK 0x0000E000

Opmode Address mask.

#define XNANDPS_OPMODE_MW_MASK 0x00000003

Opmode Memory width mask.

#define XNANDPS_OPMODE_RD_BL_MASK 0x00000038

Opmode rd_bl mask.

#define XNANDPS_OPMODE_RD_SYNC_MASK 0x00000004

Opmode rd_sync mask.

#define XNANDPS_OPMODE_WR_BL_MASK 0x00000380

Opmode BAA mask.

#define XNANDPS_OPMODE_WR_SYNC_MASK 0x00000040

Opmode wr_sync mask.

#define XNANDPS_PAGE_NOT_VALID -1

Page is not valid in command phase.

Referenced by Onfi_CmdReadStatus(), XNandPs_ReadCache(), and XNandPs_SendCommand().

#define XNANDPS_PAGE_SIZE_1024 1024

Page size 1024.

#define XNANDPS_PAGE_SIZE_2048 2048

Page size 2048.

#define XNANDPS_PAGE_SIZE_4096 4096

Page size 4096.

#define XNANDPS_PAGE_SIZE_512 512

Page size 512.

#define XNANDPS_PAGE_SIZE_8192 8192

Page size 8192.

#define XNANDPS_PCELL_ID0_OFFSET 0xFF0

Primecell id0 register.

#define XNANDPS_PCELL_ID1_OFFSET 0xFF4

Primecell id1 register.

#define XNANDPS_PCELL_ID2_OFFSET 0xFF8

Primecell id2 register.

#define XNANDPS_PCELL_ID3_OFFSET 0xFFC

Primecell id3 register.

#define XNANDPS_PERIPH_ID0_OFFSET 0xFE0

Peripheral id0 register.

#define XNANDPS_PERIPH_ID1_OFFSET 0xFE4

Peripheral id1 register.

#define XNANDPS_PERIPH_ID2_OFFSET 0xFE8

Peripheral id2 register.

#define XNANDPS_PERIPH_ID3_OFFSET 0xFEC

Peripheral id3 register.

#define XNANDPS_REFRESH_PERIOD_0_MASK 0x0000000F

Interface 0 refresh period mask.

#define XNANDPS_REFRESH_PERIOD_0_OFFSET 0x020

Refresh period_0 reg, RW.

#define XNANDPS_REFRESH_PERIOD_1_MASK 0x0000000F

Interface 1 refresh period mask.

#define XNANDPS_REFRESH_PERIOD_1_OFFSET 0x024

Refresh period_1 reg, RW.

#define XNANDPS_SET_CYCLES_OFFSET 0x014

Set cycles register, WO.

#define XNANDPS_SET_CYCLES_SET_T0_MASK 0x0000000F

Set cycles set_t0 mask.

#define XNANDPS_SET_CYCLES_SET_T0_SHIFT 0

Set cycles set_t0 shift.

#define XNANDPS_SET_CYCLES_SET_T1_MASK 0x000000F0

Set cycles set_t1 mask.

#define XNANDPS_SET_CYCLES_SET_T1_SHIFT 4

Set cycles set_t1 shift.

#define XNANDPS_SET_CYCLES_SET_T2_MASK 0x00000700

Set cycles set_t2 mask.

#define XNANDPS_SET_CYCLES_SET_T2_SHIFT 8

Set cycles set_t2 shift.

#define XNANDPS_SET_CYCLES_SET_T3_MASK 0x00003800

Set cycles set_t3 mask.

#define XNANDPS_SET_CYCLES_SET_T3_SHIFT 11

Set cycles set_t3 shift.

#define XNANDPS_SET_CYCLES_SET_T4_MASK 0x0001C000

Set cycles set_t4 mask.

#define XNANDPS_SET_CYCLES_SET_T4_SHIFT 14

Set cycles set_t4 shift.

#define XNANDPS_SET_CYCLES_SET_T5_MASK 0x000E0000

Set cycles set_t5 mask.

#define XNANDPS_SET_CYCLES_SET_T5_SHIFT 17

Set cycles set_t5 shift.

#define XNANDPS_SET_CYCLES_SET_T6_MASK 0x00F00000

Set cycles set_t6 mask.

#define XNANDPS_SET_CYCLES_SET_T6_SHIFT 20

Set cycles set_t6 shift.

#define XNANDPS_SET_OPMODE_MW_16_BITS 0x1

Set opmode memory width value for 16-bit flash.

#define XNANDPS_SET_OPMODE_MW_32_BITS 0x2

Set opmode memory width value for 32-bit flash.

#define XNANDPS_SET_OPMODE_MW_8_BITS 0x0

Set opmode memory width value for 8-bit flash.

#define XNANDPS_SET_OPMODE_OFFSET 0x018

Set opmode register, WO.

#define XNANDPS_SET_OPMODE_SET_ADV_MASK 0x00000800

Set opmode set adv mask.

#define XNANDPS_SET_OPMODE_SET_BAA_MASK 0x00000400

Set opmode set baa mask.

#define XNANDPS_SET_OPMODE_SET_BLS_MASK 0x00001000

Set opmode set bls mask.

#define XNANDPS_SET_OPMODE_SET_BURST_ALIGN_MASK 0x0000E000

Set opmode set burst align mask.

#define XNANDPS_SET_OPMODE_SET_MW_MASK 0x00000003

Set opmode set memory width mask.

#define XNANDPS_SET_OPMODE_SET_RD_BL_MASK 0x00000038

Set opmode set rd_bl mask.

#define XNANDPS_SET_OPMODE_SET_RD_SYNC_MASK 0x00000004

Set opmode set rd_sync mask.

#define XNANDPS_SET_OPMODE_SET_WR_BL_MASK 0x00000380

Set opmode set wr_bl mask.

#define XNANDPS_SET_OPMODE_SET_WR_SYNC_MASK 0x00000040

Set opmode set wr_sync mask.

#define XNANDPS_SPARE_SIZE_128 128

Spare bytes size 128.

#define XNANDPS_SPARE_SIZE_16 16

Spare bytes size 16.

#define XNANDPS_SPARE_SIZE_256 256

Spare bytes size 256.

#define XNANDPS_SPARE_SIZE_32 32

Spare bytes size 32.

#define XNANDPS_SPARE_SIZE_64 64

Spare bytes size 64.

#define XNANDPS_SPARE_SIZE_8 8

Spare bytes size 8.

#define XNANDPS_START_CMD_SHIFT 3

Start command shift.

Referenced by XNandPs_ReadSpareBytes(), and XNandPs_SendCommand().

#define XNANDPS_USER_CONFIG_MASK 0x000000FF

User config mask.

#define XNANDPS_USER_CONFIG_OFFSET 0x204

User config reg, WO.

#define XNANDPS_USER_STATUS_MASK 0x000000FF

User status mask.

#define XNANDPS_USER_STATUS_OFFSET 0x200

User status reg, RO.

Typedef Documentation

typedef struct XNandPsTag XNandPs

The XNandPs driver instance data.

The user is required to allocate a variable of this type for every flash device in the system. A pointer to a variable of this type is then passed to the driver API functions.

Enumeration Type Documentation

enum OnfiCommandsEnum

This enum defines the onfi commands.

Enumerator
READ	ONFI Read.
CHANGE_READ_COLUMN	ONFI Change Read Column.
BLOCK_ERASE	ONFI Block Erase.
READ_STATUS	ONFI Read Status.
PAGE_PROGRAM	ONFI Page Program.
CHANGE_WRITE_COLUMN	ONFI Change Write Column.
READ_ID	ONFI Read ID.
READ_PARAM_PAGE	ONFI Read Parameter Page.
RESET	ONFI Reset.
GET_FEATURES	ONFI Get Features.
SET_FEATURES	ONFI Set Features.
READ_CACHE_RANDOM	ONFI Read page cache random.
READ_CACHE_END_SEQ	ONFI Read page cache end.
PAGE_CACHE_PROGRAM	ONFI Program page cache.

enum XNandPs_EccMode

Enumerator
XNANDPS_ECC_NONE	No ECC.
XNANDPS_ECC_SW	Software ECC.
XNANDPS_ECC_HW	Hardware controller ECC.
XNANDPS_ECC_ONDIE	On-Die ECC.

Function Documentation

u8 Onfi_CmdReadStatus ( XNandPs * InstancePtr )

This function sends read status command to the flash device.

Parameters

InstancePtr is a pointer to the XNandPs instance.

Returns: flash status value read

Note: None

References XNandPsTag::Config, XNandPsTag::DataPhaseAddr, XNandPs_Config::FlashWidth, READ_STATUS, XNANDPS_COLUMN_NOT_VALID, XNANDPS_FLASH_WIDTH_16, XNANDPS_PAGE_NOT_VALID, and XNandPs_SendCommand().

Referenced by XNandPs_EraseBlock(), XNandPs_ReadCache(), XNandPs_ReadSpareBytes(), XNandPs_Write(), XNandPs_WriteCache(), and XNandPs_WriteSpareBytes().

int Onfi_NandInit ( XNandPs * InstancePtr )

This function initializes the NAND flash and gets the geometry information.

Parameters

InstancePtr is a pointer to the XNandPs instance.

Returns

XST_SUCCESS if successful.
XST_FAILURE if failed.

Note: None

References XNandPs_CommandFormat::AddrCycles, BLOCK_ERASE, XNandPs_Geometry::BlockSize, XNandPs_Geometry::BlocksPerLun, XNandPs_Geometry::BytesPerPage, CHANGE_READ_COLUMN, CHANGE_WRITE_COLUMN, XNandPs_Geometry::ColAddrCycles, XNandPs_Geometry::DeviceSize, XNandPsTag::EccMode, XNandPsTag::Features, XNandPs_Geometry::FlashWidth, XNandPsTag::Geometry, XNandPs_Geometry::NumBlocks, XNandPs_Geometry::NumLun, XNandPs_Geometry::NumPages, ONFI_ID_LEN, PAGE_PROGRAM, XNandPs_Geometry::PagesPerBlock, READ, XNandPs_Geometry::RowAddrCycles, XNandPs_Geometry::SpareBytesPerPage, XNANDPS_ECC_HW, XNANDPS_ECC_NONE, XNANDPS_ECC_ONDIE, XNANDPS_FLASH_WIDTH_16, XNANDPS_FLASH_WIDTH_8, XNANDPS_MAX_BLOCKS, XNANDPS_MAX_LUNS, XNANDPS_MAX_PAGE_SIZE, XNANDPS_MAX_PAGES_PER_BLOCK, XNANDPS_MAX_SPARE_SIZE, and XNANDPS_MAX_TARGETS.

Referenced by XNandPs_CfgInitialize().

int XNandPs_CfgInitialize	(	XNandPs *	InstancePtr,
		XNandPs_Config *	ConfigPtr,
		u32	SmcBaseAddr,
		u32	FlashBaseAddr
	)

This function initializes a specific XNandPs device/instance.

This function must be called prior to using the flash device to read or write any data.

Parameters

InstancePtr	is a pointer to the XNandPs instance.
ConfigPtr	points to the XNandPs device configuration structure.
SmcBaseAddr	is the base address of SMC controller.
FlashBaseAddr	is the base address of NAND flash.

Returns

XST_SUCCESS if successful.
XST_FAILURE if fail.

Note: The user needs to first call the XNandPs_LookupConfig() API which returns the Configuration structure pointer which is passed as a parameter to the XNandPs_CfgInitialize() API.

References XNandPs_Geometry::BytesPerPage, XNandPsTag::Config, XNandPsTag::DataBuf, XNandPs_Config::DeviceId, XNandPsTag::EccMode, XNandPs_Config::FlashBase, XNandPs_Config::FlashWidth, XNandPs_Geometry::FlashWidth, XNandPsTag::Geometry, XNandPsTag::IsReady, Onfi_NandInit(), XNandPsTag::ReadPage, XNandPs_Config::SmcBase, XNandPsTag::SpareBufPtr, XNandPsTag::WritePage, XNANDPS_CLR_CONFIG, XNANDPS_ECC_HW, XNANDPS_ECC_NONE, XNANDPS_ECC_ONDIE, XNandPs_InitBbtDesc(), XNANDPS_MEMC_CLR_CONFIG_OFFSET, XNandPs_ScanBbt(), and XNandPs_WriteReg.

Referenced by NandReadWriteCacheExample(), NandReadWriteExample(), and NandSkipBlockExample().

int XNandPs_EraseBlock	(	XNandPs *	InstancePtr,
		u32	BlockNum
	)

This function erases a specific block in the NAND device.

Parameters

InstancePtr	is a pointer to the XNandPs instance.
BlockNum	is the block number of the device.

Returns

XST_SUCCESS if successful.
XST_FAILURE if fail.
XST_NAND_WRITE_PROTECTED if the flash is write protected.

Note: None

References BLOCK_ERASE, XNandPsTag::Config, XNandPsTag::Geometry, XNandPsTag::IsReady, Onfi_CmdReadStatus(), ONFI_STATUS_WP, XNandPs_Geometry::PagesPerBlock, XNandPs_Config::SmcBase, XNANDPS_COLUMN_NOT_VALID, XNANDPS_MEMC_CLR_CONFIG_INT_CLR1_MASK, XNANDPS_MEMC_CLR_CONFIG_OFFSET, XNandPs_SendCommand(), and XNandPs_WriteReg.

Referenced by NandReadWriteCacheExample(), NandReadWriteExample(), and XNandPs_SkipErase().

void XNandPs_InitBbtDesc ( XNandPs * InstancePtr )

This function initializes the Bad Block Table(BBT) descriptors with a predefined pattern for searching Bad Block Table(BBT) in flash.

Parameters

InstancePtr is a pointer to the XNandPs instance.

Returns

NONE

References XNandPsTag::BbPattern, XNandPsTag::BbtDesc, XNandPsTag::BbtMirrorDesc, XNandPs_Geometry::BytesPerPage, XNandPsTag::EccMode, XNandPsTag::Geometry, XNandPsTag::IsReady, XNandPs_BadBlockPattern::Length, XNandPs_BbtDesc::MaxBlocks, XNandPs_BadBlockPattern::Offset, XNandPs_BadBlockPattern::Options, XNandPs_BbtDesc::PageOffset, XNandPs_BadBlockPattern::Pattern, XNandPs_BbtDesc::SigLength, XNandPs_BbtDesc::Signature, XNandPs_BbtDesc::SigOffset, XNandPs_BbtDesc::Valid, XNandPs_BbtDesc::VerOffset, XNandPs_BbtDesc::Version, XNANDPS_BB_PATTERN, XNANDPS_BB_PATTERN_LENGTH_LARGE_PAGE, XNANDPS_BB_PATTERN_LENGTH_SMALL_PAGE, XNANDPS_BB_PATTERN_OFFSET_LARGE_PAGE, XNANDPS_BB_PATTERN_OFFSET_SMALL_PAGE, XNANDPS_BBT_DESC_MAX_BLOCKS, XNANDPS_BBT_DESC_PAGE_OFFSET, XNANDPS_BBT_DESC_SIG_LEN, XNANDPS_BBT_DESC_SIG_OFFSET, XNANDPS_BBT_DESC_VER_OFFSET, XNANDPS_BBT_SCAN_2ND_PAGE, and XNANDPS_ECC_ONDIE.

Referenced by XNandPs_CfgInitialize().

int XNandPs_IsBlockBad	(	XNandPs *	InstancePtr,
		u32	Block
	)

This function checks whether a block is bad or not.

Parameters

InstancePtr	is the pointer to the XNandPs instance.
Block	is the block number.

Returns

XST_SUCCESS if successful.
XST_FAILURE if fail.

References XNandPsTag::Bbt, XNandPsTag::IsReady, XNANDPS_BBT_BLOCK_SHIFT, XNandPs_BbtBlockShift, XNANDPS_BLOCK_GOOD, and XNANDPS_BLOCK_TYPE_MASK.

Referenced by NandReadWriteCacheExample(), NandReadWriteExample(), XNandPs_CalculateLength(), XNandPs_SkipErase(), XNandPs_SkipRead(), and XNandPs_SkipWrite().

XNandPs_Config * XNandPs_LookupConfig ( u16 DeviceId )

This function looks up the device configuration based on the unique device ID.

The table XNandPs_ConfigTable contains the configuration info for each device in the system.

Parameters

DeviceId contains the ID of the device for which the device configuration pointer is to be returned.

Returns

A pointer to the configuration found.
NULL if the specified device ID was not found.

Note: None.

Referenced by NandReadWriteCacheExample(), NandReadWriteExample(), and NandSkipBlockExample().

int XNandPs_MarkBlockBad	(	XNandPs *	InstancePtr,
		u32	Block
	)

This function marks a block as bad in the RAM based Bad Block Table(BBT).

It also updates the Bad Block Table(BBT) in the flash.

Parameters

InstancePtr	is the pointer to the XNandPs instance.
Block	is the block number.

Returns

XST_SUCCESS if successful.
XST_FAILURE if fail.

References XNandPsTag::Bbt, XNandPsTag::IsReady, XNANDPS_BBT_BLOCK_SHIFT, XNandPs_BbtBlockShift, XNANDPS_BLOCK_BAD, and XNANDPS_BLOCK_TYPE_MASK.

int XNandPs_Read	(	XNandPs *	InstancePtr,
		u64	Offset,
		u32	Length,
		void *	DestPtr,
		u8 *	UserSparePtr
	)

This function reads the data from the Flash device and copies it into the specified user buffer.

It doesn't check for the bad blocks while reading the flash pages that cross block boundary. User must take care of handling bad blocks.

Parameters

InstancePtr	is the pointer to the XNandPs instance.
Offset	is the flash data address to read from.
Length	is number of bytes to read.
DestPtr	is the destination address to copy data to.
UserSparePtr	is the user buffer to which spare data must be copied.

Returns

XST_SUCCESS if successful.
XST_FAILURE if fail.

Note: This function reads sequential pages from the Flash device.

References XNandPs_Geometry::BytesPerPage, XNandPsTag::Config, XNandPsTag::DataBuf, XNandPs_Geometry::DeviceSize, XNandPsTag::Geometry, XNandPsTag::IsReady, READ, XNandPsTag::ReadPage, XNandPs_Config::SmcBase, XNandPsTag::SpareBufPtr, XNandPs_Geometry::SpareBytesPerPage, XNANDPS_ECC_CMD1, XNANDPS_ECC_CMD2, XNANDPS_MEMC_CLR_CONFIG_INT_CLR1_MASK, XNANDPS_MEMC_CLR_CONFIG_OFFSET, XNandPs_SendCommand(), and XNandPs_WriteReg.

Referenced by NandReadWriteExample(), XNandPs_ReadCache(), and XNandPs_SkipRead().

int XNandPs_ReadCache	(	XNandPs *	InstancePtr,
		u64	Offset,
		u32	Length,
		void *	DestPtr,
		u8 *	UserSparePtr
	)

This function reads the data from the Flash device using read page cache command and copies it into the specified user buffer.

It doesn't check for the bad blocks while reading the flash pages that cross block boundary. User must take care of handling bad blocks.

Parameters

InstancePtr	is the pointer to the XNandPs instance.
Offset	is the flash data address to read from.
Length	is number of bytes to read.
DestPtr	is the destination address to copy data to.
UserSparePtr	is the user buffer to which spare data must be copied.

Returns

XST_SUCCESS if successful.
XST_FAILURE if fail.

Note: This function reads sequential pages from the Flash device.

References XNandPs_Geometry::BytesPerPage, CHANGE_READ_COLUMN, XNandPsTag::Config, XNandPsTag::DataBuf, XNandPs_Geometry::DeviceSize, XNandPsTag::Features, XNandPsTag::Geometry, XNandPsTag::IsReady, ONFI_CMD_CHANGE_READ_COLUMN1, ONFI_CMD_CHANGE_READ_COLUMN2, ONFI_CMD_PAGE_CACHE_PROGRAM1, ONFI_CMD_READ_CACHE_ENHANCED1, ONFI_CMD_READ_CACHE_ENHANCED2, Onfi_CmdReadStatus(), ONFI_STATUS_FAIL, READ, READ_CACHE_END_SEQ, READ_CACHE_RANDOM, XNandPsTag::ReadPage, XNandPs_Config::SmcBase, XNandPsTag::SpareBufPtr, XNandPs_Geometry::SpareBytesPerPage, XNANDPS_COLUMN_NOT_VALID, XNANDPS_ECC_MEMCOMMAND1_RD_CMD_END_VALID_MASK, XNANDPS_MEMC_CLR_CONFIG_INT_CLR1_MASK, XNANDPS_MEMC_CLR_CONFIG_OFFSET, XNANDPS_PAGE_NOT_VALID, XNandPs_Read(), XNandPs_SendCommand(), and XNandPs_WriteReg.

Referenced by NandReadWriteCacheExample().

int XNandPs_ReadSpareBytes	(	XNandPs *	InstancePtr,
		u32	Page,
		u8 *	Buf
	)

This function reads the spare area of a page.

Parameters

InstancePtr	is the pointer to the XNandPs instance.
Page	is the page number from where spare data is read.
Buf	is pointer to the buffer where the spare data is filled.

Returns

XST_SUCCESS if successful.
XST_FAILURE if fail.

Note: None.

References XNandPs_Geometry::BytesPerPage, XNandPsTag::Config, XNandPsTag::DataPhaseAddr, XNandPsTag::EccMode, XNandPs_Config::FlashBase, XNandPsTag::Geometry, Onfi_CmdReadStatus(), ONFI_STATUS_FAIL, READ, XNandPs_Config::SmcBase, XNandPs_Geometry::SpareBytesPerPage, XNANDPS_ADDR_CYCLES_SHIFT, XNANDPS_AXI_DATA_WIDTH, XNANDPS_CLR_CS, XNANDPS_COMMAND_PHASE_MASK, XNANDPS_ECC_HW, XNANDPS_END_CMD_SHIFT, XNANDPS_END_CMD_VALID_SHIFT, XNANDPS_MEMC_CLR_CONFIG_INT_CLR1_MASK, XNANDPS_MEMC_CLR_CONFIG_OFFSET, XNandPs_SendCommand(), XNANDPS_START_CMD_SHIFT, and XNandPs_WriteReg.

int XNandPs_ScanBbt ( XNandPs * InstancePtr )

This function reads the Bad Block Table(BBT) if present in flash.

If not it scans the flash for detecting factory marked bad blocks and creates a bad block table and write the Bad Block Table(BBT) into the flash.

Parameters

InstancePtr is a pointer to the XNandPs instance.

Returns

XST_SUCCESS if successful.
XST_FAILURE if fail.

References XNandPsTag::BbtDesc, XNandPsTag::BbtMirrorDesc, and XNandPsTag::IsReady.

Referenced by XNandPs_CfgInitialize().

void XNandPs_SendCommand	(	XNandPs *	InstancePtr,
		XNandPs_CommandFormat *	Command,
		int	Page,
		int	Column
	)

This function sends a NAND command to the flash device.

Parameters

InstancePtr	is the pointer to XNandPs structure
Command	is the NAND command to send
Page	is the page offset required for specific commands
Column	the column offset required for specific commands

Returns: None

Note: None

References XNandPs_CommandFormat::AddrCycles, XNandPs_Geometry::ColAddrCycles, XNandPsTag::CommandPhaseAddr, XNandPsTag::Config, XNandPsTag::DataPhaseAddr, XNandPs_CommandFormat::EndCmd, XNandPs_CommandFormat::EndCmdValid, XNandPs_Config::FlashBase, XNandPs_Geometry::FlashWidth, XNandPsTag::Geometry, ONFI_CMD_BLOCK_ERASE1, ONFI_CMD_PAGE_PROG1, ONFI_CMD_READ1, XNandPs_Geometry::RowAddrCycles, XNandPs_CommandFormat::StartCmd, XNANDPS_ADDR_CYCLES_SHIFT, XNANDPS_CLEAR_CS_SHIFT, XNANDPS_CMD_PHASE, XNANDPS_COLUMN_NOT_VALID, XNANDPS_COMMAND_PHASE_MASK, XNANDPS_DATA_PHASE, XNANDPS_DATA_PHASE_MASK, XNANDPS_ECC_LAST_SHIFT, XNANDPS_END_CMD_SHIFT, XNANDPS_END_CMD_VALID_SHIFT, XNANDPS_FLASH_WIDTH_16, XNANDPS_PAGE_NOT_VALID, XNANDPS_START_CMD_SHIFT, and XNandPs_WriteReg.

Referenced by Onfi_CmdReadStatus(), XNandPs_EraseBlock(), XNandPs_Read(), XNandPs_ReadCache(), XNandPs_ReadSpareBytes(), XNandPs_Write(), XNandPs_WriteCache(), and XNandPs_WriteSpareBytes().

int XNandPs_Write	(	XNandPs *	InstancePtr,
		u64	Offset,
		u32	Length,
		void *	SrcPtr,
		u8 *	UserSparePtr
	)

This function programs the flash device(s) with data specified in the user buffer.

The source and destination address must be aligned to the width of the flash's data bus. It doesn't check for the bad blocks while writing to the flash pages that cross block boundary. User must take care of handling bad blocks.

Parameters

InstancePtr	is the pointer to the XNandPs instance.
Offset	is the flash data address to write to.
Length	is number of bytes to write.
SrcPtr	is the source address to write the data from.
UserSparePtr	is the user buffer which contains buffer to write into spare data area.

Returns

XST_SUCCESS if successful.
XST_FAILURE if fail.
XST_NAND_WRITE_PROTECTED if the flash is write protected.

Note: This function writes number of sequential pages into the Flash device.

References XNandPs_Geometry::BytesPerPage, XNandPsTag::DataBuf, XNandPs_Geometry::DeviceSize, XNandPsTag::Geometry, XNandPsTag::IsReady, Onfi_CmdReadStatus(), ONFI_STATUS_WP, PAGE_PROGRAM, XNandPsTag::SpareBufPtr, XNandPs_Geometry::SpareBytesPerPage, XNandPsTag::WritePage, and XNandPs_SendCommand().

Referenced by NandReadWriteExample(), XNandPs_SkipWrite(), and XNandPs_WriteCache().

int XNandPs_WriteCache	(	XNandPs *	InstancePtr,
		u64	Offset,
		u32	Length,
		void *	SrcPtr,
		u8 *	UserSparePtr
	)

This function programs the flash device(s) with data specified in the user buffer using program cache command.

The source and destination address must be aligned to the width of the flash's data bus. It doesn't check for the bad blocks while writing to the flash pages that cross block boundary. User must take care of handling bad blocks.

Parameters

InstancePtr	is the pointer to the XNandPs instance.
Offset	is the flash data address to write to.
Length	is number of bytes to write.
SrcPtr	is the source address to write the data from.
UserSparePtr	is the user buffer which contains buffer to write into spare data area.

Returns

XST_SUCCESS if successful.
XST_FAILURE if fail.
XST_NAND_WRITE_PROTECTED if the flash is write protected.

Note: This function writes number of sequential pages into the Flash device.

References XNandPs_Geometry::BytesPerPage, XNandPsTag::DataBuf, XNandPs_Geometry::DeviceSize, XNandPsTag::Geometry, XNandPsTag::IsReady, Onfi_CmdReadStatus(), ONFI_STATUS_WP, PAGE_CACHE_PROGRAM, PAGE_PROGRAM, XNandPsTag::SpareBufPtr, XNandPs_Geometry::SpareBytesPerPage, XNandPsTag::WritePage, XNandPs_SendCommand(), and XNandPs_Write().

Referenced by NandReadWriteCacheExample().

int XNandPs_WriteSpareBytes	(	XNandPs *	InstancePtr,
		u32	Page,
		u8 *	Buf
	)

This function write to the spare area of a page.

Parameters

InstancePtr	is the pointer to the XNandPs instance.
Page	is the page number to write.
Buf	is pointer to the buffer which holds the data.

Returns

XST_SUCCESS if successful.
XST_FAILURE if fail.

Note: None.

References XNandPs_Geometry::BytesPerPage, XNandPsTag::Config, XNandPsTag::DataPhaseAddr, XNandPsTag::EccMode, XNandPsTag::Geometry, Onfi_CmdReadStatus(), ONFI_STATUS_FAIL, PAGE_PROGRAM, XNandPs_Config::SmcBase, XNandPs_Geometry::SpareBytesPerPage, XNANDPS_AXI_DATA_WIDTH, XNANDPS_CLR_CS, XNANDPS_ECC_HW, XNANDPS_MEMC_CLR_CONFIG_INT_CLR1_MASK, XNANDPS_MEMC_CLR_CONFIG_OFFSET, XNandPs_SendCommand(), and XNandPs_WriteReg.

Variable Documentation

u32 NandOob16[] = {13, 14, 15}

Ecc position for 16 bytes spare area.

u32 NandOob32[] = {26, 27, 28, 29, 30, 31}

Ecc position for 32 bytes spare area.

u32 NandOob64[]

Initial value:

= {52, 53, 54, 55, 56, 57,
                   58, 59, 60, 61, 62, 63
                  }

Ecc position for 64 bytes spare area.

XNandPs_CommandFormat OnfiCommands[]

This structure defines the onfi command format sent to the flash.

ONFI commands.

XNandPs_CommandFormat OnfiCommands[]

ONFI commands.

XNandPs_Config XNandPs_ConfigTable[]

This table contains configuration information for each System Monitor/ADC device in the system.

XNandPs_Config XNandPs_ConfigTable[XPAR_XNANDPS_NUM_INSTANCES]

Initial value:

= {
        {
                XPAR_XNANDPS_0_DEVICE_ID,       
                XPAR_XPARPORTPS_CTRL_BASEADDR,  
                XPAR_XNANDPS_0_BASEADDR,        
                XPAR_XNANDPS_0_FLASH_WIDTH      
        }
}

This table contains configuration information for each System Monitor/ADC device in the system.

Data Structures

Macros

Typedefs

Enumerations

Functions

Variables

Memory controller status register bit definitions and masks

Memory interface configurartion register bit definitions and masks

Set configuration register bit definitions and masks

Clear configuration register bit definitions and masks

Clear configuration register bit definitions and masks and shift

Set cycles register bit definitions and masks and shift

Set opmode register bit definitions and masks

Refresh period register bit definitions and masks

Opmode register bit definitions and masks

User status register bit definitions and masks

User config register bit definitions and masks

ECC status register bit definitions and masks

ECC mem config register bit definitions and masks and shifts

Macro Definition Documentation

Typedef Documentation

Enumeration Type Documentation

Function Documentation

Variable Documentation