Data Structures
struct	XNandPsu_Config
	The XNandPsu_Config structure contains configuration information for NAND controller. More...

struct	XNandPsu_BbtDesc
	Bad block table descriptor. More...

struct	XNandPsu_BadBlockPattern
	Bad block pattern. More...

struct	XNandPsu_Geometry
	The XNandPsu_Geometry structure contains the ONFI geometry information. More...

struct	XNandPsu_Features
	The XNandPsu_Features structure contains the ONFI features information. More...

struct	XNandPsu_EccMatrix
	The XNandPsu_EccMatrix structure contains ECC features information. More...

struct	XNandPsu_EccCfg
	The XNandPsu_EccCfg structure contains ECC configuration. More...

struct	XNandPsu
	The XNandPsu structure contains the driver instance data. More...

Macros
#define	XNANDPSU_MAX_TARGETS 1U
	ce_n0, ce_n1 More...

#define	XNANDPSU_MAX_PKT_SIZE 0x7FFU
	Max packet size. More...

#define	XNANDPSU_MAX_PKT_COUNT 0xFFFU
	Max packet count. More...

#define	XNANDPSU_PAGE_SIZE_512 512U
	512 bytes page More...

#define	XNANDPSU_PAGE_SIZE_2K 2048U
	2K bytes page More...

#define	XNANDPSU_PAGE_SIZE_4K 4096U
	4K bytes page More...

#define	XNANDPSU_PAGE_SIZE_8K 8192U
	8K bytes page More...

#define	XNANDPSU_PAGE_SIZE_16K 16384U
	16K bytes page More...

#define	XNANDPSU_PAGE_SIZE_1K_16BIT 1024U
	16-bit 2K bytes page More...

#define	XNANDPSU_MAX_PAGE_SIZE 16384U
	Max page size supported. More...

#define	XNANDPSU_HAMMING 0x1U
	Hamming Flash. More...

#define	XNANDPSU_BCH 0x2U
	BCH Flash. More...

#define	XNANDPSU_MAX_BLOCKS 16384U
	Max number of Blocks. More...

#define	XNANDPSU_MAX_SPARE_SIZE 0x800U
	Max spare bytes of a NAND flash page of 16K. More...

#define	XNANDPSU_MAX_LUNS 8U
	Max number of LUNs. More...

#define	XNANDPSU_MAX_PAGES_PER_BLOCK 512U
	Max number pages per block. More...

#define	XNandPsu_SetBits(InstancePtr, RegOffset, BitMask)
	This macro sets the bitmask in the register. More...

#define	XNandPsu_ClrBits(InstancePtr, RegOffset, BitMask)
	This macro clears the bitmask in the register. More...

#define	XNandPsu_ReadModifyWrite(InstancePtr, RegOffset, Mask, Value)
	This macro clears and updates the bitmask in the register. More...

#define	XNandPsu_IntrSigEnable(InstancePtr, Mask)
	This macro enables bitmask in Interrupt Signal Enable register. More...

#define	XNandPsu_IntrSigClear(InstancePtr, Mask)
	This macro clears bitmask in Interrupt Signal Enable register. More...

#define	XNandPsu_IntrStsEnable(InstancePtr, Mask)
	This macro enables bitmask in Interrupt Status Enable register. More...

#define	IS_ONFI(Buff)
	This macro checks for the ONFI ID. More...

#define	XNANDPSU_BLOCK_GOOD 0x0U
	Block is good. More...

#define	XNANDPSU_BLOCK_BAD 0x1U
	Block is bad. More...

#define	XNANDPSU_BLOCK_RESERVED 0x2U
	Reserved block. More...

#define	XNANDPSU_BLOCK_FACTORY_BAD 0x3U
	Factory marked bad block. More...

#define	XNANDPSU_FLASH_BLOCK_GOOD 0x3U
	Block is good. More...

#define	XNANDPSU_FLASH_BLOCK_BAD 0x2U
	Block is bad. More...

#define	XNANDPSU_FLASH_BLOCK_RESERVED 0x1U
	Reserved block. More...

#define	XNANDPSU_FLASH_BLOCK_FAC_BAD 0x0U
	Factory marked bad block. More...

#define	XNANDPSU_BBT_SCAN_2ND_PAGE 0x00000001U
	Scan the second page for bad block information. More...

#define	XNANDPSU_BBT_DESC_PAGE_OFFSET 0U
	Page offset of Bad Block Table Desc. More...

#define	XNANDPSU_BBT_DESC_SIG_OFFSET 8U
	Bad Block Table signature offset. More...

#define	XNANDPSU_BBT_DESC_VER_OFFSET 12U
	Bad block Table version offset. More...

#define	XNANDPSU_NO_OOB_BBT_DESC_SIG_OFFSET 0U
	Bad Block Table signature offset in page memory. More...

#define	XNANDPSU_NO_OOB_BBT_DESC_VER_OFFSET 4U
	Bad block Table version offset in page memory. More...

#define	XNANDPSU_BBT_DESC_SIG_LEN 4U
	Bad block Table signature length. More...

#define	XNANDPSU_BBT_DESC_MAX_BLOCKS 64U
	Bad block Table max blocks. More...

#define	XNANDPSU_BBT_BLOCK_SHIFT 2U
	Block shift value for a block in BBT. More...

#define	XNANDPSU_BBT_ENTRY_NUM_BLOCKS 4U
	Num of blocks in one BBT entry. More...

#define	XNANDPSU_BB_PTRN_OFF_SML_PAGE 5U
	Bad block pattern offset in a page. More...

#define	XNANDPSU_BB_PTRN_LEN_SML_PAGE 1U
	Bad block pattern length. More...

#define	XNANDPSU_BB_PTRN_OFF_LARGE_PAGE 0U
	Bad block pattern offset in a large page. More...

#define	XNANDPSU_BB_PTRN_LEN_LARGE_PAGE 2U
	Bad block pattern length. More...

#define	XNANDPSU_BB_PATTERN 0xFFU
	Bad block pattern to search in a page. More...

#define	XNANDPSU_BLOCK_TYPE_MASK 0x03U
	Block type mask. More...

#define	XNANDPSU_BLOCK_SHIFT_MASK 0x06U
	Block shift mask for a Bad Block Table entry byte. More...

#define	XNandPsu_BbtBlockShift(Block) (u8)(((Block) * 2U) & XNANDPSU_BLOCK_SHIFT_MASK)
	This macro returns the Block shift value corresponding to a Block. More...

#define	XNANDPSU_PKT_OFFSET 0x00U
	Packet Register. More...

#define	XNANDPSU_MEM_ADDR1_OFFSET 0x04U
	Memory Address Register 1. More...

#define	XNANDPSU_MEM_ADDR2_OFFSET 0x08U
	Memory Address Register 2. More...

#define	XNANDPSU_CMD_OFFSET 0x0CU
	Command Register. More...

#define	XNANDPSU_PROG_OFFSET 0x10U
	Program Register. More...

#define	XNANDPSU_INTR_STS_EN_OFFSET 0x14U
	Interrupt Status Enable Register. More...

#define	XNANDPSU_INTR_SIG_EN_OFFSET 0x18U
	Interrupt Signal Enable Register. More...

#define	XNANDPSU_INTR_STS_OFFSET 0x1CU
	Interrupt Status Register. More...

#define	XNANDPSU_READY_BUSY_OFFSET 0x20U
	Ready/Busy status Register. More...

#define	XNANDPSU_FLASH_STS_OFFSET 0x28U
	Flash Status Register. More...

#define	XNANDPSU_TIMING_OFFSET 0x2CU
	Timing Register. More...

#define	XNANDPSU_BUF_DATA_PORT_OFFSET 0x30U
	Buffer Data Port Register. More...

#define	XNANDPSU_ECC_OFFSET 0x34U
	ECC Register. More...

#define	XNANDPSU_ECC_ERR_CNT_OFFSET 0x38U
	ECC Error Count Register. More...

#define	XNANDPSU_ECC_SPR_CMD_OFFSET 0x3CU
	ECC Spare Command Register. More...

#define	XNANDPSU_ECC_CNT_1BIT_OFFSET 0x40U
	Error Count 1bit Register. More...

#define	XNANDPSU_ECC_CNT_2BIT_OFFSET 0x44U
	Error Count 2bit Register. More...

#define	XNANDPSU_ECC_CNT_3BIT_OFFSET 0x48U
	Error Count 3bit Register. More...

#define	XNANDPSU_ECC_CNT_4BIT_OFFSET 0x4CU
	Error Count 4bit Register. More...

#define	XNANDPSU_CPU_REL_OFFSET 0x58U
	CPU Release Register. More...

#define	XNANDPSU_ECC_CNT_5BIT_OFFSET 0x5CU
	Error Count 5bit Register. More...

#define	XNANDPSU_ECC_CNT_6BIT_OFFSET 0x60U
	Error Count 6bit Register. More...

#define	XNANDPSU_ECC_CNT_7BIT_OFFSET 0x64U
	Error Count 7bit Register. More...

#define	XNANDPSU_ECC_CNT_8BIT_OFFSET 0x68U
	Error Count 8bit Register. More...

#define	XNANDPSU_DATA_INTF_OFFSET 0x6CU
	Data Interface Register. More...

#define	XNANDPSU_DMA_SYS_ADDR0_OFFSET 0x50U
	DMA System Address 0 Register. More...

#define	XNANDPSU_DMA_SYS_ADDR1_OFFSET 0x24U
	DMA System Address 1 Register. More...

#define	XNANDPSU_DMA_BUF_BND_OFFSET 0x54U
	DMA Buffer Boundary Register. More...

#define	XNANDPSU_SLV_DMA_CONF_OFFSET 0x80U
	Slave DMA Configuration Register. More...

#define	XNandPsu_ReadReg(BaseAddress, RegOffset) Xil_In32((BaseAddress) + (RegOffset))
	This macro reads the given register. More...

#define	XNandPsu_WriteReg(BaseAddress, RegOffset, Data) Xil_Out32(((BaseAddress) + (RegOffset)), (Data))
	This macro writes the given register. More...

#define	ONFI_CMD_RD1 0x00U
	Read (1st cycle) More...

#define	ONFI_CMD_RD2 0x30U
	Read (2nd cycle) More...

#define	ONFI_CMD_CHNG_RD_COL1 0x05U
	Change Read Column (1st cycle) More...

#define	ONFI_CMD_CHNG_RD_COL2 0xE0U
	Change Read Column (2nd cycle) More...

#define	ONFI_CMD_BLK_ERASE1 0x60U
	Block Erase (1st cycle) More...

#define	ONFI_CMD_BLK_ERASE2 0xD0U
	Block Erase (2nd cycle) More...

#define	ONFI_CMD_RD_STS 0x70U
	Read Status. More...

#define	ONFI_CMD_PG_PROG1 0x80U
	Page Program(1st cycle) More...

#define	ONFI_CMD_PG_PROG2 0x10U
	Page Program(2nd cycle) More...

#define	ONFI_CMD_CHNG_WR_COL 0x85U
	Change Write Column. More...

#define	ONFI_CMD_RD_ID 0x90U
	Read ID. More...

#define	ONFI_CMD_RD_PRM_PG 0xECU
	Read Parameter Page. More...

#define	ONFI_CMD_RST 0xFFU
	Reset. More...

#define	ONFI_CMD_MUL_RD1 0x00U
	Multiplane Read (1st cycle) More...

#define	ONFI_CMD_MUL_RD2 0x32U
	Multiplane Read (2nd cycle) More...

#define	ONFI_CMD_CPBK_RD1 0x00U
	Copyback Read (1st cycle) More...

#define	ONFI_CMD_CPBK_RD2 0x35U
	Copyback Read (2nd cycle) More...

#define	ONFI_CMD_CHNG_RD_COL_ENHCD1 0x06U
	Change Read Column Enhanced (1st cycle) More...

#define	ONFI_CMD_CHNG_RD_COL_ENHCD2 0xE0U
	Change Read Column Enhanced (2nd cycle) More...

#define	ONFI_CMD_RD_CACHE_RND1 0x00U
	Read Cache Random (1st cycle) More...

#define	ONFI_CMD_RD_CACHE_RND2 0x31U
	Read Cache Random (2nd cycle) More...

#define	ONFI_CMD_RD_CACHE_SEQ 0x31U
	Read Cache Sequential. More...

#define	ONFI_CMD_RD_CACHE_END 0x3FU
	Read Cache End. More...

#define	ONFI_CMD_MUL_BLK_ERASE1 0x60U
	Multiplane Block Erase (1st cycle) More...

#define	ONFI_CMD_MUL_BLK_ERASE2 0xD1U
	Multiplane Block Erase (2nd cycle) More...

#define	ONFI_CMD_RD_STS_ENHCD 0x78U
	Read Status Enhanced. More...

#define	ONFI_CMD_BLK_ERASE_INTRLVD2 0xD1U
	Block Erase Interleaved (2nd cycle) More...

#define	ONFI_CMD_MUL_PG_PROG1 0x80U
	Multiplane Page Program (1st cycle) More...

#define	ONFI_CMD_MUL_PG_PROG2 0x11U
	Multiplane Page Program (2nd cycle) More...

#define	ONFI_CMD_PG_CACHE_PROG1 0x80U
	Page Cache Program (1st cycle) More...

#define	ONFI_CMD_PG_CACHE_PROG2 0x15U
	Page Cache Program (2nd cycle) More...

#define	ONFI_CMD_CPBK_PROG1 0x85U
	Copyback Program (1st cycle) More...

#define	ONFI_CMD_CPBK_PROG2 0x10U
	Copyback Program (2nd cycle) More...

#define	ONFI_CMD_MUL_CPBK_PROG1 0x85U
	Multiplane Copyback Program (1st cycle) More...

#define	ONFI_CMD_MUL_CPBK_PROG2 0x10U
	Multiplane Copyback Program (2nd cycle) More...

#define	ONFI_CMD_SMALL_DATA_MV1 0x85U
	Small Data Move (1st cycle) More...

#define	ONFI_CMD_SMALL_DATA_MV2 0x10U
	Small Data Move (2nd cycle) More...

#define	ONFI_CMD_CHNG_ROW_ADDR 0x85U
	Change Row Address. More...

#define	ONFI_CMD_VOL_SEL 0xE1U
	Volume Select. More...

#define	ONFI_CMD_ODT_CONF 0xE2U
	ODT Configure. More...

#define	ONFI_CMD_RD_UNIQID 0xEDU
	Read Unique ID. More...

#define	ONFI_CMD_GET_FEATURES 0xEEU
	Get Features. More...

#define	ONFI_CMD_SET_FEATURES 0xEFU
	Set Features. More...

#define	ONFI_CMD_LUN_GET_FEATURES 0xD4U
	LUN Get Features. More...

#define	ONFI_CMD_LUN_SET_FEATURES 0xD5U
	LUN Set Features. More...

#define	ONFI_CMD_RST_LUN 0xFAU
	Reset LUN. More...

#define	ONFI_CMD_SYN_RST 0xFCU
	Synchronous Reset. More...

#define	ONFI_STS_FAIL 0x01U
	FAIL. More...

#define	ONFI_STS_FAILC 0x02U
	FAILC. More...

#define	ONFI_STS_CSP 0x08U
	CSP. More...

#define	ONFI_STS_VSP 0x10U
	VSP. More...

#define	ONFI_STS_ARDY 0x20U
	ARDY. More...

#define	ONFI_STS_RDY 0x40U
	RDY. More...

#define	ONFI_STS_WP 0x80U
	WP_n. More...

#define	ONFI_CRC_LEN 254U
	ONFI CRC Buf Length. More...

#define	ONFI_PRM_PG_LEN 256U
	Parameter Page Length. More...

#define	ONFI_MND_PRM_PGS 3U
	Number of mandatory parameter pages. More...

#define	ONFI_SIG_LEN 4U
	Signature Length. More...

#define	ONFI_CMD_INVALID 0x00U
	Invalid Command. More...

#define	ONFI_READ_ID_LEN 4U
	ONFI ID length. More...

#define	ONFI_READ_ID_ADDR 0x20U
	ONFI Read ID Address. More...

#define	ONFI_READ_ID_ADDR_CYCLES 1U
	ONFI Read ID Address cycles. More...

#define	ONFI_PRM_PG_ADDR_CYCLES 1U
	ONFI Read Parameter page address cycles. More...

Enumerations
enum	XNandPsu_DataInterface { XNANDPSU_SDR = 0U, XNANDPSU_NVDDR }
	The XNandPsu_DataInterface enum contains flash operating mode. More...

enum	XNandPsu_TimingMode
	XNandPsu_TimingMode enum contains timing modes. More...

enum	XNandPsu_SWMode { XNANDPSU_POLLING = 0, XNANDPSU_INTERRUPT }
	The XNandPsu_SWMode enum contains the driver operating mode. More...

enum	XNandPsu_DmaMode { XNANDPSU_PIO = 0, XNANDPSU_SDMA, XNANDPSU_MDMA }
	The XNandPsu_DmaMode enum contains the controller MDMA mode. More...

enum	XNandPsu_EccMode
	The XNandPsu_EccMode enum contains ECC functionality. More...

enum	OnfiCommandList { READ = 0, MULTIPLANE_READ, COPYBACK_READ, CHANGE_READ_COLUMN, CHANGE_READ_COLUMN_ENHANCED, READ_CACHE_RANDOM, READ_CACHE_SEQUENTIAL, READ_CACHE_END, BLOCK_ERASE, MULTIPLANE_BLOCK_ERASE, READ_STATUS, READ_STATUS_ENHANCED, PAGE_PROGRAM, MULTIPLANE_PAGE_PROGRAM, PAGE_CACHE_PROGRAM, COPYBACK_PROGRAM, MULTIPLANE_COPYBACK_PROGRAM, SMALL_DATA_MOVE, CHANGE_WRITE_COLUMN, CHANGE_ROW_ADDR, READ_ID, VOLUME_SELECT, ODT_CONFIGURE, READ_PARAM_PAGE, READ_UNIQUE_ID, GET_FEATURES, SET_FEATURES, LUN_GET_FEATURES, LUN_SET_FEATURES, RESET_LUN, SYN_RESET, RESET, MAX_CMDS }
	This enum defines the ONFI 3.1 commands. More...

Functions
s32	XNandPsu_CfgInitialize (XNandPsu InstancePtr, XNandPsu_Config ConfigPtr, u32 EffectiveAddr)
	This function initializes a specific XNandPsu instance. More...

void	XNandPsu_EnableDmaMode (XNandPsu *InstancePtr)
	This function enables DMA mode of controller operation. More...

void	XNandPsu_DisableDmaMode (XNandPsu *InstancePtr)
	This function disables DMA mode of driver/controller operation. More...

void	XNandPsu_EnableEccMode (XNandPsu *InstancePtr)
	This function enables ECC mode of driver/controller operation. More...

void	XNandPsu_DisableEccMode (XNandPsu *InstancePtr)
	This function disables ECC mode of driver/controller operation. More...

s32	XNandPsu_Write (XNandPsu InstancePtr, u64 Offset, u64 Length, u8 SrcBuf)
	This function writes to the flash. More...

s32	XNandPsu_Read (XNandPsu InstancePtr, u64 Offset, u64 Length, u8 DestBuf)
	This function reads from the flash. More...

s32	XNandPsu_Erase (XNandPsu *InstancePtr, u64 Offset, u64 Length)
	This function erases the flash. More...

s32	XNandPsu_WriteSpareBytes (XNandPsu InstancePtr, u32 Page, u8 Buf)
	This function sends ONFI Program Page command to flash. More...

s32	XNandPsu_ReadSpareBytes (XNandPsu InstancePtr, u32 Page, u8 Buf)
	This function reads spare bytes from flash. More...

s32	XNandPsu_EraseBlock (XNandPsu *InstancePtr, u32 Target, u32 Block)
	This function sends ONFI block erase command to the flash. More...

s32	XNandPsu_GetFeature (XNandPsu InstancePtr, u32 Target, u8 Feature, u8 Buf)
	This function sends ONFI Get Feature command to flash. More...

s32	XNandPsu_SetFeature (XNandPsu InstancePtr, u32 Target, u8 Feature, u8 Buf)
	This function sends ONFI Set Feature command to flash. More...

s32	XNandPsu_ChangeTimingMode (XNandPsu *InstancePtr, XNandPsu_DataInterface NewIntf, XNandPsu_TimingMode NewMode)
	This function changes the data interface and timing mode. More...

void	XNandPsu_Prepare_Cmd (XNandPsu *InstancePtr, u8 Cmd1, u8 Cmd2, u8 EccState, u8 DmaMode, u8 AddrCycles)
	This function prepares command to be written into command register. More...

s32	XNandPsu_ScanBbt (XNandPsu *InstancePtr)
	This function reads the Bad Block Table(BBT) if present in flash. More...

s32	XNandPsu_MarkBlockBad (XNandPsu *InstancePtr, u32 Block)
	This function marks a block as bad in the RAM based Bad Block Table(BBT). More...

XNandPsu_Config *	XNandPsu_LookupConfig (u16 DevID)
	Looks up the controller configuration based on the unique controller ID. More...

void	XNandPsu_InitBbtDesc (XNandPsu *InstancePtr)
	This function initializes the Bad Block Table(BBT) descriptors with a predefined pattern for searching Bad Block Table(BBT) in flash. More...

s32	XNandPsu_IsBlockBad (XNandPsu *InstancePtr, u32 Block)
	This function checks whether a block is bad or not. More...

u32	XNandPsu_OnfiParamPageCrc (u8 *ParamBuf, u32 StartOff, u32 Length)
	This function calculates ONFI parameter page CRC. More...

Variables
XNandPsu_Config	XNandPsu_ConfigTable []
	Each XNandPsu device in the system has an entry in this table. More...

XNandPsu_Config	XNandPsu_ConfigTable []
	Each XNandPsu device in the system has an entry in this table. More...

Packet Register bit definitions and masks
#define	XNANDPSU_PKT_PKT_SIZE_MASK 0x000007FFU
	Packet Size. More...

#define	XNANDPSU_PKT_PKT_CNT_MASK 0x00FFF000U
	Packet Count. More...

#define	XNANDPSU_PKT_PKT_CNT_SHIFT 12U
	Packet Count Shift. More...

Memory Address Register 1 bit definitions and masks
#define	XNANDPSU_MEM_ADDR1_COL_ADDR_MASK 0x0000FFFFU
	Column Address Mask. More...

#define	XNANDPSU_MEM_ADDR1_PG_ADDR_MASK 0xFFFF0000U
	Page, Block Address Mask. More...

#define	XNANDPSU_MEM_ADDR1_PG_ADDR_SHIFT 16U
	Page Shift. More...

Memory Address Register 2 bit definitions and masks
#define	XNANDPSU_MEM_ADDR2_MEM_ADDR_MASK 0x000000FFU
	Memory Address. More...

#define	XNANDPSU_MEM_ADDR2_BUS_WIDTH_MASK 0x01000000U
	Bus Width. More...

#define	XNANDPSU_MEM_ADDR2_NFC_BCH_MODE_MASK 0x0E000000U
	BCH Mode Value. More...

#define	XNANDPSU_MEM_ADDR2_MODE_MASK 0x30000000U
	Flash Connection Mode. More...

#define	XNANDPSU_MEM_ADDR2_CHIP_SEL_MASK 0xC0000000U
	Chip Select. More...

#define	XNANDPSU_MEM_ADDR2_CHIP_SEL_SHIFT 30U
	Chip select shift. More...

#define	XNANDPSU_MEM_ADDR2_BUS_WIDTH_SHIFT 24U
	Bus width shift. More...

#define	XNANDPSU_MEM_ADDR2_NFC_BCH_MODE_SHIFT 25U

Command Register bit definitions and masks
#define	XNANDPSU_CMD_CMD1_MASK 0x000000FFU
	1st Cycle Command More...

#define	XNANDPSU_CMD_CMD2_MASK 0x0000FF00U
	2nd Cycle Command More...

#define	XNANDPSU_CMD_PG_SIZE_MASK 0x03800000U
	Page Size. More...

#define	XNANDPSU_CMD_DMA_EN_MASK 0x0C000000U
	DMA Enable Mode. More...

#define	XNANDPSU_CMD_ADDR_CYCLES_MASK 0x70000000U
	Number of Address Cycles. More...

#define	XNANDPSU_CMD_ECC_ON_MASK 0x80000000U
	ECC ON/OFF. More...

#define	XNANDPSU_CMD_CMD2_SHIFT 8U
	2nd Cycle Command Shift More...

#define	XNANDPSU_CMD_PG_SIZE_SHIFT 23U
	Page Size Shift. More...

#define	XNANDPSU_CMD_DMA_EN_SHIFT 26U
	DMA Enable Shift. More...

#define	XNANDPSU_CMD_ADDR_CYCLES_SHIFT 28U
	Number of Address Cycles Shift. More...

#define	XNANDPSU_CMD_ECC_ON_SHIFT 31U
	ECC ON/OFF. More...

Program Register bit definitions and masks
#define	XNANDPSU_PROG_RD_MASK 0x00000001U
	Read. More...

#define	XNANDPSU_PROG_MUL_DIE_MASK 0x00000002U
	Multi Die. More...

#define	XNANDPSU_PROG_BLK_ERASE_MASK 0x00000004U
	Block Erase. More...

#define	XNANDPSU_PROG_RD_STS_MASK 0x00000008U
	Read Status. More...

#define	XNANDPSU_PROG_PG_PROG_MASK 0x00000010U
	Page Program. More...

#define	XNANDPSU_PROG_MUL_DIE_RD_MASK 0x00000020U
	Multi Die Rd. More...

#define	XNANDPSU_PROG_RD_ID_MASK 0x00000040U
	Read ID. More...

#define	XNANDPSU_PROG_RD_PRM_PG_MASK 0x00000080U
	Read Param Page. More...

#define	XNANDPSU_PROG_RST_MASK 0x00000100U
	Reset. More...

#define	XNANDPSU_PROG_GET_FEATURES_MASK 0x00000200U
	Get Features. More...

#define	XNANDPSU_PROG_SET_FEATURES_MASK 0x00000400U
	Set Features. More...

#define	XNANDPSU_PROG_RD_UNQ_ID_MASK 0x00000800U
	Read Unique ID. More...

#define	XNANDPSU_PROG_RD_STS_ENH_MASK 0x00001000U
	Read Status Enhanced. More...

#define	XNANDPSU_PROG_RD_INTRLVD_MASK 0x00002000U
	Read Interleaved. More...

#define	XNANDPSU_PROG_CHNG_RD_COL_ENH_MASK 0x00004000U
	Change Read Column Enhanced. More...

#define	XNANDPSU_PROG_COPY_BACK_INTRLVD_MASK 0x00008000U
	Copy Back Interleaved. More...

#define	XNANDPSU_PROG_RD_CACHE_START_MASK 0x00010000U
	Read Cache Start. More...

#define	XNANDPSU_PROG_RD_CACHE_SEQ_MASK 0x00020000U
	Read Cache Sequential. More...

#define	XNANDPSU_PROG_RD_CACHE_RAND_MASK 0x00040000U
	Read Cache Random. More...

#define	XNANDPSU_PROG_RD_CACHE_END_MASK 0x00080000U
	Read Cache End. More...

#define	XNANDPSU_PROG_SMALL_DATA_MOVE_MASK 0x00100000U
	Small Data Move. More...

#define	XNANDPSU_PROG_CHNG_ROW_ADDR_MASK 0x00200000U
	Change Row Address. More...

#define	XNANDPSU_PROG_CHNG_ROW_ADDR_END_MASK 0x00400000U
	Change Row Address End. More...

#define	XNANDPSU_PROG_RST_LUN_MASK 0x00800000U
	Reset LUN. More...

#define	XNANDPSU_PROG_PGM_PG_CLR_MASK 0x01000000U
	Enhanced Program Page Register Clear. More...

#define	XNANDPSU_PROG_VOL_SEL_MASK 0x02000000U
	Volume Select. More...

#define	XNANDPSU_PROG_ODT_CONF_MASK 0x04000000U
	ODT Configure. More...

Interrupt Status Enable Register bit definitions and masks
#define	XNANDPSU_INTR_STS_EN_BUFF_WR_RDY_STS_EN_MASK 0x00000001U
	Buffer Write Ready Status Enable. More...

#define	XNANDPSU_INTR_STS_EN_BUFF_RD_RDY_STS_EN_MASK 0x00000002U
	Buffer Read Ready Status Enable. More...

#define	XNANDPSU_INTR_STS_EN_TRANS_COMP_STS_EN_MASK 0x00000004U
	Transfer Complete Status Enable. More...

#define	XNANDPSU_INTR_STS_EN_MUL_BIT_ERR_STS_EN_MASK 0x00000008U
	Multi Bit Error Status Enable. More...

#define	XNANDPSU_INTR_STS_EN_ERR_INTR_STS_EN_MASK 0x00000010U
	Single Bit Error Status Enable, BCH Detect Error Status Enable. More...

#define	XNANDPSU_INTR_STS_EN_DMA_INT_STS_EN_MASK 0x00000040U
	DMA Status Enable. More...

#define	XNANDPSU_INTR_STS_EN_ERR_AHB_STS_EN_MASK 0x00000080U
	Error AHB Status Enable. More...

Interrupt Signal Enable Register bit definitions and masks
#define	XNANDPSU_INTR_SIG_EN_BUFF_WR_RDY_STS_EN_MASK 0x00000001U
	Buffer Write Ready Signal Enable. More...

#define	XNANDPSU_INTR_SIG_EN_BUFF_RD_RDY_STS_EN_MASK 0x00000002U
	Buffer Read Ready Signal Enable. More...

#define	XNANDPSU_INTR_SIG_EN_TRANS_COMP_STS_EN_MASK 0x00000004U
	Transfer Complete Signal Enable. More...

#define	XNANDPSU_INTR_SIG_EN_MUL_BIT_ERR_STS_EN_MASK 0x00000008U
	Multi Bit Error Signal Enable. More...

#define	XNANDPSU_INTR_SIG_EN_ERR_INTR_STS_EN_MASK 0x00000010U
	Single Bit Error Signal Enable, BCH Detect Error Signal Enable. More...

#define	XNANDPSU_INTR_SIG_EN_DMA_INT_STS_EN_MASK 0x00000040U
	DMA Signal Enable. More...

#define	XNANDPSU_INTR_SIG_EN_ERR_AHB_STS_EN_MASK 0x00000080U
	Error AHB Signal Enable. More...

Interrupt Status Register bit definitions and masks
#define	XNANDPSU_INTR_STS_BUFF_WR_RDY_STS_EN_MASK 0x00000001U
	Buffer Write Ready. More...

#define	XNANDPSU_INTR_STS_BUFF_RD_RDY_STS_EN_MASK 0x00000002U
	Buffer Read Ready. More...

#define	XNANDPSU_INTR_STS_TRANS_COMP_STS_EN_MASK 0x00000004U
	Transfer Complete. More...

#define	XNANDPSU_INTR_STS_MUL_BIT_ERR_STS_EN_MASK 0x00000008U
	Multi Bit Error. More...

#define	XNANDPSU_INTR_STS_ERR_INTR_STS_EN_MASK 0x00000010U
	Single Bit Error, BCH Detect Error. More...

#define	XNANDPSU_INTR_STS_DMA_INT_STS_EN_MASK 0x00000040U
	DMA Interrupt. More...

#define	XNANDPSU_INTR_STS_ERR_AHB_STS_EN_MASK 0x00000080U
	Error AHB. More...

Interrupt bit definitions and masks
#define	XNANDPSU_INTR_BUFF_WR_RDY_STS_EN_MASK 0x00000001U
	Buffer Write Ready Status Enable. More...

#define	XNANDPSU_INTR_BUFF_RD_RDY_STS_EN_MASK 0x00000002U
	Buffer Read Ready Status Enable. More...

#define	XNANDPSU_INTR_TRANS_COMP_STS_EN_MASK 0x00000004U
	Transfer Complete Status Enable. More...

#define	XNANDPSU_INTR_MUL_BIT_ERR_STS_EN_MASK 0x00000008U
	Multi Bit Error Status Enable. More...

#define	XNANDPSU_INTR_ERR_INTR_STS_EN_MASK 0x00000010U
	Single Bit Error Status Enable, BCH Detect Error Status Enable. More...

#define	XNANDPSU_INTR_DMA_INT_STS_EN_MASK 0x00000040U
	DMA Status Enable. More...

#define	XNANDPSU_INTR_ERR_AHB_STS_EN_MASK 0x00000080U
	Error AHB Status Enable. More...

ID2 Register bit definitions and masks
#define	XNANDPSU_ID2_DEVICE_ID2_MASK 0x000000FFU
	MSB Device ID. More...

Flash Status Register bit definitions and masks
#define	XNANDPSU_FLASH_STS_FLASH_STS_MASK 0x0000FFFFU
	Flash Status Value. More...

Timing Register bit definitions and masks
#define	XNANDPSU_TIMING_TCCS_TIME_MASK 0x00000003U
	Change column setup time. More...

#define	XNANDPSU_TIMING_SLOW_FAST_TCAD_MASK 0x00000004U
	Slow/Fast device. More...

#define	XNANDPSU_TIMING_DQS_BUFF_SEL_MASK 0x00000078U
	Write/Read data transaction value. More...

#define	XNANDPSU_TIMING_TADL_TIME_MASK 0x00007F80U
	Address latch enable to Data loading time. More...

ECC Register bit definitions and masks
#define	XNANDPSU_ECC_ADDR_MASK 0x0000FFFFU
	ECC address. More...

#define	XNANDPSU_ECC_SIZE_MASK 0x01FF0000U
	ECC size. More...

#define	XNANDPSU_ECC_HAMMING_BCH_MASK 0x02000000U
	Hamming/BCH support. More...

ECC Error Count Register bit definitions and masks
#define	XNANDPSU_ECC_ERR_CNT_PKT_BND_ERR_CNT_MASK 0x000000FFU
	Packet bound error count. More...

#define	XNANDPSU_ECC_ERR_CNT_PG_BND_ERR_CNT_MASK 0x0000FF00U
	Page bound error count. More...

ECC Spare Command Register bit definitions and masks
#define	XNANDPSU_ECC_SPR_CMD_SPR_CMD_MASK 0x000000FFU
	ECC spare command. More...

#define	XNANDPSU_ECC_SPR_CMD_ECC_ADDR_CYCLES_MASK 0x70000000U
	Number of ECC/ spare address cycles. More...

Data Interface Register bit definitions and masks
#define	XNANDPSU_DATA_INTF_SDR_MASK 0x00000007U
	SDR mode. More...

#define	XNANDPSU_DATA_INTF_NVDDR_MASK 0x00000038U
	NVDDR mode. More...

#define	XNANDPSU_DATA_INTF_NVDDR2_MASK 0x000001C0U
	NVDDR2 mode. More...

#define	XNANDPSU_DATA_INTF_DATA_INTF_MASK 0x00000600U
	Data Interface. More...

#define	XNANDPSU_DATA_INTF_NVDDR_SHIFT 3U
	NVDDR mode shift. More...

#define	XNANDPSU_DATA_INTF_DATA_INTF_SHIFT 9U
	Data Interface Shift. More...

DMA Buffer Boundary Register bit definitions and masks
#define	XNANDPSU_DMA_BUF_BND_BND_MASK 0x00000007U
	DMA buffer boundary. More...

#define	XNANDPSU_DMA_BUF_BND_4K 0x0U

#define	XNANDPSU_DMA_BUF_BND_8K 0x1U

#define	XNANDPSU_DMA_BUF_BND_16K 0x2U

#define	XNANDPSU_DMA_BUF_BND_32K 0x3U

#define	XNANDPSU_DMA_BUF_BND_64K 0x4U

#define	XNANDPSU_DMA_BUF_BND_128K 0x5U

#define	XNANDPSU_DMA_BUF_BND_256K 0x6U

#define	XNANDPSU_DMA_BUF_BND_512K 0x7U

Slave DMA Configuration Register bit definitions and masks
#define	XNANDPSU_SLV_DMA_CONF_SDMA_TX_RX_MASK 0x00000001U
	Slave DMA Transfer Direction. More...

#define	XNANDPSU_SLV_DMA_CONF_DMA_TRANS_CNT_MASK 0x001FFFFEU
	Slave DMA Transfer Count. More...

#define	XNANDPSU_SLV_DMA_CONF_DMA_BURST_SIZE_MASK 0x00E00000U
	Slave DMA Burst Size. More...

#define	XNANDPSU_SLV_DMA_CONF_DMA_TMOUT_CNT_VAL_MASK 0x0F000000U
	DMA Timeout Counter Value. More...

#define	XNANDPSU_SLV_DMA_CONF_SDMA_EN_MASK 0x10000000U
	Slave DMA Enable. More...

Macro Definition Documentation

#define IS_ONFI ( Buff )

Value:

((Buff)[0] == (u8)'O') && ((Buff)[1] == (u8)'N') && \

((Buff)[2] == (u8)'F') && ((Buff)[3] == (u8)'I')

This macro checks for the ONFI ID.

Parameters

Buff	is the buffer holding ONFI ID

Note: none.

#define ONFI_CMD_BLK_ERASE1 0x60U

Block Erase (1st cycle)

Referenced by XNandPsu_EraseBlock().

#define ONFI_CMD_BLK_ERASE2 0xD0U

Block Erase (2nd cycle)

Referenced by XNandPsu_EraseBlock().

#define ONFI_CMD_BLK_ERASE_INTRLVD2 0xD1U

Block Erase Interleaved (2nd cycle)

#define ONFI_CMD_CHNG_RD_COL1 0x05U

Change Read Column (1st cycle)

#define ONFI_CMD_CHNG_RD_COL2 0xE0U

Change Read Column (2nd cycle)

#define ONFI_CMD_CHNG_RD_COL_ENHCD1 0x06U

Change Read Column Enhanced (1st cycle)

#define ONFI_CMD_CHNG_RD_COL_ENHCD2 0xE0U

Change Read Column Enhanced (2nd cycle)

#define ONFI_CMD_CHNG_ROW_ADDR 0x85U

Change Row Address.

#define ONFI_CMD_CHNG_WR_COL 0x85U

Change Write Column.

#define ONFI_CMD_CPBK_PROG1 0x85U

Copyback Program (1st cycle)

#define ONFI_CMD_CPBK_PROG2 0x10U

Copyback Program (2nd cycle)

#define ONFI_CMD_CPBK_RD1 0x00U

Copyback Read (1st cycle)

#define ONFI_CMD_CPBK_RD2 0x35U

Copyback Read (2nd cycle)

#define ONFI_CMD_GET_FEATURES 0xEEU

Get Features.

Referenced by XNandPsu_GetFeature().

#define ONFI_CMD_INVALID 0x00U

Invalid Command.

Referenced by XNandPsu_GetFeature(), and XNandPsu_SetFeature().

#define ONFI_CMD_LUN_GET_FEATURES 0xD4U

LUN Get Features.

#define ONFI_CMD_LUN_SET_FEATURES 0xD5U

LUN Set Features.

#define ONFI_CMD_MUL_BLK_ERASE1 0x60U

Multiplane Block Erase (1st cycle)

#define ONFI_CMD_MUL_BLK_ERASE2 0xD1U

Multiplane Block Erase (2nd cycle)

#define ONFI_CMD_MUL_CPBK_PROG1 0x85U

Multiplane Copyback Program (1st cycle)

#define ONFI_CMD_MUL_CPBK_PROG2 0x10U

Multiplane Copyback Program (2nd cycle)

#define ONFI_CMD_MUL_PG_PROG1 0x80U

Multiplane Page Program (1st cycle)

#define ONFI_CMD_MUL_PG_PROG2 0x11U

Multiplane Page Program (2nd cycle)

#define ONFI_CMD_MUL_RD1 0x00U

Multiplane Read (1st cycle)

#define ONFI_CMD_MUL_RD2 0x32U

Multiplane Read (2nd cycle)

#define ONFI_CMD_ODT_CONF 0xE2U

ODT Configure.

#define ONFI_CMD_PG_CACHE_PROG1 0x80U

Page Cache Program (1st cycle)

#define ONFI_CMD_PG_CACHE_PROG2 0x15U

Page Cache Program (2nd cycle)

#define ONFI_CMD_PG_PROG1 0x80U

Page Program(1st cycle)

Referenced by XNandPsu_WriteSpareBytes().

#define ONFI_CMD_PG_PROG2 0x10U

Page Program(2nd cycle)

Referenced by XNandPsu_WriteSpareBytes().

#define ONFI_CMD_RD1 0x00U

Read (1st cycle)

Referenced by XNandPsu_ReadSpareBytes().

#define ONFI_CMD_RD2 0x30U

Read (2nd cycle)

Referenced by XNandPsu_ReadSpareBytes().

#define ONFI_CMD_RD_CACHE_END 0x3FU

Read Cache End.

#define ONFI_CMD_RD_CACHE_RND1 0x00U

Read Cache Random (1st cycle)

#define ONFI_CMD_RD_CACHE_RND2 0x31U

Read Cache Random (2nd cycle)

#define ONFI_CMD_RD_CACHE_SEQ 0x31U

Read Cache Sequential.

#define ONFI_CMD_RD_ID 0x90U

Read ID.

#define ONFI_CMD_RD_PRM_PG 0xECU

Read Parameter Page.

#define ONFI_CMD_RD_STS 0x70U

Read Status.

#define ONFI_CMD_RD_STS_ENHCD 0x78U

Read Status Enhanced.

#define ONFI_CMD_RD_UNIQID 0xEDU

Read Unique ID.

#define ONFI_CMD_RST 0xFFU

Reset.

#define ONFI_CMD_RST_LUN 0xFAU

Reset LUN.

#define ONFI_CMD_SET_FEATURES 0xEFU

Set Features.

Referenced by XNandPsu_SetFeature().

#define ONFI_CMD_SMALL_DATA_MV1 0x85U

Small Data Move (1st cycle)

#define ONFI_CMD_SMALL_DATA_MV2 0x10U

Small Data Move (2nd cycle)

#define ONFI_CMD_SYN_RST 0xFCU

Synchronous Reset.

#define ONFI_CMD_VOL_SEL 0xE1U

Volume Select.

#define ONFI_CRC_LEN 254U

ONFI CRC Buf Length.

#define ONFI_MND_PRM_PGS 3U

Number of mandatory parameter pages.

#define ONFI_PRM_PG_ADDR_CYCLES 1U

ONFI Read Parameter page address cycles.

#define ONFI_PRM_PG_LEN 256U

Parameter Page Length.

#define ONFI_READ_ID_ADDR 0x20U

ONFI Read ID Address.

#define ONFI_READ_ID_ADDR_CYCLES 1U

ONFI Read ID Address cycles.

#define ONFI_READ_ID_LEN 4U

ONFI ID length.

#define ONFI_SIG_LEN 4U

Signature Length.

#define ONFI_STS_ARDY 0x20U

ARDY.

#define ONFI_STS_CSP 0x08U

CSP.

#define ONFI_STS_FAIL 0x01U

FAIL.

#define ONFI_STS_FAILC 0x02U

FAILC.

#define ONFI_STS_RDY 0x40U

RDY.

#define ONFI_STS_VSP 0x10U

VSP.

#define ONFI_STS_WP 0x80U

WP_n.

#define XNANDPSU_BB_PATTERN 0xFFU

Bad block pattern to search in a page.

Referenced by XNandPsu_InitBbtDesc().

#define XNANDPSU_BB_PTRN_LEN_LARGE_PAGE 2U

Bad block pattern length.

Referenced by XNandPsu_InitBbtDesc().

#define XNANDPSU_BB_PTRN_LEN_SML_PAGE 1U

Bad block pattern length.

Referenced by XNandPsu_InitBbtDesc().

#define XNANDPSU_BB_PTRN_OFF_LARGE_PAGE 0U

Bad block pattern offset in a large page.

Referenced by XNandPsu_InitBbtDesc().

#define XNANDPSU_BB_PTRN_OFF_SML_PAGE 5U

Bad block pattern offset in a page.

Referenced by XNandPsu_InitBbtDesc().

#define XNANDPSU_BBT_BLOCK_SHIFT 2U

Block shift value for a block in BBT.

Referenced by XNandPsu_IsBlockBad(), XNandPsu_MarkBlockBad(), and XNandPsu_ScanBbt().

#define XNANDPSU_BBT_DESC_MAX_BLOCKS 64U

Bad block Table max blocks.

Referenced by XNandPsu_InitBbtDesc().

#define XNANDPSU_BBT_DESC_PAGE_OFFSET 0U

Page offset of Bad Block Table Desc.

Referenced by XNandPsu_InitBbtDesc().

#define XNANDPSU_BBT_DESC_SIG_LEN 4U

Bad block Table signature length.

Referenced by XNandPsu_InitBbtDesc().

#define XNANDPSU_BBT_DESC_SIG_OFFSET 8U

Bad Block Table signature offset.

Referenced by XNandPsu_InitBbtDesc().

#define XNANDPSU_BBT_DESC_VER_OFFSET 12U

Bad block Table version offset.

Referenced by XNandPsu_InitBbtDesc().

#define XNANDPSU_BBT_ENTRY_NUM_BLOCKS 4U

Num of blocks in one BBT entry.

#define XNANDPSU_BBT_SCAN_2ND_PAGE 0x00000001U

Scan the second page for bad block information.

Referenced by XNandPsu_InitBbtDesc().

#define XNandPsu_BbtBlockShift ( Block ) (u8)(((Block) * 2U) & XNANDPSU_BLOCK_SHIFT_MASK)

This macro returns the Block shift value corresponding to a Block.

Parameters

Block is the block number.

Returns: Block shift value

Note: None.

Referenced by XNandPsu_IsBlockBad(), and XNandPsu_MarkBlockBad().

#define XNANDPSU_BCH 0x2U

BCH Flash.

#define XNANDPSU_BLOCK_BAD 0x1U

Block is bad.

Referenced by XNandPsu_MarkBlockBad().

#define XNANDPSU_BLOCK_FACTORY_BAD 0x3U

Factory marked bad block.

#define XNANDPSU_BLOCK_GOOD 0x0U

Block is good.

Referenced by XNandPsu_IsBlockBad().

#define XNANDPSU_BLOCK_RESERVED 0x2U

Reserved block.

Referenced by XNandPsu_IsBlockBad().

#define XNANDPSU_BLOCK_SHIFT_MASK 0x06U

Block shift mask for a Bad Block Table entry byte.

#define XNANDPSU_BLOCK_TYPE_MASK 0x03U

Block type mask.

Referenced by XNandPsu_IsBlockBad(), and XNandPsu_MarkBlockBad().

#define XNANDPSU_BUF_DATA_PORT_OFFSET 0x30U

Buffer Data Port Register.

#define XNandPsu_ClrBits	(	InstancePtr,
		RegOffset,
		BitMask
	)

Value:

XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,            \
                          (RegOffset),                                          \
                          ((u32)(XNandPsu_ReadReg((InstancePtr)->Config.BaseAddress,    \
                                          (RegOffset)) & ~(BitMask))))

This macro clears the bitmask in the register.

Parameters

InstancePtr	is a pointer to the XNandPsu instance of the controller.
RegOffset	is the register offset.
BitMask	is the bitmask.

Note: C-style signature: void XNandPsu_ClrBits(XNandPsu *InstancePtr, u32 RegOffset, u32 BitMask)

#define XNANDPSU_CMD_ADDR_CYCLES_MASK 0x70000000U

Number of Address Cycles.

#define XNANDPSU_CMD_ADDR_CYCLES_SHIFT 28U

Number of Address Cycles Shift.

Referenced by XNandPsu_Prepare_Cmd().

#define XNANDPSU_CMD_CMD1_MASK 0x000000FFU

1st Cycle Command

#define XNANDPSU_CMD_CMD2_MASK 0x0000FF00U

2nd Cycle Command

Referenced by XNandPsu_Prepare_Cmd().

#define XNANDPSU_CMD_CMD2_SHIFT 8U

2nd Cycle Command Shift

Referenced by XNandPsu_Prepare_Cmd().

#define XNANDPSU_CMD_DMA_EN_MASK 0x0C000000U

DMA Enable Mode.

#define XNANDPSU_CMD_DMA_EN_SHIFT 26U

DMA Enable Shift.

Referenced by XNandPsu_Prepare_Cmd().

#define XNANDPSU_CMD_ECC_ON_MASK 0x80000000U

ECC ON/OFF.

#define XNANDPSU_CMD_ECC_ON_SHIFT 31U

ECC ON/OFF.

Referenced by XNandPsu_Prepare_Cmd().

#define XNANDPSU_CMD_OFFSET 0x0CU

Command Register.

Referenced by XNandPsu_Prepare_Cmd().

#define XNANDPSU_CMD_PG_SIZE_MASK 0x03800000U

Page Size.

#define XNANDPSU_CMD_PG_SIZE_SHIFT 23U

Page Size Shift.

#define XNANDPSU_CPU_REL_OFFSET 0x58U

CPU Release Register.

#define XNANDPSU_DATA_INTF_DATA_INTF_MASK 0x00000600U

Data Interface.

#define XNANDPSU_DATA_INTF_DATA_INTF_SHIFT 9U

Data Interface Shift.

Referenced by XNandPsu_ChangeTimingMode().

#define XNANDPSU_DATA_INTF_NVDDR2_MASK 0x000001C0U

NVDDR2 mode.

#define XNANDPSU_DATA_INTF_NVDDR_MASK 0x00000038U

NVDDR mode.

#define XNANDPSU_DATA_INTF_NVDDR_SHIFT 3U

NVDDR mode shift.

#define XNANDPSU_DATA_INTF_OFFSET 0x6CU

Data Interface Register.

Referenced by XNandPsu_ChangeTimingMode().

#define XNANDPSU_DATA_INTF_SDR_MASK 0x00000007U

SDR mode.

#define XNANDPSU_DMA_BUF_BND_BND_MASK 0x00000007U

DMA buffer boundary.

#define XNANDPSU_DMA_BUF_BND_OFFSET 0x54U

DMA Buffer Boundary Register.

#define XNANDPSU_DMA_SYS_ADDR0_OFFSET 0x50U

DMA System Address 0 Register.

#define XNANDPSU_DMA_SYS_ADDR1_OFFSET 0x24U

DMA System Address 1 Register.

#define XNANDPSU_ECC_ADDR_MASK 0x0000FFFFU

ECC address.

#define XNANDPSU_ECC_CNT_1BIT_OFFSET 0x40U

Error Count 1bit Register.

#define XNANDPSU_ECC_CNT_2BIT_OFFSET 0x44U

Error Count 2bit Register.

#define XNANDPSU_ECC_CNT_3BIT_OFFSET 0x48U

Error Count 3bit Register.

#define XNANDPSU_ECC_CNT_4BIT_OFFSET 0x4CU

Error Count 4bit Register.

#define XNANDPSU_ECC_CNT_5BIT_OFFSET 0x5CU

Error Count 5bit Register.

#define XNANDPSU_ECC_CNT_6BIT_OFFSET 0x60U

Error Count 6bit Register.

#define XNANDPSU_ECC_CNT_7BIT_OFFSET 0x64U

Error Count 7bit Register.

#define XNANDPSU_ECC_CNT_8BIT_OFFSET 0x68U

Error Count 8bit Register.

#define XNANDPSU_ECC_ERR_CNT_OFFSET 0x38U

ECC Error Count Register.

#define XNANDPSU_ECC_ERR_CNT_PG_BND_ERR_CNT_MASK 0x0000FF00U

Page bound error count.

#define XNANDPSU_ECC_ERR_CNT_PKT_BND_ERR_CNT_MASK 0x000000FFU

Packet bound error count.

#define XNANDPSU_ECC_HAMMING_BCH_MASK 0x02000000U

Hamming/BCH support.

#define XNANDPSU_ECC_OFFSET 0x34U

ECC Register.

#define XNANDPSU_ECC_SIZE_MASK 0x01FF0000U

ECC size.

#define XNANDPSU_ECC_SPR_CMD_ECC_ADDR_CYCLES_MASK 0x70000000U

Number of ECC/ spare address cycles.

#define XNANDPSU_ECC_SPR_CMD_OFFSET 0x3CU

ECC Spare Command Register.

#define XNANDPSU_ECC_SPR_CMD_SPR_CMD_MASK 0x000000FFU

ECC spare command.

#define XNANDPSU_FLASH_BLOCK_BAD 0x2U

Block is bad.

#define XNANDPSU_FLASH_BLOCK_FAC_BAD 0x0U

Factory marked bad block.

#define XNANDPSU_FLASH_BLOCK_GOOD 0x3U

Block is good.

#define XNANDPSU_FLASH_BLOCK_RESERVED 0x1U

Reserved block.

#define XNANDPSU_FLASH_STS_FLASH_STS_MASK 0x0000FFFFU

Flash Status Value.

#define XNANDPSU_FLASH_STS_OFFSET 0x28U

Flash Status Register.

#define XNANDPSU_HAMMING 0x1U

Hamming Flash.

#define XNANDPSU_ID2_DEVICE_ID2_MASK 0x000000FFU

MSB Device ID.

#define XNANDPSU_INTR_BUFF_RD_RDY_STS_EN_MASK 0x00000002U

Buffer Read Ready Status Enable.

#define XNANDPSU_INTR_BUFF_WR_RDY_STS_EN_MASK 0x00000001U

Buffer Write Ready Status Enable.

#define XNANDPSU_INTR_DMA_INT_STS_EN_MASK 0x00000040U

DMA Status Enable.

#define XNANDPSU_INTR_ERR_AHB_STS_EN_MASK 0x00000080U

Error AHB Status Enable.

#define XNANDPSU_INTR_ERR_INTR_STS_EN_MASK 0x00000010U

Single Bit Error Status Enable, BCH Detect Error Status Enable.

#define XNANDPSU_INTR_MUL_BIT_ERR_STS_EN_MASK 0x00000008U

Multi Bit Error Status Enable.

#define XNANDPSU_INTR_SIG_EN_BUFF_RD_RDY_STS_EN_MASK 0x00000002U

Buffer Read Ready Signal Enable.

#define XNANDPSU_INTR_SIG_EN_BUFF_WR_RDY_STS_EN_MASK 0x00000001U

Buffer Write Ready Signal Enable.

#define XNANDPSU_INTR_SIG_EN_DMA_INT_STS_EN_MASK 0x00000040U

DMA Signal Enable.

#define XNANDPSU_INTR_SIG_EN_ERR_AHB_STS_EN_MASK 0x00000080U

Error AHB Signal Enable.

#define XNANDPSU_INTR_SIG_EN_ERR_INTR_STS_EN_MASK 0x00000010U

Single Bit Error Signal Enable, BCH Detect Error Signal Enable.

#define XNANDPSU_INTR_SIG_EN_MUL_BIT_ERR_STS_EN_MASK 0x00000008U

Multi Bit Error Signal Enable.

#define XNANDPSU_INTR_SIG_EN_OFFSET 0x18U

Interrupt Signal Enable Register.

#define XNANDPSU_INTR_SIG_EN_TRANS_COMP_STS_EN_MASK 0x00000004U

Transfer Complete Signal Enable.

#define XNANDPSU_INTR_STS_BUFF_RD_RDY_STS_EN_MASK 0x00000002U

Buffer Read Ready.

#define XNANDPSU_INTR_STS_BUFF_WR_RDY_STS_EN_MASK 0x00000001U

Buffer Write Ready.

#define XNANDPSU_INTR_STS_DMA_INT_STS_EN_MASK 0x00000040U

DMA Interrupt.

#define XNANDPSU_INTR_STS_EN_BUFF_RD_RDY_STS_EN_MASK 0x00000002U

Buffer Read Ready Status Enable.

Referenced by XNandPsu_GetFeature(), and XNandPsu_ReadSpareBytes().

#define XNANDPSU_INTR_STS_EN_BUFF_WR_RDY_STS_EN_MASK 0x00000001U

Buffer Write Ready Status Enable.

Referenced by XNandPsu_SetFeature(), and XNandPsu_WriteSpareBytes().

#define XNANDPSU_INTR_STS_EN_DMA_INT_STS_EN_MASK 0x00000040U

DMA Status Enable.

#define XNANDPSU_INTR_STS_EN_ERR_AHB_STS_EN_MASK 0x00000080U

Error AHB Status Enable.

#define XNANDPSU_INTR_STS_EN_ERR_INTR_STS_EN_MASK 0x00000010U

Single Bit Error Status Enable, BCH Detect Error Status Enable.

#define XNANDPSU_INTR_STS_EN_MUL_BIT_ERR_STS_EN_MASK 0x00000008U

Multi Bit Error Status Enable.

#define XNANDPSU_INTR_STS_EN_OFFSET 0x14U

Interrupt Status Enable Register.

Referenced by XNandPsu_EraseBlock(), XNandPsu_GetFeature(), XNandPsu_ReadSpareBytes(), XNandPsu_SetFeature(), and XNandPsu_WriteSpareBytes().

#define XNANDPSU_INTR_STS_EN_TRANS_COMP_STS_EN_MASK 0x00000004U

Transfer Complete Status Enable.

Referenced by XNandPsu_EraseBlock(), XNandPsu_ReadSpareBytes(), and XNandPsu_WriteSpareBytes().

#define XNANDPSU_INTR_STS_ERR_AHB_STS_EN_MASK 0x00000080U

Error AHB.

#define XNANDPSU_INTR_STS_ERR_INTR_STS_EN_MASK 0x00000010U

Single Bit Error, BCH Detect Error.

#define XNANDPSU_INTR_STS_MUL_BIT_ERR_STS_EN_MASK 0x00000008U

Multi Bit Error.

#define XNANDPSU_INTR_STS_OFFSET 0x1CU

Interrupt Status Register.

#define XNANDPSU_INTR_STS_TRANS_COMP_STS_EN_MASK 0x00000004U

Transfer Complete.

#define XNANDPSU_INTR_TRANS_COMP_STS_EN_MASK 0x00000004U

Transfer Complete Status Enable.

#define XNandPsu_IntrSigClear	(	InstancePtr,
		Mask
	)

Value:

XNandPsu_ClrBits((InstancePtr),                         \
                         XNANDPSU_INTR_SIG_EN_OFFSET,                   \
                         (Mask))

This macro clears bitmask in Interrupt Signal Enable register.

Parameters

InstancePtr	is a pointer to the XNandPsu instance of the controller.
Mask	is the bitmask.

Note: C-style signature: void XNandPsu_IntrSigClear(XNandPsu *InstancePtr, u32 Mask)

#define XNandPsu_IntrSigEnable	(	InstancePtr,
		Mask
	)

Value:

XNandPsu_SetBits((InstancePtr),                         \
                         XNANDPSU_INTR_SIG_EN_OFFSET,                   \
                         (Mask))

This macro enables bitmask in Interrupt Signal Enable register.

Parameters

InstancePtr	is a pointer to the XNandPsu instance of the controller.
Mask	is the bitmask.

Note: C-style signature: void XNandPsu_IntrSigEnable(XNandPsu *InstancePtr, u32 Mask)

#define XNandPsu_IntrStsEnable	(	InstancePtr,
		Mask
	)

Value:

XNandPsu_SetBits((InstancePtr),                         \
                         XNANDPSU_INTR_STS_EN_OFFSET,                   \
                         (Mask))

This macro enables bitmask in Interrupt Status Enable register.

Parameters

InstancePtr	is a pointer to the XNandPsu instance of the controller.
Mask	is the bitmask.

Note: C-style signature: void XNandPsu_IntrStsEnable(XNandPsu *InstancePtr, u32 Mask)

#define XNANDPSU_MAX_BLOCKS 16384U

Max number of Blocks.

#define XNANDPSU_MAX_LUNS 8U

Max number of LUNs.

#define XNANDPSU_MAX_PAGE_SIZE 16384U

Max page size supported.

#define XNANDPSU_MAX_PAGES_PER_BLOCK 512U

Max number pages per block.

#define XNANDPSU_MAX_PKT_COUNT 0xFFFU

Max packet count.

#define XNANDPSU_MAX_PKT_SIZE 0x7FFU

Max packet size.

#define XNANDPSU_MAX_SPARE_SIZE 0x800U

Max spare bytes of a NAND flash page of 16K.

#define XNANDPSU_MAX_TARGETS 1U

ce_n0, ce_n1

Referenced by XNandPsu_InitBbtDesc().

#define XNANDPSU_MEM_ADDR1_COL_ADDR_MASK 0x0000FFFFU

Column Address Mask.

#define XNANDPSU_MEM_ADDR1_OFFSET 0x04U

Memory Address Register 1.

#define XNANDPSU_MEM_ADDR1_PG_ADDR_MASK 0xFFFF0000U

Page, Block Address Mask.

#define XNANDPSU_MEM_ADDR1_PG_ADDR_SHIFT 16U

Page Shift.

#define XNANDPSU_MEM_ADDR2_BUS_WIDTH_MASK 0x01000000U

Bus Width.

#define XNANDPSU_MEM_ADDR2_BUS_WIDTH_SHIFT 24U

Bus width shift.

#define XNANDPSU_MEM_ADDR2_CHIP_SEL_MASK 0xC0000000U

Chip Select.

#define XNANDPSU_MEM_ADDR2_CHIP_SEL_SHIFT 30U

Chip select shift.

#define XNANDPSU_MEM_ADDR2_MEM_ADDR_MASK 0x000000FFU

Memory Address.

#define XNANDPSU_MEM_ADDR2_MODE_MASK 0x30000000U

Flash Connection Mode.

#define XNANDPSU_MEM_ADDR2_NFC_BCH_MODE_MASK 0x0E000000U

BCH Mode Value.

#define XNANDPSU_MEM_ADDR2_OFFSET 0x08U

Memory Address Register 2.

#define XNANDPSU_NO_OOB_BBT_DESC_SIG_OFFSET 0U

Bad Block Table signature offset in page memory.

#define XNANDPSU_NO_OOB_BBT_DESC_VER_OFFSET 4U

Bad block Table version offset in page memory.

#define XNANDPSU_PAGE_SIZE_16K 16384U

16K bytes page

#define XNANDPSU_PAGE_SIZE_1K_16BIT 1024U

16-bit 2K bytes page

#define XNANDPSU_PAGE_SIZE_2K 2048U

2K bytes page

#define XNANDPSU_PAGE_SIZE_4K 4096U

4K bytes page

#define XNANDPSU_PAGE_SIZE_512 512U

512 bytes page

#define XNANDPSU_PAGE_SIZE_8K 8192U

8K bytes page

#define XNANDPSU_PKT_OFFSET 0x00U

Packet Register.

#define XNANDPSU_PKT_PKT_CNT_MASK 0x00FFF000U

Packet Count.

#define XNANDPSU_PKT_PKT_CNT_SHIFT 12U

Packet Count Shift.

#define XNANDPSU_PKT_PKT_SIZE_MASK 0x000007FFU

Packet Size.

#define XNANDPSU_PROG_BLK_ERASE_MASK 0x00000004U

Block Erase.

Referenced by XNandPsu_EraseBlock().

#define XNANDPSU_PROG_CHNG_RD_COL_ENH_MASK 0x00004000U

Change Read Column Enhanced.

#define XNANDPSU_PROG_CHNG_ROW_ADDR_END_MASK 0x00400000U

Change Row Address End.

#define XNANDPSU_PROG_CHNG_ROW_ADDR_MASK 0x00200000U

Change Row Address.

Referenced by XNandPsu_WriteSpareBytes().

#define XNANDPSU_PROG_COPY_BACK_INTRLVD_MASK 0x00008000U

Copy Back Interleaved.

#define XNANDPSU_PROG_GET_FEATURES_MASK 0x00000200U

Get Features.

Referenced by XNandPsu_GetFeature().

#define XNANDPSU_PROG_MUL_DIE_MASK 0x00000002U

Multi Die.

#define XNANDPSU_PROG_MUL_DIE_RD_MASK 0x00000020U

Multi Die Rd.

#define XNANDPSU_PROG_ODT_CONF_MASK 0x04000000U

ODT Configure.

#define XNANDPSU_PROG_OFFSET 0x10U

Program Register.

Referenced by XNandPsu_EraseBlock(), XNandPsu_GetFeature(), XNandPsu_ReadSpareBytes(), XNandPsu_SetFeature(), and XNandPsu_WriteSpareBytes().

#define XNANDPSU_PROG_PG_PROG_MASK 0x00000010U

Page Program.

Referenced by XNandPsu_WriteSpareBytes().

#define XNANDPSU_PROG_PGM_PG_CLR_MASK 0x01000000U

Enhanced Program Page Register Clear.

#define XNANDPSU_PROG_RD_CACHE_END_MASK 0x00080000U

Read Cache End.

#define XNANDPSU_PROG_RD_CACHE_RAND_MASK 0x00040000U

Read Cache Random.

#define XNANDPSU_PROG_RD_CACHE_SEQ_MASK 0x00020000U

Read Cache Sequential.

#define XNANDPSU_PROG_RD_CACHE_START_MASK 0x00010000U

Read Cache Start.

#define XNANDPSU_PROG_RD_ID_MASK 0x00000040U

Read ID.

#define XNANDPSU_PROG_RD_INTRLVD_MASK 0x00002000U

Read Interleaved.

#define XNANDPSU_PROG_RD_MASK 0x00000001U

Read.

Referenced by XNandPsu_ReadSpareBytes().

#define XNANDPSU_PROG_RD_PRM_PG_MASK 0x00000080U

Read Param Page.

#define XNANDPSU_PROG_RD_STS_ENH_MASK 0x00001000U

Read Status Enhanced.

#define XNANDPSU_PROG_RD_STS_MASK 0x00000008U

Read Status.

#define XNANDPSU_PROG_RD_UNQ_ID_MASK 0x00000800U

Read Unique ID.

#define XNANDPSU_PROG_RST_LUN_MASK 0x00800000U

Reset LUN.

#define XNANDPSU_PROG_RST_MASK 0x00000100U

Reset.

#define XNANDPSU_PROG_SET_FEATURES_MASK 0x00000400U

Set Features.

Referenced by XNandPsu_SetFeature().

#define XNANDPSU_PROG_SMALL_DATA_MOVE_MASK 0x00100000U

Small Data Move.

#define XNANDPSU_PROG_VOL_SEL_MASK 0x02000000U

Volume Select.

#define XNandPsu_ReadModifyWrite	(	InstancePtr,
		RegOffset,
		Mask,
		Value
	)

Value:

XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,            \
                          (RegOffset),                                          \
                          ((u32)((u32)(XNandPsu_ReadReg((InstancePtr)->Config.BaseAddress,\
                                          (u32)(RegOffset)) & (u32)(~(Mask))) | (u32)(Value))))

This macro clears and updates the bitmask in the register.

Parameters

InstancePtr	is a pointer to the XNandPsu instance of the controller.
RegOffset	is the register offset.
Mask	is the bitmask.
Value	is the register value to write.

Note: C-style signature: void XNandPsu_ReadModifyWrite(XNandPsu *InstancePtr, u32 RegOffset, u32 Mask, u32 Val)

#define XNandPsu_ReadReg	(	BaseAddress,
		RegOffset
	)	Xil_In32((BaseAddress) + (RegOffset))

This macro reads the given register.

Parameters

BaseAddress	is the base address of controller registers.
RegOffset	is the register offset to be read.

Returns: The 32-bit value of the register.

Note: C-style signature: u32 XNandPsu_ReadReg(u32 BaseAddress, u32 RegOffset)

#define XNANDPSU_READY_BUSY_OFFSET 0x20U

Ready/Busy status Register.

#define XNandPsu_SetBits	(	InstancePtr,
		RegOffset,
		BitMask
	)

Value:

XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,            \
                          (RegOffset),                                          \
                          ((u32)(XNandPsu_ReadReg((InstancePtr)->Config.BaseAddress,    \
                                          (RegOffset)) | (BitMask))))

This macro sets the bitmask in the register.

Parameters

InstancePtr	is a pointer to the XNandPsu instance of the controller.
RegOffset	is the register offset.
BitMask	is the bitmask.

Note: C-style signature: void XNandPsu_SetBits(XNandPsu *InstancePtr, u32 RegOffset, u32 BitMask)

#define XNANDPSU_SLV_DMA_CONF_DMA_BURST_SIZE_MASK 0x00E00000U

Slave DMA Burst Size.

#define XNANDPSU_SLV_DMA_CONF_DMA_TMOUT_CNT_VAL_MASK 0x0F000000U

DMA Timeout Counter Value.

#define XNANDPSU_SLV_DMA_CONF_DMA_TRANS_CNT_MASK 0x001FFFFEU

Slave DMA Transfer Count.

#define XNANDPSU_SLV_DMA_CONF_OFFSET 0x80U

Slave DMA Configuration Register.

#define XNANDPSU_SLV_DMA_CONF_SDMA_EN_MASK 0x10000000U

Slave DMA Enable.

#define XNANDPSU_SLV_DMA_CONF_SDMA_TX_RX_MASK 0x00000001U

Slave DMA Transfer Direction.

#define XNANDPSU_TIMING_DQS_BUFF_SEL_MASK 0x00000078U

Write/Read data transaction value.

#define XNANDPSU_TIMING_OFFSET 0x2CU

Timing Register.

#define XNANDPSU_TIMING_SLOW_FAST_TCAD_MASK 0x00000004U

Slow/Fast device.

#define XNANDPSU_TIMING_TADL_TIME_MASK 0x00007F80U

Address latch enable to Data loading time.

#define XNANDPSU_TIMING_TCCS_TIME_MASK 0x00000003U

Change column setup time.

#define XNandPsu_WriteReg	(	BaseAddress,
		RegOffset,
		Data
	)	Xil_Out32(((BaseAddress) + (RegOffset)), (Data))

This macro writes the given register.

Parameters

BaseAddress	is the the base address of controller registers.
RegOffset	is the register offset to be written.
Data	is the the 32-bit value to write to the register.

Returns: None.

Note: C-style signature: void XNandPsu_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)

Referenced by XNandPsu_ChangeTimingMode(), XNandPsu_EraseBlock(), XNandPsu_GetFeature(), XNandPsu_Prepare_Cmd(), XNandPsu_ReadSpareBytes(), XNandPsu_SetFeature(), and XNandPsu_WriteSpareBytes().

Enumeration Type Documentation

enum OnfiCommandList

This enum defines the ONFI 3.1 commands.

Enumerator
READ	Read.
MULTIPLANE_READ	Multiplane Read.
COPYBACK_READ	Copyback Read.
CHANGE_READ_COLUMN	Change Read Column.
CHANGE_READ_COLUMN_ENHANCED	Change Read Column Enhanced.
READ_CACHE_RANDOM	Read Cache Random.
READ_CACHE_SEQUENTIAL	Read Cache Sequential.
READ_CACHE_END	Read Cache End.
BLOCK_ERASE	Block Erase.
MULTIPLANE_BLOCK_ERASE	Multiplane Block Erase.
READ_STATUS	Read Status.
READ_STATUS_ENHANCED	Read Status Enhanced.
PAGE_PROGRAM	Page Program.
MULTIPLANE_PAGE_PROGRAM	Multiplane Page Program.
PAGE_CACHE_PROGRAM	Page Cache Program.
COPYBACK_PROGRAM	Copyback Program.
MULTIPLANE_COPYBACK_PROGRAM	Multiplance Copyback Program.
SMALL_DATA_MOVE	Small Data Move.
CHANGE_WRITE_COLUMN	Change Write Column.
CHANGE_ROW_ADDR	Change Row Address.
READ_ID	Read ID.
VOLUME_SELECT	Volume Select.
ODT_CONFIGURE	ODT Configure.
READ_PARAM_PAGE	Read Parameter Page.
READ_UNIQUE_ID	Read Unique ID.
GET_FEATURES	Get Features.
SET_FEATURES	Set Features.
LUN_GET_FEATURES	LUN Get Features.
LUN_SET_FEATURES	LUN Set Features.
RESET_LUN	Reset LUN.
SYN_RESET	Synchronous Reset.
RESET	Reset.
MAX_CMDS	Dummy Command.

enum XNandPsu_DataInterface

The XNandPsu_DataInterface enum contains flash operating mode.

Enumerator
XNANDPSU_SDR	Single Data Rate.
XNANDPSU_NVDDR	Double Data Rate.

enum XNandPsu_DmaMode

The XNandPsu_DmaMode enum contains the controller MDMA mode.

Enumerator
XNANDPSU_PIO	PIO Mode.
XNANDPSU_SDMA	SDMA Mode.
XNANDPSU_MDMA	MDMA Mode.

enum XNandPsu_EccMode

The XNandPsu_EccMode enum contains ECC functionality.

enum XNandPsu_SWMode

The XNandPsu_SWMode enum contains the driver operating mode.

Enumerator
XNANDPSU_POLLING	Polling.
XNANDPSU_INTERRUPT	Interrupt.

enum XNandPsu_TimingMode

XNandPsu_TimingMode enum contains timing modes.

Function Documentation

s32 XNandPsu_CfgInitialize	(	XNandPsu *	InstancePtr,
		XNandPsu_Config *	ConfigPtr,
		u32	EffectiveAddr
	)

This function initializes a specific XNandPsu instance.

This function must be called prior to using the NAND flash device to read or write any data.

Parameters

InstancePtr	is a pointer to the XNandPsu instance.
ConfigPtr	points to XNandPsu device configuration structure.
EffectiveAddr	is the base address of NAND flash controller.

Returns

XST_SUCCESS if successful.
XST_FAILURE if fail.

Note: The user needs to first call the XNandPsu_LookupConfig() API which returns the Configuration structure pointer which is passed as a parameter to the XNandPsu_CfgInitialize() API.

References XNandPsu_Config::BaseAddress, XNandPsu_Config::DeviceId, XNandPsu::DmaMode, XNandPsu::Ecc_Stat_PerPage_flips, XNandPsu::Ecc_Stats_total_flips, XNandPsu::EccMode, XNandPsu::Features, XNandPsu_Config::IsCacheCoherent, XNandPsu::IsReady, XNandPsu::Mode, XNandPsu_InitBbtDesc(), XNANDPSU_MDMA, XNANDPSU_POLLING, and XNandPsu_ScanBbt().

Referenced by NandReadWriteExample().

s32 XNandPsu_ChangeTimingMode	(	XNandPsu *	InstancePtr,
		XNandPsu_DataInterface	NewIntf,
		XNandPsu_TimingMode	NewMode
	)

This function changes the data interface and timing mode.

Parameters

InstancePtr	is a pointer to the XNandPsu instance.
NewIntf	is the new data interface.
NewMode	is the new timing mode.

Returns

XST_SUCCESS if successful.
XST_FAILURE if failed.

Note: None

References XNandPsu_Config::BaseAddress, XNandPsu::Geometry, XNandPsu::IsReady, XNandPsu_Geometry::NumTargets, XNANDPSU_DATA_INTF_DATA_INTF_SHIFT, XNANDPSU_DATA_INTF_OFFSET, XNandPsu_GetFeature(), XNANDPSU_NVDDR, XNANDPSU_SDR, XNandPsu_SetFeature(), and XNandPsu_WriteReg.

Referenced by NandReadWriteExample().

void XNandPsu_DisableDmaMode ( XNandPsu * InstancePtr )

This function disables DMA mode of driver/controller operation.

Parameters

InstancePtr is a pointer to the XNandPsu instance.

Returns: None

Note: None

References XNandPsu::DmaMode, XNandPsu::IsReady, and XNANDPSU_PIO.

void XNandPsu_DisableEccMode ( XNandPsu * InstancePtr )

This function disables ECC mode of driver/controller operation.

Parameters

InstancePtr is a pointer to the XNandPsu instance.

Returns: None

Note: None

References XNandPsu::EccMode, and XNandPsu::IsReady.

void XNandPsu_EnableDmaMode ( XNandPsu * InstancePtr )

This function enables DMA mode of controller operation.

Parameters

InstancePtr is a pointer to the XNandPsu instance.

Returns: None

Note: None

References XNandPsu::DmaMode, XNandPsu::IsReady, and XNANDPSU_MDMA.

Referenced by NandReadWriteExample().

void XNandPsu_EnableEccMode ( XNandPsu * InstancePtr )

This function enables ECC mode of driver/controller operation.

Parameters

InstancePtr is a pointer to the XNandPsu instance.

Returns: None

Note: None

References XNandPsu::EccMode, and XNandPsu::IsReady.

s32 XNandPsu_Erase	(	XNandPsu *	InstancePtr,
		u64	Offset,
		u64	Length
	)

This function erases the flash.

Parameters

InstancePtr	is a pointer to the XNandPsu instance.
Offset	is the starting offset of flash to erase.
Length	is the number of bytes to erase.

Returns

XST_SUCCESS if successful.
XST_FAILURE if failed.

Note: The Offset and Length should be aligned to block size boundary to get better results.

References XNandPsu_Geometry::BlockSize, XNandPsu_Geometry::DeviceSize, XNandPsu::Geometry, XNandPsu::IsReady, XNandPsu_Geometry::NumTargetBlocks, XNandPsu_EraseBlock(), and XNandPsu_IsBlockBad().

Referenced by NandReadWriteExample().

s32 XNandPsu_EraseBlock	(	XNandPsu *	InstancePtr,
		u32	Target,
		u32	Block
	)

This function sends ONFI block erase command to the flash.

Parameters

InstancePtr	is a pointer to the XNandPsu instance.
Target	is the chip select value.
Block	is the block to erase.

Returns

XST_SUCCESS if successful.
XST_FAILURE if failed.

Note: None

References XNandPsu::Geometry, XNandPsu::IsReady, ONFI_CMD_BLK_ERASE1, ONFI_CMD_BLK_ERASE2, XNandPsu_Geometry::PagesPerBlock, XNandPsu_Geometry::RowAddrCycles, XNANDPSU_INTR_STS_EN_OFFSET, XNANDPSU_INTR_STS_EN_TRANS_COMP_STS_EN_MASK, XNandPsu_Prepare_Cmd(), XNANDPSU_PROG_BLK_ERASE_MASK, XNANDPSU_PROG_OFFSET, and XNandPsu_WriteReg.

Referenced by XNandPsu_Erase().

s32 XNandPsu_GetFeature	(	XNandPsu *	InstancePtr,
		u32	Target,
		u8	Feature,
		u8 *	Buf
	)

This function sends ONFI Get Feature command to flash.

Parameters

InstancePtr	is a pointer to the XNandPsu instance.
Target	is the chip select value.
Feature	is the feature selector.
Buf	is the buffer to fill feature value.

Returns

XST_SUCCESS if successful.
XST_FAILURE if failed.

Note: None

References XNandPsu::IsReady, ONFI_CMD_GET_FEATURES, ONFI_CMD_INVALID, XNANDPSU_INTR_STS_EN_BUFF_RD_RDY_STS_EN_MASK, XNANDPSU_INTR_STS_EN_OFFSET, XNANDPSU_NVDDR, XNandPsu_Prepare_Cmd(), XNANDPSU_PROG_GET_FEATURES_MASK, XNANDPSU_PROG_OFFSET, and XNandPsu_WriteReg.

Referenced by XNandPsu_ChangeTimingMode().

void XNandPsu_InitBbtDesc ( XNandPsu * InstancePtr )

This function initializes the Bad Block Table(BBT) descriptors with a predefined pattern for searching Bad Block Table(BBT) in flash.

Parameters

InstancePtr is a pointer to the XNandPsu instance.

Returns

NONE

References XNandPsu::BbPattern, XNandPsu::BbtDesc, XNandPsu::BbtMirrorDesc, XNandPsu_Geometry::BytesPerPage, XNandPsu::EccMode, XNandPsu::Geometry, XNandPsu_BadBlockPattern::Length, XNandPsu_BbtDesc::MaxBlocks, XNandPsu_Geometry::NumTargetBlocks, XNandPsu_BadBlockPattern::Offset, XNandPsu_BadBlockPattern::Options, XNandPsu_BbtDesc::PageOffset, XNandPsu_BadBlockPattern::Pattern, XNandPsu_BbtDesc::SigLength, XNandPsu_BbtDesc::Signature, XNandPsu_BbtDesc::SigOffset, XNandPsu_BbtDesc::Valid, XNandPsu_BbtDesc::VerOffset, XNandPsu_BbtDesc::Version, XNANDPSU_BB_PATTERN, XNANDPSU_BB_PTRN_LEN_LARGE_PAGE, XNANDPSU_BB_PTRN_LEN_SML_PAGE, XNANDPSU_BB_PTRN_OFF_LARGE_PAGE, XNANDPSU_BB_PTRN_OFF_SML_PAGE, XNANDPSU_BBT_DESC_MAX_BLOCKS, XNANDPSU_BBT_DESC_PAGE_OFFSET, XNANDPSU_BBT_DESC_SIG_LEN, XNANDPSU_BBT_DESC_SIG_OFFSET, XNANDPSU_BBT_DESC_VER_OFFSET, XNANDPSU_BBT_SCAN_2ND_PAGE, and XNANDPSU_MAX_TARGETS.

Referenced by XNandPsu_CfgInitialize().

s32 XNandPsu_IsBlockBad	(	XNandPsu *	InstancePtr,
		u32	Block
	)

This function checks whether a block is bad or not.

Parameters

InstancePtr	is the pointer to the XNandPsu instance.
Block	is the block number.

Returns

XST_SUCCESS if successful.
XST_FAILURE if fail.

References XNandPsu::Bbt, XNandPsu::IsReady, XNANDPSU_BBT_BLOCK_SHIFT, XNandPsu_BbtBlockShift, XNANDPSU_BLOCK_GOOD, XNANDPSU_BLOCK_RESERVED, and XNANDPSU_BLOCK_TYPE_MASK.

Referenced by XNandPsu_Erase(), XNandPsu_Read(), and XNandPsu_Write().

XNandPsu_Config * XNandPsu_LookupConfig ( u16 DevID )

Looks up the controller configuration based on the unique controller ID.

A table contains the configuration info for each controller in the system.

Parameters

DevID is the ID of the controller to look up the configuration for.

Returns: A pointer to the configuration found or NULL if the specified controller ID was not found.

Referenced by NandReadWriteExample().

s32 XNandPsu_MarkBlockBad	(	XNandPsu *	InstancePtr,
		u32	Block
	)

This function marks a block as bad in the RAM based Bad Block Table(BBT).

It also updates the Bad Block Table(BBT) in the flash.

Parameters

InstancePtr	is the pointer to the XNandPsu instance.
Block	is the block number.

Returns

XST_SUCCESS if successful.
XST_FAILURE if fail.

References XNandPsu::Bbt, XNandPsu::Geometry, XNandPsu::IsReady, XNandPsu_Geometry::NumTargetBlocks, XNANDPSU_BBT_BLOCK_SHIFT, XNandPsu_BbtBlockShift, XNANDPSU_BLOCK_BAD, and XNANDPSU_BLOCK_TYPE_MASK.

u32 XNandPsu_OnfiParamPageCrc	(	u8 *	ParamBuf,
		u32	StartOff,
		u32	Length
	)

This function calculates ONFI parameter page CRC.

Parameters

ParamBuf	is a pointer to the ONFI parameter page buffer.
StartOff	is the starting offset in buffer to calculate CRC.
Length	is the number of bytes for which CRC is calculated.

Returns: CRC value.

Note: None.

void XNandPsu_Prepare_Cmd	(	XNandPsu *	InstancePtr,
		u8	Cmd1,
		u8	Cmd2,
		u8	EccState,
		u8	DmaMode,
		u8	AddrCycles
	)

This function prepares command to be written into command register.

Parameters

InstancePtr	is a pointer to the XNandPsu instance.
Cmd1	is the first Onfi Command.
Cmd2	is the second Onfi Command.
EccState	is the flag to set Ecc State.
DmaMode	is the flag to set DMA mode.
AddrCycles	is the number of Address Cycles.

Returns: None

Note: None

References XNandPsu::DmaMode, XNandPsu::EccMode, XNANDPSU_CMD_ADDR_CYCLES_SHIFT, XNANDPSU_CMD_CMD2_MASK, XNANDPSU_CMD_CMD2_SHIFT, XNANDPSU_CMD_DMA_EN_SHIFT, XNANDPSU_CMD_ECC_ON_SHIFT, XNANDPSU_CMD_OFFSET, XNANDPSU_MDMA, and XNandPsu_WriteReg.

Referenced by XNandPsu_EraseBlock(), XNandPsu_GetFeature(), XNandPsu_ReadSpareBytes(), XNandPsu_SetFeature(), and XNandPsu_WriteSpareBytes().

s32 XNandPsu_Read	(	XNandPsu *	InstancePtr,
		u64	Offset,
		u64	Length,
		u8 *	DestBuf
	)

This function reads from the flash.

Parameters

InstancePtr	is a pointer to the XNandPsu instance.
Offset	is the starting offset of flash to read.
Length	is the number of bytes to read.
DestBuf	is the destination data buffer to fill in.

Returns

XST_SUCCESS if successful.
XST_FAILURE if failed.

Note: None

References XNandPsu_Geometry::BlockSize, XNandPsu_Geometry::BytesPerPage, XNandPsu_Geometry::DeviceSize, XNandPsu::Geometry, XNandPsu_Config::IsCacheCoherent, XNandPsu::IsReady, XNandPsu_Geometry::NumTargetPages, XNandPsu_Geometry::TargetSize, and XNandPsu_IsBlockBad().

Referenced by NandReadWriteExample().

s32 XNandPsu_ReadSpareBytes	(	XNandPsu *	InstancePtr,
		u32	Page,
		u8 *	Buf
	)

This function reads spare bytes from flash.

Parameters

InstancePtr	is a pointer to the XNandPsu instance.
Page	is the page address value to read.
Buf	is the data buffer to fill in.

Returns

XST_SUCCESS if successful.
XST_FAILURE if failed.

Note: None

References XNandPsu_Geometry::BytesPerPage, XNandPsu_Geometry::ColAddrCycles, XNandPsu::DmaMode, XNandPsu::Geometry, XNandPsu_Config::IsCacheCoherent, XNandPsu::IsReady, XNandPsu_Geometry::NumTargetPages, ONFI_CMD_RD1, ONFI_CMD_RD2, XNandPsu_Geometry::RowAddrCycles, XNandPsu_Geometry::SpareBytesPerPage, XNANDPSU_INTR_STS_EN_BUFF_RD_RDY_STS_EN_MASK, XNANDPSU_INTR_STS_EN_OFFSET, XNANDPSU_INTR_STS_EN_TRANS_COMP_STS_EN_MASK, XNANDPSU_MDMA, XNandPsu_Prepare_Cmd(), XNANDPSU_PROG_OFFSET, XNANDPSU_PROG_RD_MASK, and XNandPsu_WriteReg.

s32 XNandPsu_ScanBbt ( XNandPsu * InstancePtr )

This function reads the Bad Block Table(BBT) if present in flash.

If not it scans the flash for detecting factory marked bad blocks and creates a bad block table and write the Bad Block Table(BBT) into the flash.

Parameters

InstancePtr is a pointer to the XNandPsu instance.

Returns

XST_SUCCESS if successful.
XST_FAILURE if fail.

References XNandPsu::Bbt, XNandPsu::BbtDesc, XNandPsu::BbtMirrorDesc, XNandPsu::Geometry, XNandPsu::IsReady, XNandPsu_Geometry::NumBlocks, XNandPsu_Geometry::NumTargets, and XNANDPSU_BBT_BLOCK_SHIFT.

Referenced by XNandPsu_CfgInitialize().

s32 XNandPsu_SetFeature	(	XNandPsu *	InstancePtr,
		u32	Target,
		u8	Feature,
		u8 *	Buf
	)

This function sends ONFI Set Feature command to flash.

Parameters

InstancePtr	is a pointer to the XNandPsu instance.
Target	is the chip select value.
Feature	is the feature selector.
Buf	is the feature value to send.

Returns

XST_SUCCESS if successful.
XST_FAILURE if failed.

Note: None

References XNandPsu::IsReady, ONFI_CMD_INVALID, ONFI_CMD_SET_FEATURES, XNANDPSU_INTR_STS_EN_BUFF_WR_RDY_STS_EN_MASK, XNANDPSU_INTR_STS_EN_OFFSET, XNANDPSU_NVDDR, XNandPsu_Prepare_Cmd(), XNANDPSU_PROG_OFFSET, XNANDPSU_PROG_SET_FEATURES_MASK, and XNandPsu_WriteReg.

Referenced by XNandPsu_ChangeTimingMode().

s32 XNandPsu_Write	(	XNandPsu *	InstancePtr,
		u64	Offset,
		u64	Length,
		u8 *	SrcBuf
	)

This function writes to the flash.

Parameters

InstancePtr	is a pointer to the XNandPsu instance.
Offset	is the starting offset of flash to write.
Length	is the number of bytes to write.
SrcBuf	is the source data buffer to write.

Returns

XST_SUCCESS if successful.
XST_FAILURE if failed.

Note: None

References XNandPsu_Geometry::BlockSize, XNandPsu_Geometry::BytesPerPage, XNandPsu_Geometry::DeviceSize, XNandPsu::Geometry, XNandPsu::IsReady, XNandPsu_Geometry::NumTargetPages, XNandPsu_Geometry::TargetSize, and XNandPsu_IsBlockBad().

Referenced by NandReadWriteExample().

s32 XNandPsu_WriteSpareBytes	(	XNandPsu *	InstancePtr,
		u32	Page,
		u8 *	Buf
	)

This function sends ONFI Program Page command to flash.

Parameters

InstancePtr	is a pointer to the XNandPsu instance.
Page	is the page address value to program.
Buf	is the data buffer to program.

Returns

XST_SUCCESS if successful.
XST_FAILURE if failed.

Note: None

References XNandPsu_Geometry::BytesPerPage, XNandPsu_Geometry::ColAddrCycles, XNandPsu::DmaMode, XNandPsu::EccCfg, XNandPsu::EccMode, XNandPsu::Geometry, XNandPsu_Config::IsCacheCoherent, XNandPsu::IsReady, XNandPsu_Geometry::NumTargetPages, ONFI_CMD_PG_PROG1, ONFI_CMD_PG_PROG2, XNandPsu_Geometry::RowAddrCycles, XNandPsu_Geometry::SpareBytesPerPage, XNANDPSU_INTR_STS_EN_BUFF_WR_RDY_STS_EN_MASK, XNANDPSU_INTR_STS_EN_OFFSET, XNANDPSU_INTR_STS_EN_TRANS_COMP_STS_EN_MASK, XNANDPSU_MDMA, XNandPsu_Prepare_Cmd(), XNANDPSU_PROG_CHNG_ROW_ADDR_MASK, XNANDPSU_PROG_OFFSET, XNANDPSU_PROG_PG_PROG_MASK, and XNandPsu_WriteReg.

Variable Documentation

XNandPsu_Config XNandPsu_ConfigTable[]

Each XNandPsu device in the system has an entry in this table.

XNandPsu_Config XNandPsu_ConfigTable[]

Initial value:

= {
        {
                0U,
                (u32)XPAR_XNANDPSU_0_BASEADDR
        }
}

Each XNandPsu device in the system has an entry in this table.

Data Structures

Macros

Enumerations

Functions

Variables

Packet Register bit definitions and masks

Memory Address Register 1 bit definitions and masks

Memory Address Register 2 bit definitions and masks

Command Register bit definitions and masks

Program Register bit definitions and masks

Interrupt Status Enable Register bit definitions and masks

Interrupt Signal Enable Register bit definitions and masks

Interrupt Status Register bit definitions and masks

Interrupt bit definitions and masks

ID2 Register bit definitions and masks

Flash Status Register bit definitions and masks

Timing Register bit definitions and masks

ECC Register bit definitions and masks

ECC Error Count Register bit definitions and masks

ECC Spare Command Register bit definitions and masks

Data Interface Register bit definitions and masks

DMA Buffer Boundary Register bit definitions and masks

Slave DMA Configuration Register bit definitions and masks

Macro Definition Documentation

Enumeration Type Documentation

Function Documentation

Variable Documentation