 |
nandpsu
Vitis Drivers API Documentation
|
|
nandpsu
Vitis Drivers API Documentation
|
Macros | |
| #define | XNANDPSU_PKT_OFFSET 0x00U |
| Packet Register. More... | |
| #define | XNANDPSU_MEM_ADDR1_OFFSET 0x04U |
| Memory Address Register 1. More... | |
| #define | XNANDPSU_MEM_ADDR2_OFFSET 0x08U |
| Memory Address Register 2. More... | |
| #define | XNANDPSU_CMD_OFFSET 0x0CU |
| Command Register. More... | |
| #define | XNANDPSU_PROG_OFFSET 0x10U |
| Program Register. More... | |
| #define | XNANDPSU_INTR_STS_EN_OFFSET 0x14U |
| Interrupt Status Enable Register. More... | |
| #define | XNANDPSU_INTR_SIG_EN_OFFSET 0x18U |
| Interrupt Signal Enable Register. More... | |
| #define | XNANDPSU_INTR_STS_OFFSET 0x1CU |
| Interrupt Status Register. More... | |
| #define | XNANDPSU_READY_BUSY_OFFSET 0x20U |
| Ready/Busy status Register. More... | |
| #define | XNANDPSU_FLASH_STS_OFFSET 0x28U |
| Flash Status Register. More... | |
| #define | XNANDPSU_TIMING_OFFSET 0x2CU |
| Timing Register. More... | |
| #define | XNANDPSU_BUF_DATA_PORT_OFFSET 0x30U |
| Buffer Data Port Register. More... | |
| #define | XNANDPSU_ECC_OFFSET 0x34U |
| ECC Register. More... | |
| #define | XNANDPSU_ECC_ERR_CNT_OFFSET 0x38U |
| ECC Error Count Register. More... | |
| #define | XNANDPSU_ECC_SPR_CMD_OFFSET 0x3CU |
| ECC Spare Command Register. More... | |
| #define | XNANDPSU_ECC_CNT_1BIT_OFFSET 0x40U |
| Error Count 1bit Register. More... | |
| #define | XNANDPSU_ECC_CNT_2BIT_OFFSET 0x44U |
| Error Count 2bit Register. More... | |
| #define | XNANDPSU_ECC_CNT_3BIT_OFFSET 0x48U |
| Error Count 3bit Register. More... | |
| #define | XNANDPSU_ECC_CNT_4BIT_OFFSET 0x4CU |
| Error Count 4bit Register. More... | |
| #define | XNANDPSU_CPU_REL_OFFSET 0x58U |
| CPU Release Register. More... | |
| #define | XNANDPSU_ECC_CNT_5BIT_OFFSET 0x5CU |
| Error Count 5bit Register. More... | |
| #define | XNANDPSU_ECC_CNT_6BIT_OFFSET 0x60U |
| Error Count 6bit Register. More... | |
| #define | XNANDPSU_ECC_CNT_7BIT_OFFSET 0x64U |
| Error Count 7bit Register. More... | |
| #define | XNANDPSU_ECC_CNT_8BIT_OFFSET 0x68U |
| Error Count 8bit Register. More... | |
| #define | XNANDPSU_DATA_INTF_OFFSET 0x6CU |
| Data Interface Register. More... | |
| #define | XNANDPSU_DMA_SYS_ADDR0_OFFSET 0x50U |
| DMA System Address 0 Register. More... | |
| #define | XNANDPSU_DMA_SYS_ADDR1_OFFSET 0x24U |
| DMA System Address 1 Register. More... | |
| #define | XNANDPSU_DMA_BUF_BND_OFFSET 0x54U |
| DMA Buffer Boundary Register. More... | |
| #define | XNANDPSU_SLV_DMA_CONF_OFFSET 0x80U |
| Slave DMA Configuration Register. More... | |
| #define | XNandPsu_ReadReg(BaseAddress, RegOffset) Xil_In32((BaseAddress) + (RegOffset)) |
| This macro reads the given register. More... | |
| #define | XNandPsu_WriteReg(BaseAddress, RegOffset, Data) Xil_Out32(((BaseAddress) + (RegOffset)), (Data)) |
| This macro writes the given register. More... | |
Packet Register bit definitions and masks | |
| #define | XNANDPSU_PKT_PKT_SIZE_MASK 0x000007FFU |
| Packet Size. More... | |
| #define | XNANDPSU_PKT_PKT_CNT_MASK 0x00FFF000U |
| Packet Count. More... | |
| #define | XNANDPSU_PKT_PKT_CNT_SHIFT 12U |
| Packet Count Shift. More... | |
Memory Address Register 1 bit definitions and masks | |
| #define | XNANDPSU_MEM_ADDR1_COL_ADDR_MASK 0x0000FFFFU |
| Column Address Mask. More... | |
| #define | XNANDPSU_MEM_ADDR1_PG_ADDR_MASK 0xFFFF0000U |
| Page, Block Address Mask. More... | |
| #define | XNANDPSU_MEM_ADDR1_PG_ADDR_SHIFT 16U |
| Page Shift. More... | |
Memory Address Register 2 bit definitions and masks | |
| #define | XNANDPSU_MEM_ADDR2_MEM_ADDR_MASK 0x000000FFU |
| Memory Address. More... | |
| #define | XNANDPSU_MEM_ADDR2_BUS_WIDTH_MASK 0x01000000U |
| Bus Width. More... | |
| #define | XNANDPSU_MEM_ADDR2_NFC_BCH_MODE_MASK 0x0E000000U |
| BCH Mode Value. More... | |
| #define | XNANDPSU_MEM_ADDR2_MODE_MASK 0x30000000U |
| Flash Connection Mode. More... | |
| #define | XNANDPSU_MEM_ADDR2_CHIP_SEL_MASK 0xC0000000U |
| Chip Select. More... | |
| #define | XNANDPSU_MEM_ADDR2_CHIP_SEL_SHIFT 30U |
| Chip select shift. More... | |
| #define | XNANDPSU_MEM_ADDR2_BUS_WIDTH_SHIFT 24U |
| Bus width shift. More... | |
| #define | XNANDPSU_MEM_ADDR2_NFC_BCH_MODE_SHIFT 25U |
Command Register bit definitions and masks | |
| #define | XNANDPSU_CMD_CMD1_MASK 0x000000FFU |
| 1st Cycle Command More... | |
| #define | XNANDPSU_CMD_CMD2_MASK 0x0000FF00U |
| 2nd Cycle Command More... | |
| #define | XNANDPSU_CMD_PG_SIZE_MASK 0x03800000U |
| Page Size. More... | |
| #define | XNANDPSU_CMD_DMA_EN_MASK 0x0C000000U |
| DMA Enable Mode. More... | |
| #define | XNANDPSU_CMD_ADDR_CYCLES_MASK 0x70000000U |
| Number of Address Cycles. More... | |
| #define | XNANDPSU_CMD_ECC_ON_MASK 0x80000000U |
| ECC ON/OFF. More... | |
| #define | XNANDPSU_CMD_CMD2_SHIFT 8U |
| 2nd Cycle Command Shift More... | |
| #define | XNANDPSU_CMD_PG_SIZE_SHIFT 23U |
| Page Size Shift. More... | |
| #define | XNANDPSU_CMD_DMA_EN_SHIFT 26U |
| DMA Enable Shift. More... | |
| #define | XNANDPSU_CMD_ADDR_CYCLES_SHIFT 28U |
| Number of Address Cycles Shift. More... | |
| #define | XNANDPSU_CMD_ECC_ON_SHIFT 31U |
| ECC ON/OFF. More... | |
Program Register bit definitions and masks | |
| #define | XNANDPSU_PROG_RD_MASK 0x00000001U |
| Read. More... | |
| #define | XNANDPSU_PROG_MUL_DIE_MASK 0x00000002U |
| Multi Die. More... | |
| #define | XNANDPSU_PROG_BLK_ERASE_MASK 0x00000004U |
| Block Erase. More... | |
| #define | XNANDPSU_PROG_RD_STS_MASK 0x00000008U |
| Read Status. More... | |
| #define | XNANDPSU_PROG_PG_PROG_MASK 0x00000010U |
| Page Program. More... | |
| #define | XNANDPSU_PROG_MUL_DIE_RD_MASK 0x00000020U |
| Multi Die Rd. More... | |
| #define | XNANDPSU_PROG_RD_ID_MASK 0x00000040U |
| Read ID. More... | |
| #define | XNANDPSU_PROG_RD_PRM_PG_MASK 0x00000080U |
| Read Param Page. More... | |
| #define | XNANDPSU_PROG_RST_MASK 0x00000100U |
| Reset. More... | |
| #define | XNANDPSU_PROG_GET_FEATURES_MASK 0x00000200U |
| Get Features. More... | |
| #define | XNANDPSU_PROG_SET_FEATURES_MASK 0x00000400U |
| Set Features. More... | |
| #define | XNANDPSU_PROG_RD_UNQ_ID_MASK 0x00000800U |
| Read Unique ID. More... | |
| #define | XNANDPSU_PROG_RD_STS_ENH_MASK 0x00001000U |
| Read Status Enhanced. More... | |
| #define | XNANDPSU_PROG_RD_INTRLVD_MASK 0x00002000U |
| Read Interleaved. More... | |
| #define | XNANDPSU_PROG_CHNG_RD_COL_ENH_MASK 0x00004000U |
| Change Read Column Enhanced. More... | |
| #define | XNANDPSU_PROG_COPY_BACK_INTRLVD_MASK 0x00008000U |
| Copy Back Interleaved. More... | |
| #define | XNANDPSU_PROG_RD_CACHE_START_MASK 0x00010000U |
| Read Cache Start. More... | |
| #define | XNANDPSU_PROG_RD_CACHE_SEQ_MASK 0x00020000U |
| Read Cache Sequential. More... | |
| #define | XNANDPSU_PROG_RD_CACHE_RAND_MASK 0x00040000U |
| Read Cache Random. More... | |
| #define | XNANDPSU_PROG_RD_CACHE_END_MASK 0x00080000U |
| Read Cache End. More... | |
| #define | XNANDPSU_PROG_SMALL_DATA_MOVE_MASK 0x00100000U |
| Small Data Move. More... | |
| #define | XNANDPSU_PROG_CHNG_ROW_ADDR_MASK 0x00200000U |
| Change Row Address. More... | |
| #define | XNANDPSU_PROG_CHNG_ROW_ADDR_END_MASK 0x00400000U |
| Change Row Address End. More... | |
| #define | XNANDPSU_PROG_RST_LUN_MASK 0x00800000U |
| Reset LUN. More... | |
| #define | XNANDPSU_PROG_PGM_PG_CLR_MASK 0x01000000U |
| Enhanced Program Page Register Clear. More... | |
| #define | XNANDPSU_PROG_VOL_SEL_MASK 0x02000000U |
| Volume Select. More... | |
| #define | XNANDPSU_PROG_ODT_CONF_MASK 0x04000000U |
| ODT Configure. More... | |
Interrupt Status Enable Register bit definitions and masks | |
| #define | XNANDPSU_INTR_STS_EN_BUFF_WR_RDY_STS_EN_MASK 0x00000001U |
| Buffer Write Ready Status Enable. More... | |
| #define | XNANDPSU_INTR_STS_EN_BUFF_RD_RDY_STS_EN_MASK 0x00000002U |
| Buffer Read Ready Status Enable. More... | |
| #define | XNANDPSU_INTR_STS_EN_TRANS_COMP_STS_EN_MASK 0x00000004U |
| Transfer Complete Status Enable. More... | |
| #define | XNANDPSU_INTR_STS_EN_MUL_BIT_ERR_STS_EN_MASK 0x00000008U |
| Multi Bit Error Status Enable. More... | |
| #define | XNANDPSU_INTR_STS_EN_ERR_INTR_STS_EN_MASK 0x00000010U |
| Single Bit Error Status Enable, BCH Detect Error Status Enable. More... | |
| #define | XNANDPSU_INTR_STS_EN_DMA_INT_STS_EN_MASK 0x00000040U |
| DMA Status Enable. More... | |
| #define | XNANDPSU_INTR_STS_EN_ERR_AHB_STS_EN_MASK 0x00000080U |
| Error AHB Status Enable. More... | |
Interrupt Signal Enable Register bit definitions and masks | |
| #define | XNANDPSU_INTR_SIG_EN_BUFF_WR_RDY_STS_EN_MASK 0x00000001U |
| Buffer Write Ready Signal Enable. More... | |
| #define | XNANDPSU_INTR_SIG_EN_BUFF_RD_RDY_STS_EN_MASK 0x00000002U |
| Buffer Read Ready Signal Enable. More... | |
| #define | XNANDPSU_INTR_SIG_EN_TRANS_COMP_STS_EN_MASK 0x00000004U |
| Transfer Complete Signal Enable. More... | |
| #define | XNANDPSU_INTR_SIG_EN_MUL_BIT_ERR_STS_EN_MASK 0x00000008U |
| Multi Bit Error Signal Enable. More... | |
| #define | XNANDPSU_INTR_SIG_EN_ERR_INTR_STS_EN_MASK 0x00000010U |
| Single Bit Error Signal Enable, BCH Detect Error Signal Enable. More... | |
| #define | XNANDPSU_INTR_SIG_EN_DMA_INT_STS_EN_MASK 0x00000040U |
| DMA Signal Enable. More... | |
| #define | XNANDPSU_INTR_SIG_EN_ERR_AHB_STS_EN_MASK 0x00000080U |
| Error AHB Signal Enable. More... | |
Interrupt Status Register bit definitions and masks | |
| #define | XNANDPSU_INTR_STS_BUFF_WR_RDY_STS_EN_MASK 0x00000001U |
| Buffer Write Ready. More... | |
| #define | XNANDPSU_INTR_STS_BUFF_RD_RDY_STS_EN_MASK 0x00000002U |
| Buffer Read Ready. More... | |
| #define | XNANDPSU_INTR_STS_TRANS_COMP_STS_EN_MASK 0x00000004U |
| Transfer Complete. More... | |
| #define | XNANDPSU_INTR_STS_MUL_BIT_ERR_STS_EN_MASK 0x00000008U |
| Multi Bit Error. More... | |
| #define | XNANDPSU_INTR_STS_ERR_INTR_STS_EN_MASK 0x00000010U |
| Single Bit Error, BCH Detect Error. More... | |
| #define | XNANDPSU_INTR_STS_DMA_INT_STS_EN_MASK 0x00000040U |
| DMA Interrupt. More... | |
| #define | XNANDPSU_INTR_STS_ERR_AHB_STS_EN_MASK 0x00000080U |
| Error AHB. More... | |
Interrupt bit definitions and masks | |
| #define | XNANDPSU_INTR_BUFF_WR_RDY_STS_EN_MASK 0x00000001U |
| Buffer Write Ready Status Enable. More... | |
| #define | XNANDPSU_INTR_BUFF_RD_RDY_STS_EN_MASK 0x00000002U |
| Buffer Read Ready Status Enable. More... | |
| #define | XNANDPSU_INTR_TRANS_COMP_STS_EN_MASK 0x00000004U |
| Transfer Complete Status Enable. More... | |
| #define | XNANDPSU_INTR_MUL_BIT_ERR_STS_EN_MASK 0x00000008U |
| Multi Bit Error Status Enable. More... | |
| #define | XNANDPSU_INTR_ERR_INTR_STS_EN_MASK 0x00000010U |
| Single Bit Error Status Enable, BCH Detect Error Status Enable. More... | |
| #define | XNANDPSU_INTR_DMA_INT_STS_EN_MASK 0x00000040U |
| DMA Status Enable. More... | |
| #define | XNANDPSU_INTR_ERR_AHB_STS_EN_MASK 0x00000080U |
| Error AHB Status Enable. More... | |
ID2 Register bit definitions and masks | |
| #define | XNANDPSU_ID2_DEVICE_ID2_MASK 0x000000FFU |
| MSB Device ID. More... | |
Flash Status Register bit definitions and masks | |
| #define | XNANDPSU_FLASH_STS_FLASH_STS_MASK 0x0000FFFFU |
| Flash Status Value. More... | |
Timing Register bit definitions and masks | |
| #define | XNANDPSU_TIMING_TCCS_TIME_MASK 0x00000003U |
| Change column setup time. More... | |
| #define | XNANDPSU_TIMING_SLOW_FAST_TCAD_MASK 0x00000004U |
| Slow/Fast device. More... | |
| #define | XNANDPSU_TIMING_DQS_BUFF_SEL_MASK 0x00000078U |
| Write/Read data transaction value. More... | |
| #define | XNANDPSU_TIMING_TADL_TIME_MASK 0x00007F80U |
| Address latch enable to Data loading time. More... | |
ECC Register bit definitions and masks | |
| #define | XNANDPSU_ECC_ADDR_MASK 0x0000FFFFU |
| ECC address. More... | |
| #define | XNANDPSU_ECC_SIZE_MASK 0x01FF0000U |
| ECC size. More... | |
| #define | XNANDPSU_ECC_HAMMING_BCH_MASK 0x02000000U |
| Hamming/BCH support. More... | |
ECC Error Count Register bit definitions and masks | |
| #define | XNANDPSU_ECC_ERR_CNT_PKT_BND_ERR_CNT_MASK 0x000000FFU |
| Packet bound error count. More... | |
| #define | XNANDPSU_ECC_ERR_CNT_PG_BND_ERR_CNT_MASK 0x0000FF00U |
| Page bound error count. More... | |
ECC Spare Command Register bit definitions and masks | |
| #define | XNANDPSU_ECC_SPR_CMD_SPR_CMD_MASK 0x000000FFU |
| ECC spare command. More... | |
| #define | XNANDPSU_ECC_SPR_CMD_ECC_ADDR_CYCLES_MASK 0x70000000U |
| Number of ECC/ spare address cycles. More... | |
Data Interface Register bit definitions and masks | |
| #define | XNANDPSU_DATA_INTF_SDR_MASK 0x00000007U |
| SDR mode. More... | |
| #define | XNANDPSU_DATA_INTF_NVDDR_MASK 0x00000038U |
| NVDDR mode. More... | |
| #define | XNANDPSU_DATA_INTF_NVDDR2_MASK 0x000001C0U |
| NVDDR2 mode. More... | |
| #define | XNANDPSU_DATA_INTF_DATA_INTF_MASK 0x00000600U |
| Data Interface. More... | |
| #define | XNANDPSU_DATA_INTF_NVDDR_SHIFT 3U |
| NVDDR mode shift. More... | |
| #define | XNANDPSU_DATA_INTF_DATA_INTF_SHIFT 9U |
| Data Interface Shift. More... | |
DMA Buffer Boundary Register bit definitions and masks | |
| #define | XNANDPSU_DMA_BUF_BND_BND_MASK 0x00000007U |
| DMA buffer boundary. More... | |
| #define | XNANDPSU_DMA_BUF_BND_4K 0x0U |
| #define | XNANDPSU_DMA_BUF_BND_8K 0x1U |
| #define | XNANDPSU_DMA_BUF_BND_16K 0x2U |
| #define | XNANDPSU_DMA_BUF_BND_32K 0x3U |
| #define | XNANDPSU_DMA_BUF_BND_64K 0x4U |
| #define | XNANDPSU_DMA_BUF_BND_128K 0x5U |
| #define | XNANDPSU_DMA_BUF_BND_256K 0x6U |
| #define | XNANDPSU_DMA_BUF_BND_512K 0x7U |
Slave DMA Configuration Register bit definitions and masks | |
| #define | XNANDPSU_SLV_DMA_CONF_SDMA_TX_RX_MASK 0x00000001U |
| Slave DMA Transfer Direction. More... | |
| #define | XNANDPSU_SLV_DMA_CONF_DMA_TRANS_CNT_MASK 0x001FFFFEU |
| Slave DMA Transfer Count. More... | |
| #define | XNANDPSU_SLV_DMA_CONF_DMA_BURST_SIZE_MASK 0x00E00000U |
| Slave DMA Burst Size. More... | |
| #define | XNANDPSU_SLV_DMA_CONF_DMA_TMOUT_CNT_VAL_MASK 0x0F000000U |
| DMA Timeout Counter Value. More... | |
| #define | XNANDPSU_SLV_DMA_CONF_SDMA_EN_MASK 0x10000000U |
| Slave DMA Enable. More... | |