Xilinx Vitis Drivers API Documentation
ospipsv Documentation

This is the header file for the implementation of OSPIPSV driver.

Ver   Who Date     Changes
--— — -----— --------------------------------------------—.
1.0   nsk  02/19/18 First release
      sk   01/09/19 Added interrupt mode support.
                    Remove STIG/DMA mode selection by the user, driver will
                    take care of operating in DMA/STIG based on command.
                    Added support for unaligned byte count read.
      sk   02/04/19 Added support for SDR+PHY and DDR+PHY modes.
      sk   02/07/19 Added OSPI Idling sequence.
1.0   akm 03/29/19 Fixed data alignment issues on IAR compiler.
1.1   sk   07/22/19 Added RX Tuning algorithm for SDR and DDR modes.
      sk   08/08/19 Added flash device reset support.
      sk   08/16/19 Set Read Delay Fld to 0x1 for Non-Phy mode.
1.2   sk   02/03/20 Added APIs for non-blocking transfer support.
      sk   02/20/20 Reorganize the source code, enable the interrupts
                    by default and updated XOspiPsv_DeviceReset() API with
                    masked data writes.
      sk   02/20/20 Make XOspiPsv_SetDllDelay() API as user API.
      sk   02/20/20 Added support for DLL Master mode.
1.3   sk   04/09/20 Added support for 64-bit address read from 32-bit proc.
      sk   05/27/20 Added support for reading C_OSPI_MODE param.
      sk  08/19/20 Reduced the usleep delay while checking transfer done.
      sk   10/06/20 Clear the ISR for polled mode transfers.
1.4   sk   02/18/21 Added support for Dual byte opcode.
      sk   02/18/21 Updated RX Tuning algorithm for Master DLL mode.
      sk   04/08/21 Fixed doxygen warnings in all source files.
      sk   05/07/21 Fixed MISRAC violations.
1.5   sk   08/17/21 Added DCache invalidate after non-blocking DMA read.
      sk   08/30/21 Limit RX maximum number of taps to 127.