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qspips
Vitis Drivers API Documentation
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qspips
Vitis Drivers API Documentation
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Macros | |
| #define | XQspiPs_ReadReg(BaseAddress, RegOffset) XQspiPs_In32((BaseAddress) + (RegOffset)) |
| Read a register. More... | |
| #define | XQspiPs_WriteReg(BaseAddress, RegOffset, RegisterValue) XQspiPs_Out32((BaseAddress) + (RegOffset), (RegisterValue)) |
| Write to a register. More... | |
Register Map | |
Register offsets from the base address of an QSPI device. | |
| #define | XQSPIPS_CR_OFFSET 0x00 |
| Configuration Register. More... | |
| #define | XQSPIPS_SR_OFFSET 0x04 |
| Interrupt Status. More... | |
| #define | XQSPIPS_IER_OFFSET 0x08 |
| Interrupt Enable. More... | |
| #define | XQSPIPS_IDR_OFFSET 0x0c |
| Interrupt Disable. More... | |
| #define | XQSPIPS_IMR_OFFSET 0x10 |
| Interrupt Enabled Mask. More... | |
| #define | XQSPIPS_ER_OFFSET 0x14 |
| Enable/Disable Register. More... | |
| #define | XQSPIPS_DR_OFFSET 0x18 |
| Delay Register. More... | |
| #define | XQSPIPS_TXD_00_OFFSET 0x1C |
| Transmit 4-byte inst/data. More... | |
| #define | XQSPIPS_RXD_OFFSET 0x20 |
| Data Receive Register. More... | |
| #define | XQSPIPS_SICR_OFFSET 0x24 |
| Slave Idle Count. More... | |
| #define | XQSPIPS_TXWR_OFFSET 0x28 |
| Transmit FIFO Watermark. More... | |
| #define | XQSPIPS_RXWR_OFFSET 0x2C |
| Receive FIFO Watermark. More... | |
| #define | XQSPIPS_GPIO_OFFSET 0x30 |
| GPIO Register. More... | |
| #define | XQSPIPS_LPBK_DLY_ADJ_OFFSET 0x38 |
| Loopback Delay Adjust Reg. More... | |
| #define | XQSPIPS_TXD_01_OFFSET 0x80 |
| Transmit 1-byte inst. More... | |
| #define | XQSPIPS_TXD_10_OFFSET 0x84 |
| Transmit 2-byte inst. More... | |
| #define | XQSPIPS_TXD_11_OFFSET 0x88 |
| Transmit 3-byte inst. More... | |
| #define | XQSPIPS_LQSPI_CR_OFFSET 0xA0 |
| Linear QSPI config register. More... | |
| #define | XQSPIPS_LQSPI_SR_OFFSET 0xA4 |
| Linear QSPI status register. More... | |
| #define | XQSPIPS_MOD_ID_OFFSET 0xFC |
| Module ID register. More... | |
Configuration Register | |
This register contains various control bits that affect the operation of the QSPI device. Read/Write. | |
| #define | XQSPIPS_CR_IFMODE_MASK 0x80000000 |
| Flash mem interface mode. More... | |
| #define | XQSPIPS_CR_ENDIAN_MASK 0x04000000 |
| Tx/Rx FIFO endianness. More... | |
| #define | XQSPIPS_CR_MANSTRT_MASK 0x00010000 |
| Manual Transmission Start. More... | |
| #define | XQSPIPS_CR_MANSTRTEN_MASK 0x00008000 |
| Manual Transmission Start Enable. More... | |
| #define | XQSPIPS_CR_SSFORCE_MASK 0x00004000 |
| Force Slave Select. More... | |
| #define | XQSPIPS_CR_SSCTRL_MASK 0x00000400 |
| Slave Select Decode. More... | |
| #define | XQSPIPS_CR_SSCTRL_SHIFT 10 |
| Slave Select Decode shift. More... | |
| #define | XQSPIPS_CR_DATA_SZ_MASK 0x000000C0 |
| Size of word to be transferred. More... | |
| #define | XQSPIPS_CR_PRESC_MASK 0x00000038 |
| Prescaler Setting. More... | |
| #define | XQSPIPS_CR_PRESC_SHIFT 3 |
| Prescaler shift. More... | |
| #define | XQSPIPS_CR_PRESC_MAXIMUM 0x07 |
| Prescaler maximum value. More... | |
| #define | XQSPIPS_CR_CPHA_MASK 0x00000004 |
| Phase Configuration. More... | |
| #define | XQSPIPS_CR_CPOL_MASK 0x00000002 |
| Polarity Configuration. More... | |
| #define | XQSPIPS_CR_MSTREN_MASK 0x00000001 |
| Master Mode Enable. More... | |
| #define | XQSPIPS_CR_HOLD_B_MASK 0x00080000 |
| HOLD_B Pin Drive Enable. More... | |
| #define | XQSPIPS_CR_REF_CLK_MASK 0x00000100 |
| Ref clk bit - should be 0. More... | |
| #define | XQSPIPS_CR_RESET_MASK_SET |
| #define | XQSPIPS_CR_RESET_MASK_CLR |
QSPI Interrupt Registers | |
QSPI Status Register This register holds the interrupt status flags for an QSPI device. Some of the flags are level triggered, which means that they are set as long as the interrupt condition exists. Other flags are edge triggered, which means they are set once the interrupt condition occurs and remain set until they are cleared by software. The interrupts are cleared by writing a '1' to the interrupt bit position in the Status Register. Read/Write. QSPI Interrupt Enable Register This register is used to enable chosen interrupts for an QSPI device. Writing a '1' to a bit in this register sets the corresponding bit in the QSPI Interrupt Mask register. Write only. QSPI Interrupt Disable Register This register is used to disable chosen interrupts for an QSPI device. Writing a '1' to a bit in this register clears the corresponding bit in the QSPI Interrupt Mask register. Write only. QSPI Interrupt Mask Register This register shows the enabled/disabled interrupts of an QSPI device. Read only. All four registers have the same bit definitions. They are only defined once for each of the Interrupt Enable Register, Interrupt Disable Register, Interrupt Mask Register, and Channel Interrupt Status Register | |
| #define | XQSPIPS_IXR_TXUF_MASK 0x00000040 |
| QSPI Tx FIFO Underflow. More... | |
| #define | XQSPIPS_IXR_RXFULL_MASK 0x00000020 |
| QSPI Rx FIFO Full. More... | |
| #define | XQSPIPS_IXR_RXNEMPTY_MASK 0x00000010 |
| QSPI Rx FIFO Not Empty. More... | |
| #define | XQSPIPS_IXR_TXFULL_MASK 0x00000008 |
| QSPI Tx FIFO Full. More... | |
| #define | XQSPIPS_IXR_TXOW_MASK 0x00000004 |
| QSPI Tx FIFO Overwater. More... | |
| #define | XQSPIPS_IXR_RXOVR_MASK 0x00000001 |
| QSPI Rx FIFO Overrun. More... | |
| #define | XQSPIPS_IXR_DFLT_MASK 0x00000025 |
| QSPI default interrupts mask. More... | |
| #define | XQSPIPS_IXR_WR_TO_CLR_MASK 0x00000041 |
| Interrupts which need write to clear. More... | |
| #define | XQSPIPS_ISR_RESET_STATE 0x00000004 |
| Default to tx/rx empty. More... | |
| #define | XQSPIPS_IXR_DISABLE_ALL 0x0000007D |
| Disable all interrupts. More... | |
Enable Register | |
This register is used to enable or disable an QSPI device. Read/Write | |
| #define | XQSPIPS_ER_ENABLE_MASK 0x00000001 |
| QSPI Enable Bit Mask. More... | |
Delay Register | |
This register is used to program timing delays in slave mode. Read/Write | |
| #define | XQSPIPS_DR_NSS_MASK 0xFF000000 |
| Delay to de-assert slave select between two words mask. More... | |
| #define | XQSPIPS_DR_NSS_SHIFT 24 |
| Delay to de-assert slave select between two words shift. More... | |
| #define | XQSPIPS_DR_BTWN_MASK 0x00FF0000 |
| Delay Between Transfers mask. More... | |
| #define | XQSPIPS_DR_BTWN_SHIFT 16 |
| Delay Between Transfers shift. More... | |
| #define | XQSPIPS_DR_AFTER_MASK 0x0000FF00 |
| Delay After Transfers mask. More... | |
| #define | XQSPIPS_DR_AFTER_SHIFT 8 |
| Delay After Transfers shift. More... | |
| #define | XQSPIPS_DR_INIT_MASK 0x000000FF |
| Delay Initially mask. More... | |
Slave Idle Count Registers | |
This register defines the number of pclk cycles the slave waits for a the QSPI clock to become stable in quiescent state before it can detect the start of the next transfer in CPHA = 1 mode. Read/Write | |
| #define | XQSPIPS_SICR_MASK 0x000000FF |
| Slave Idle Count Mask. More... | |
Transmit FIFO Watermark Register | |
This register defines the watermark setting for the Transmit FIFO. | |
| #define | XQSPIPS_TXWR_MASK 0x0000003F |
| Transmit Watermark Mask. More... | |
| #define | XQSPIPS_TXWR_RESET_VALUE 0x00000001 |
| Transmit Watermark register reset value. More... | |
Receive FIFO Watermark Register | |
This register defines the watermark setting for the Receive FIFO. | |
| #define | XQSPIPS_RXWR_MASK 0x0000003F |
| Receive Watermark Mask. More... | |
| #define | XQSPIPS_RXWR_RESET_VALUE 0x00000001 |
| Receive Watermark register reset value. More... | |
FIFO Depth | |
This macro provides the depth of transmit FIFO and receive FIFO. | |
| #define | XQSPIPS_FIFO_DEPTH 63 |
| FIFO depth (words) More... | |
Linear QSPI Configuration Register | |
This register contains various control bits that affect the operation of the Linear QSPI controller. Read/Write. | |
| #define | XQSPIPS_LQSPI_CR_LINEAR_MASK 0x80000000 |
| LQSPI mode enable. More... | |
| #define | XQSPIPS_LQSPI_CR_TWO_MEM_MASK 0x40000000 |
| Both memories or one. More... | |
| #define | XQSPIPS_LQSPI_CR_SEP_BUS_MASK 0x20000000 |
| Separate memory bus. More... | |
| #define | XQSPIPS_LQSPI_CR_U_PAGE_MASK 0x10000000 |
| Upper memory page. More... | |
| #define | XQSPIPS_LQSPI_CR_MODE_EN_MASK 0x02000000 |
| Enable mode bits. More... | |
| #define | XQSPIPS_LQSPI_CR_MODE_ON_MASK 0x01000000 |
| Mode on. More... | |
| #define | XQSPIPS_LQSPI_CR_MODE_BITS_MASK 0x00FF0000 |
| Mode value for dual I/O or quad I/O. More... | |
| #define | XQSPIPS_LQSPI_CR_DUMMY_MASK 0x00000700 |
| Number of dummy bytes between addr and return read data. More... | |
| #define | XQSPIPS_LQSPI_CR_INST_MASK 0x000000FF |
| Read instr code. More... | |
| #define | XQSPIPS_LQSPI_CR_RST_STATE 0x8000016B |
| Default CR value. More... | |
Linear QSPI Status Register | |
This register contains various status bits of the Linear QSPI controller. Read/Write. | |
| #define | XQSPIPS_LQSPI_SR_D_FSM_ERR_MASK 0x00000004 |
| AXI Data FSM Error received. More... | |
| #define | XQSPIPS_LQSPI_SR_WR_RECVD_MASK 0x00000002 |
| AXI write command received. More... | |
Loopback Delay Adjust Register | |
This register contains various bit masks of Loopback Delay Adjust Register. | |
| #define | XQSPIPS_LPBK_DLY_ADJ_USE_LPBK_MASK 0x00000020 |
| Loopback Bit. More... | |
SLCR Register | |
Bit Masks of above SLCR Registers . | |
| #define | SLCR_LOCK 0x00000004 |
| SLCR Write Protection Lock. More... | |
| #define | SLCR_UNLOCK 0x00000008 |
| SLCR Write Protection Unlock. More... | |
| #define | LQSPI_RST_CTRL 0x00000230 |
| Quad SPI Software Reset Control. More... | |
| #define | SLCR_LOCKSTA 0x0000000C |
| SLCR Write Protection status. More... | |
| #define | XPAR_XSLCR_0_BASEADDR 0xF8000000 |
| #define | SLCR_LOCK_MASK 0x767B |
| Write Protection Lock mask. More... | |
| #define | SLCR_UNLOCK_MASK 0xDF0D |
| SLCR Write Protection Unlock. More... | |
| #define | LQSPI_RST_CTRL_MASK 0x3 |
| Quad SPI Software Reset Control. More... | |
Functions | |
| void | XQspiPs_ResetHw (u32 BaseAddress) |
| Resets QSPI by disabling the device and bringing it to reset state through register writes. More... | |
| void | XQspiPs_LinearInit (u32 BaseAddress) |
| Initializes QSPI to Linear mode with default QSPI boot settings. More... | |