Data Structures
struct	XQspiPs_Config
	This typedef contains configuration information for the device. More...

struct	XQspiPs
	The XQspiPs driver instance data. More...

Macros
#define	XQspiPs_SetSlaveIdle(InstancePtr, RegisterValue)
	Set the contents of the slave idle count register. More...

#define	XQspiPs_GetSlaveIdle(InstancePtr)
	Get the contents of the slave idle count register. More...

#define	XQspiPs_SetTXWatermark(InstancePtr, RegisterValue)
	Set the contents of the transmit FIFO watermark register. More...

#define	XQspiPs_GetTXWatermark(InstancePtr) XQspiPs_In32((InstancePtr->Config.BaseAddress) + XQSPIPS_TXWR_OFFSET)
	Get the contents of the transmit FIFO watermark register. More...

#define	XQspiPs_SetRXWatermark(InstancePtr, RegisterValue)
	Set the contents of the receive FIFO watermark register. More...

#define	XQspiPs_GetRXWatermark(InstancePtr) XQspiPs_In32((InstancePtr->Config.BaseAddress) + XQSPIPS_RXWR_OFFSET)
	Get the contents of the receive FIFO watermark register. More...

#define	XQspiPs_Enable(InstancePtr)
	Enable the device and uninhibit master transactions. More...

#define	XQspiPs_Disable(InstancePtr) XQspiPs_Out32((InstancePtr->Config.BaseAddress) + XQSPIPS_ER_OFFSET, 0)
	Disable the device. More...

#define	XQspiPs_SetLqspiConfigReg(InstancePtr, RegisterValue)
	Set the contents of the Linear QSPI Configuration register. More...

#define	XQspiPs_GetLqspiConfigReg(InstancePtr)
	Get the contents of the Linear QSPI Configuration register. More...

#define	XQspiPs_ReadReg(BaseAddress, RegOffset) XQspiPs_In32((BaseAddress) + (RegOffset))
	Read a register. More...

#define	XQspiPs_WriteReg(BaseAddress, RegOffset, RegisterValue) XQspiPs_Out32((BaseAddress) + (RegOffset), (RegisterValue))
	Write to a register. More...

Typedefs
typedef void(*	XQspiPs_StatusHandler )(void *CallBackRef, u32 StatusEvent, unsigned ByteCount)
	The handler data type allows the user to define a callback function to handle the asynchronous processing for the QSPI device. More...

Functions
int	XQspiPs_CfgInitialize (XQspiPs InstancePtr, XQspiPs_Config ConfigPtr, u32 EffectiveAddr)
	Initializes a specific XQspiPs instance such that the driver is ready to use. More...

void	XQspiPs_Reset (XQspiPs *InstancePtr)
	Resets the QSPI device. More...

void	XQspiPs_Abort (XQspiPs *InstancePtr)
	Aborts a transfer in progress by disabling the device and flush the RxFIFO. More...

s32	XQspiPs_Transfer (XQspiPs InstancePtr, u8 SendBufPtr, u8 *RecvBufPtr, u32 ByteCount)
	Transfers specified data on the QSPI bus. More...

s32	XQspiPs_PolledTransfer (XQspiPs InstancePtr, u8 SendBufPtr, u8 *RecvBufPtr, u32 ByteCount)
	Transfers specified data on the QSPI bus in polled mode. More...

int	XQspiPs_LqspiRead (XQspiPs InstancePtr, u8 RecvBufPtr, u32 Address, unsigned ByteCount)
	Read the flash in Linear QSPI mode. More...

int	XQspiPs_SetSlaveSelect (XQspiPs *InstancePtr)
	Selects the slave with which the master communicates. More...

void	XQspiPs_SetStatusHandler (XQspiPs InstancePtr, void CallBackRef, XQspiPs_StatusHandler FuncPtr)
	Sets the status callback function, the status handler, which the driver calls when it encounters conditions that should be reported to upper layer software. More...

void	XQspiPs_InterruptHandler (void *InstancePtr)
	The interrupt handler for QSPI interrupts. More...

XQspiPs_Config *	XQspiPs_LookupConfig (u16 DeviceId)
	Looks up the device configuration based on the unique device ID. More...

int	XQspiPs_SelfTest (XQspiPs *InstancePtr)
	Runs a self-test on the driver/device. More...

s32	XQspiPs_SetOptions (XQspiPs *InstancePtr, u32 Options)
	This function sets the options for the QSPI device driver. More...

u32	XQspiPs_GetOptions (XQspiPs *InstancePtr)
	This function gets the options for the QSPI device. More...

s32	XQspiPs_SetClkPrescaler (XQspiPs *InstancePtr, u8 Prescaler)
	This function sets the clock prescaler for an QSPI device. More...

u8	XQspiPs_GetClkPrescaler (XQspiPs *InstancePtr)
	This function gets the clock prescaler of an QSPI device. More...

int	XQspiPs_SetDelays (XQspiPs *InstancePtr, u8 DelayNss, u8 DelayBtwn, u8 DelayAfter, u8 DelayInit)
	This function sets the delay register for the QSPI device driver. More...

void	XQspiPs_GetDelays (XQspiPs InstancePtr, u8 DelayNss, u8 DelayBtwn, u8 DelayAfter, u8 *DelayInit)
	This function gets the delay settings for an QSPI device. More...

void	XQspiPs_ResetHw (u32 BaseAddress)
	Resets QSPI by disabling the device and bringing it to reset state through register writes. More...

void	XQspiPs_LinearInit (u32 BaseAddress)
	Initializes QSPI to Linear mode with default QSPI boot settings. More...

Variables
XQspiPs_Config	XQspiPs_ConfigTable [XPAR_XQSPIPS_NUM_INSTANCES]
	This table contains configuration information for each QSPI device in the system. More...

XQspiPs_Config	XQspiPs_ConfigTable []
	This table contains configuration information for each QSPI device in the system. More...

Configuration options
The following options are supported to enable/disable certain features of an QSPI device. Each of the options is a bit mask, so more than one may be specified. The Active Low Clock option configures the device's clock polarity. Setting this option means the clock is active low and the SCK signal idles high. By default, the clock is active high and SCK idles low. The Clock Phase option configures the QSPI device for one of two transfer formats. A clock phase of 0, the default, means data is valid on the first SCK edge (rising or falling) after the slave select (SS) signal has been asserted. A clock phase of 1 means data is valid on the second SCK edge (rising or falling) after SS has been asserted. The QSPI Force Slave Select option is used to enable manual control of the slave select signal. 0: The SPI_SS signal is controlled by the QSPI controller during transfers. (Default) 1: The SPI_SS signal is forced active (driven low) regardless of any transfers in progress. NOTE: The driver will handle setting and clearing the Slave Select when the user sets the "FORCE_SSELECT_OPTION". Using this option will allow the QSPI clock to be set to a faster speed. If the QSPI clock is too fast, the processor cannot empty and refill the FIFOs before the TX FIFO is empty When the QSPI hardware is controlling the Slave Select signals, this will cause slave to be de-selected and terminate the transfer. The Manual Start option is used to enable manual control of the Start command to perform data transfer. 0: The Start command is controlled by the QSPI controller during transfers(Default). Data transmission starts as soon as there is data in the TXFIFO and stalls when the TXFIFO is empty 1: The Start command must be issued by software to perform data transfer. Bit 15 of Configuration register is used to issue Start command. This bit must be set whenever TXFIFO is filled with new data. NOTE: The driver will set the Manual Start Enable bit in Configuration Register, if Manual Start option is selected. Software will issue Manual Start command whenever TXFIFO is filled with data. When there is no further data, driver will clear the Manual Start Enable bit.
#define	XQSPIPS_CLK_ACTIVE_LOW_OPTION 0x2
	Active Low Clock option. More...

#define	XQSPIPS_CLK_PHASE_1_OPTION 0x4
	Clock Phase one option. More...

#define	XQSPIPS_FORCE_SSELECT_OPTION 0x10
	Force Slave Select. More...

#define	XQSPIPS_MANUAL_START_OPTION 0x20
	Manual Start enable. More...

#define	XQSPIPS_LQSPI_MODE_OPTION 0x80
	Linear QPSI mode. More...

#define	XQSPIPS_HOLD_B_DRIVE_OPTION 0x100
	Drive HOLD_B Pin. More...

QSPI Clock Prescaler options
The QSPI Clock Prescaler Configuration bits are used to program master mode bit rate. The bit rate can be programmed in divide-by-two decrements from pclk/2 to pclk/256.
#define	XQSPIPS_CLK_PRESCALE_2 0x00
	PCLK/2 Prescaler. More...

#define	XQSPIPS_CLK_PRESCALE_4 0x01
	PCLK/4 Prescaler. More...

#define	XQSPIPS_CLK_PRESCALE_8 0x02
	PCLK/8 Prescaler. More...

#define	XQSPIPS_CLK_PRESCALE_16 0x03
	PCLK/16 Prescaler. More...

#define	XQSPIPS_CLK_PRESCALE_32 0x04
	PCLK/32 Prescaler. More...

#define	XQSPIPS_CLK_PRESCALE_64 0x05
	PCLK/64 Prescaler. More...

#define	XQSPIPS_CLK_PRESCALE_128 0x06
	PCLK/128 Prescaler. More...

#define	XQSPIPS_CLK_PRESCALE_256 0x07
	PCLK/256 Prescaler. More...

Callback events
These constants specify the handler events that are passed to a handler from the driver. These constants are not bit masks such that only one will be passed at a time to the handler.
#define	XQSPIPS_EVENT_TRANSFER_DONE 2
	Transfer done. More...

#define	XQSPIPS_EVENT_TRANSMIT_UNDERRUN 3
	TX FIFO empty. More...

#define	XQSPIPS_EVENT_RECEIVE_OVERRUN 4
	Receive data loss because RX FIFO full. More...

Flash commands
The following constants define most of the commands supported by flash devices. Users can add more commands supported by the flash devices
#define	XQSPIPS_FLASH_OPCODE_WRSR 0x01 /* Write status register */

#define	XQSPIPS_FLASH_OPCODE_PP 0x02 /* Page program */

#define	XQSPIPS_FLASH_OPCODE_NORM_READ 0x03 /* Normal read data bytes */

#define	XQSPIPS_FLASH_OPCODE_WRDS 0x04 /* Write disable */

#define	XQSPIPS_FLASH_OPCODE_RDSR1 0x05 /* Read status register 1 */

#define	XQSPIPS_FLASH_OPCODE_WREN 0x06 /* Write enable */

#define	XQSPIPS_FLASH_OPCODE_FAST_READ 0x0B /* Fast read data bytes */

#define	XQSPIPS_FLASH_OPCODE_BE_4K 0x20 /* Erase 4KiB block */

#define	XQSPIPS_FLASH_OPCODE_RDSR2 0x35 /* Read status register 2 */

#define	XQSPIPS_FLASH_OPCODE_DUAL_READ 0x3B /* Dual read data bytes */

#define	XQSPIPS_FLASH_OPCODE_BE_32K 0x52 /* Erase 32KiB block */

#define	XQSPIPS_FLASH_OPCODE_QUAD_READ 0x6B /* Quad read data bytes */

#define	XQSPIPS_FLASH_OPCODE_ERASE_SUS 0x75 /* Erase suspend */

#define	XQSPIPS_FLASH_OPCODE_ERASE_RES 0x7A /* Erase resume */

#define	XQSPIPS_FLASH_OPCODE_RDID 0x9F /* Read JEDEC ID */

#define	XQSPIPS_FLASH_OPCODE_BE 0xC7 /* Erase whole flash block */

#define	XQSPIPS_FLASH_OPCODE_SE 0xD8 /* Sector erase (usually 64KB)*/

#define	XQSPIPS_FLASH_OPCODE_DUAL_IO_READ 0xBB /* Read data using Dual I/O */

#define	XQSPIPS_FLASH_OPCODE_QUAD_IO_READ 0xEB /* Read data using Quad I/O */

#define	XQSPIPS_FLASH_OPCODE_BRWR 0x17 /* Bank Register Write */

#define	XQSPIPS_FLASH_OPCODE_BRRD 0x16 /* Bank Register Read */

#define	XQSPIPS_FLASH_OPCODE_EARWR 0xC5

#define	XQSPIPS_FLASH_OPCODE_EARRD 0xC8

#define	XQSPIPS_FLASH_OPCODE_DIE_ERASE 0xC4

#define	XQSPIPS_FLASH_OPCODE_READ_FLAG_SR 0x70

#define	XQSPIPS_FLASH_OPCODE_CLEAR_FLAG_SR 0x50

#define	XQSPIPS_FLASH_OPCODE_READ_LOCK_REG 0xE8 /* Lock Reg Read */

#define	XQSPIPS_FLASH_OPCODE_WRITE_LOCK_REG 0xE5 /* Lock Reg Write */

Instruction size
The following constants define numbers 1 to 4. Used to identify whether TXD0,1,2 or 3 is to be used.
#define	XQSPIPS_SIZE_ONE 1

#define	XQSPIPS_SIZE_TWO 2

#define	XQSPIPS_SIZE_THREE 3

#define	XQSPIPS_SIZE_FOUR 4

ConnectionMode
The following constants are the possible values of ConnectionMode in Config structure.
#define	XQSPIPS_CONNECTION_MODE_SINGLE 0

#define	XQSPIPS_CONNECTION_MODE_STACKED 1

#define	XQSPIPS_CONNECTION_MODE_PARALLEL 2

FIFO threshold value
This is the Rx FIFO threshold (in words) that was found to be most optimal in terms of performance
#define	XQSPIPS_RXFIFO_THRESHOLD_OPT 32

Pre-scaler value for divided by 4
Pre-scaler value for divided by 4
#define	XQSPIPS_CR_PRESC_DIV_BY_4 0x01

Register Map
Register offsets from the base address of an QSPI device.
#define	XQSPIPS_CR_OFFSET 0x00
	Configuration Register. More...

#define	XQSPIPS_SR_OFFSET 0x04
	Interrupt Status. More...

#define	XQSPIPS_IER_OFFSET 0x08
	Interrupt Enable. More...

#define	XQSPIPS_IDR_OFFSET 0x0c
	Interrupt Disable. More...

#define	XQSPIPS_IMR_OFFSET 0x10
	Interrupt Enabled Mask. More...

#define	XQSPIPS_ER_OFFSET 0x14
	Enable/Disable Register. More...

#define	XQSPIPS_DR_OFFSET 0x18
	Delay Register. More...

#define	XQSPIPS_TXD_00_OFFSET 0x1C
	Transmit 4-byte inst/data. More...

#define	XQSPIPS_RXD_OFFSET 0x20
	Data Receive Register. More...

#define	XQSPIPS_SICR_OFFSET 0x24
	Slave Idle Count. More...

#define	XQSPIPS_TXWR_OFFSET 0x28
	Transmit FIFO Watermark. More...

#define	XQSPIPS_RXWR_OFFSET 0x2C
	Receive FIFO Watermark. More...

#define	XQSPIPS_GPIO_OFFSET 0x30
	GPIO Register. More...

#define	XQSPIPS_LPBK_DLY_ADJ_OFFSET 0x38
	Loopback Delay Adjust Reg. More...

#define	XQSPIPS_TXD_01_OFFSET 0x80
	Transmit 1-byte inst. More...

#define	XQSPIPS_TXD_10_OFFSET 0x84
	Transmit 2-byte inst. More...

#define	XQSPIPS_TXD_11_OFFSET 0x88
	Transmit 3-byte inst. More...

#define	XQSPIPS_LQSPI_CR_OFFSET 0xA0
	Linear QSPI config register. More...

#define	XQSPIPS_LQSPI_SR_OFFSET 0xA4
	Linear QSPI status register. More...

#define	XQSPIPS_MOD_ID_OFFSET 0xFC
	Module ID register. More...

Configuration Register
This register contains various control bits that affect the operation of the QSPI device. Read/Write.
#define	XQSPIPS_CR_IFMODE_MASK 0x80000000
	Flash mem interface mode. More...

#define	XQSPIPS_CR_ENDIAN_MASK 0x04000000
	Tx/Rx FIFO endianness. More...

#define	XQSPIPS_CR_MANSTRT_MASK 0x00010000
	Manual Transmission Start. More...

#define	XQSPIPS_CR_MANSTRTEN_MASK 0x00008000
	Manual Transmission Start Enable. More...

#define	XQSPIPS_CR_SSFORCE_MASK 0x00004000
	Force Slave Select. More...

#define	XQSPIPS_CR_SSCTRL_MASK 0x00000400
	Slave Select Decode. More...

#define	XQSPIPS_CR_SSCTRL_SHIFT 10
	Slave Select Decode shift. More...

#define	XQSPIPS_CR_DATA_SZ_MASK 0x000000C0
	Size of word to be transferred. More...

#define	XQSPIPS_CR_PRESC_MASK 0x00000038
	Prescaler Setting. More...

#define	XQSPIPS_CR_PRESC_SHIFT 3
	Prescaler shift. More...

#define	XQSPIPS_CR_PRESC_MAXIMUM 0x07
	Prescaler maximum value. More...

#define	XQSPIPS_CR_CPHA_MASK 0x00000004
	Phase Configuration. More...

#define	XQSPIPS_CR_CPOL_MASK 0x00000002
	Polarity Configuration. More...

#define	XQSPIPS_CR_MSTREN_MASK 0x00000001
	Master Mode Enable. More...

#define	XQSPIPS_CR_HOLD_B_MASK 0x00080000
	HOLD_B Pin Drive Enable. More...

#define	XQSPIPS_CR_REF_CLK_MASK 0x00000100
	Ref clk bit - should be 0. More...

#define	XQSPIPS_CR_RESET_MASK_SET

#define	XQSPIPS_CR_RESET_MASK_CLR

QSPI Interrupt Registers
QSPI Status Register This register holds the interrupt status flags for an QSPI device. Some of the flags are level triggered, which means that they are set as long as the interrupt condition exists. Other flags are edge triggered, which means they are set once the interrupt condition occurs and remain set until they are cleared by software. The interrupts are cleared by writing a '1' to the interrupt bit position in the Status Register. Read/Write. QSPI Interrupt Enable Register This register is used to enable chosen interrupts for an QSPI device. Writing a '1' to a bit in this register sets the corresponding bit in the QSPI Interrupt Mask register. Write only. QSPI Interrupt Disable Register This register is used to disable chosen interrupts for an QSPI device. Writing a '1' to a bit in this register clears the corresponding bit in the QSPI Interrupt Mask register. Write only. QSPI Interrupt Mask Register This register shows the enabled/disabled interrupts of an QSPI device. Read only. All four registers have the same bit definitions. They are only defined once for each of the Interrupt Enable Register, Interrupt Disable Register, Interrupt Mask Register, and Channel Interrupt Status Register
#define	XQSPIPS_IXR_TXUF_MASK 0x00000040
	QSPI Tx FIFO Underflow. More...

#define	XQSPIPS_IXR_RXFULL_MASK 0x00000020
	QSPI Rx FIFO Full. More...

#define	XQSPIPS_IXR_RXNEMPTY_MASK 0x00000010
	QSPI Rx FIFO Not Empty. More...

#define	XQSPIPS_IXR_TXFULL_MASK 0x00000008
	QSPI Tx FIFO Full. More...

#define	XQSPIPS_IXR_TXOW_MASK 0x00000004
	QSPI Tx FIFO Overwater. More...

#define	XQSPIPS_IXR_RXOVR_MASK 0x00000001
	QSPI Rx FIFO Overrun. More...

#define	XQSPIPS_IXR_DFLT_MASK 0x00000025
	QSPI default interrupts mask. More...

#define	XQSPIPS_IXR_WR_TO_CLR_MASK 0x00000041
	Interrupts which need write to clear. More...

#define	XQSPIPS_ISR_RESET_STATE 0x00000004
	Default to tx/rx empty. More...

#define	XQSPIPS_IXR_DISABLE_ALL 0x0000007D
	Disable all interrupts. More...

Enable Register
This register is used to enable or disable an QSPI device. Read/Write
#define	XQSPIPS_ER_ENABLE_MASK 0x00000001
	QSPI Enable Bit Mask. More...

Delay Register
This register is used to program timing delays in slave mode. Read/Write
#define	XQSPIPS_DR_NSS_MASK 0xFF000000
	Delay to de-assert slave select between two words mask. More...

#define	XQSPIPS_DR_NSS_SHIFT 24
	Delay to de-assert slave select between two words shift. More...

#define	XQSPIPS_DR_BTWN_MASK 0x00FF0000
	Delay Between Transfers mask. More...

#define	XQSPIPS_DR_BTWN_SHIFT 16
	Delay Between Transfers shift. More...

#define	XQSPIPS_DR_AFTER_MASK 0x0000FF00
	Delay After Transfers mask. More...

#define	XQSPIPS_DR_AFTER_SHIFT 8
	Delay After Transfers shift. More...

#define	XQSPIPS_DR_INIT_MASK 0x000000FF
	Delay Initially mask. More...

Slave Idle Count Registers
This register defines the number of pclk cycles the slave waits for a the QSPI clock to become stable in quiescent state before it can detect the start of the next transfer in CPHA = 1 mode. Read/Write
#define	XQSPIPS_SICR_MASK 0x000000FF
	Slave Idle Count Mask. More...

Transmit FIFO Watermark Register
This register defines the watermark setting for the Transmit FIFO.
#define	XQSPIPS_TXWR_MASK 0x0000003F
	Transmit Watermark Mask. More...

#define	XQSPIPS_TXWR_RESET_VALUE 0x00000001
	Transmit Watermark register reset value. More...

Receive FIFO Watermark Register
This register defines the watermark setting for the Receive FIFO.
#define	XQSPIPS_RXWR_MASK 0x0000003F
	Receive Watermark Mask. More...

#define	XQSPIPS_RXWR_RESET_VALUE 0x00000001
	Receive Watermark register reset value. More...

FIFO Depth
This macro provides the depth of transmit FIFO and receive FIFO.
#define	XQSPIPS_FIFO_DEPTH 63
	FIFO depth (words) More...

Linear QSPI Configuration Register
This register contains various control bits that affect the operation of the Linear QSPI controller. Read/Write.
#define	XQSPIPS_LQSPI_CR_LINEAR_MASK 0x80000000
	LQSPI mode enable. More...

#define	XQSPIPS_LQSPI_CR_TWO_MEM_MASK 0x40000000
	Both memories or one. More...

#define	XQSPIPS_LQSPI_CR_SEP_BUS_MASK 0x20000000
	Separate memory bus. More...

#define	XQSPIPS_LQSPI_CR_U_PAGE_MASK 0x10000000
	Upper memory page. More...

#define	XQSPIPS_LQSPI_CR_MODE_EN_MASK 0x02000000
	Enable mode bits. More...

#define	XQSPIPS_LQSPI_CR_MODE_ON_MASK 0x01000000
	Mode on. More...

#define	XQSPIPS_LQSPI_CR_MODE_BITS_MASK 0x00FF0000
	Mode value for dual I/O or quad I/O. More...

#define	XQSPIPS_LQSPI_CR_DUMMY_MASK 0x00000700
	Number of dummy bytes between addr and return read data. More...

#define	XQSPIPS_LQSPI_CR_INST_MASK 0x000000FF
	Read instr code. More...

#define	XQSPIPS_LQSPI_CR_RST_STATE 0x8000016B
	Default CR value. More...

Linear QSPI Status Register
This register contains various status bits of the Linear QSPI controller. Read/Write.
#define	XQSPIPS_LQSPI_SR_D_FSM_ERR_MASK 0x00000004
	AXI Data FSM Error received. More...

#define	XQSPIPS_LQSPI_SR_WR_RECVD_MASK 0x00000002
	AXI write command received. More...

Loopback Delay Adjust Register
This register contains various bit masks of Loopback Delay Adjust Register.
#define	XQSPIPS_LPBK_DLY_ADJ_USE_LPBK_MASK 0x00000020
	Loopback Bit. More...

SLCR Register
Bit Masks of above SLCR Registers .
#define	SLCR_LOCK 0x00000004
	SLCR Write Protection Lock. More...

#define	SLCR_UNLOCK 0x00000008
	SLCR Write Protection Unlock. More...

#define	LQSPI_RST_CTRL 0x00000230
	Quad SPI Software Reset Control. More...

#define	SLCR_LOCKSTA 0x0000000C
	SLCR Write Protection status. More...

#define	XPAR_XSLCR_0_BASEADDR 0xF8000000

#define	SLCR_LOCK_MASK 0x767B
	Write Protection Lock mask. More...

#define	SLCR_UNLOCK_MASK 0xDF0D
	SLCR Write Protection Unlock. More...

#define	LQSPI_RST_CTRL_MASK 0x3
	Quad SPI Software Reset Control. More...

Macro Definition Documentation

#define LQSPI_RST_CTRL 0x00000230

Quad SPI Software Reset Control.

Referenced by XQspiPs_Abort().

#define LQSPI_RST_CTRL_MASK 0x3

Quad SPI Software Reset Control.

Referenced by XQspiPs_Abort().

#define SLCR_LOCK 0x00000004

SLCR Write Protection Lock.

Referenced by XQspiPs_Abort().

#define SLCR_LOCK_MASK 0x767B

Write Protection Lock mask.

Referenced by XQspiPs_Abort().

#define SLCR_LOCKSTA 0x0000000C

SLCR Write Protection status.

Referenced by XQspiPs_Abort().

#define SLCR_UNLOCK 0x00000008

SLCR Write Protection Unlock.

Referenced by XQspiPs_Abort().

#define SLCR_UNLOCK_MASK 0xDF0D

SLCR Write Protection Unlock.

Referenced by XQspiPs_Abort().

#define XQSPIPS_CLK_ACTIVE_LOW_OPTION 0x2

Active Low Clock option.

#define XQSPIPS_CLK_PHASE_1_OPTION 0x4

Clock Phase one option.

#define XQSPIPS_CLK_PRESCALE_128 0x06

PCLK/128 Prescaler.

#define XQSPIPS_CLK_PRESCALE_16 0x03

PCLK/16 Prescaler.

#define XQSPIPS_CLK_PRESCALE_2 0x00

PCLK/2 Prescaler.

#define XQSPIPS_CLK_PRESCALE_256 0x07

PCLK/256 Prescaler.

#define XQSPIPS_CLK_PRESCALE_32 0x04

PCLK/32 Prescaler.

#define XQSPIPS_CLK_PRESCALE_4 0x01

PCLK/4 Prescaler.

#define XQSPIPS_CLK_PRESCALE_64 0x05

PCLK/64 Prescaler.

#define XQSPIPS_CLK_PRESCALE_8 0x02

PCLK/8 Prescaler.

Referenced by DualStackExample(), LinearQspiFlashExample(), QspiFlashIntrExample(), QspiFlashPolledExample(), and QspiG128FlashExample().

#define XQSPIPS_CR_CPHA_MASK 0x00000004

Phase Configuration.

#define XQSPIPS_CR_CPOL_MASK 0x00000002

Polarity Configuration.

#define XQSPIPS_CR_DATA_SZ_MASK 0x000000C0

Size of word to be transferred.

#define XQSPIPS_CR_ENDIAN_MASK 0x04000000

Tx/Rx FIFO endianness.

#define XQSPIPS_CR_HOLD_B_MASK 0x00080000

HOLD_B Pin Drive Enable.

#define XQSPIPS_CR_IFMODE_MASK 0x80000000

Flash mem interface mode.

#define XQSPIPS_CR_MANSTRT_MASK 0x00010000

Manual Transmission Start.

Referenced by XQspiPs_InterruptHandler(), XQspiPs_PolledTransfer(), and XQspiPs_Transfer().

#define XQSPIPS_CR_MANSTRTEN_MASK 0x00008000

Manual Transmission Start Enable.

#define XQSPIPS_CR_MSTREN_MASK 0x00000001

Master Mode Enable.

#define XQSPIPS_CR_OFFSET 0x00

Configuration Register.

Referenced by XQspiPs_Abort(), XQspiPs_GetClkPrescaler(), XQspiPs_GetOptions(), XQspiPs_InterruptHandler(), XQspiPs_LinearInit(), XQspiPs_PolledTransfer(), XQspiPs_Reset(), XQspiPs_ResetHw(), XQspiPs_SetClkPrescaler(), XQspiPs_SetOptions(), XQspiPs_SetSlaveSelect(), and XQspiPs_Transfer().

#define XQSPIPS_CR_PRESC_MASK 0x00000038

Prescaler Setting.

Referenced by XQspiPs_GetClkPrescaler(), XQspiPs_LinearInit(), and XQspiPs_SetClkPrescaler().

#define XQSPIPS_CR_PRESC_MAXIMUM 0x07

Prescaler maximum value.

Referenced by XQspiPs_SetClkPrescaler().

#define XQSPIPS_CR_PRESC_SHIFT 3

Prescaler shift.

Referenced by XQspiPs_GetClkPrescaler(), XQspiPs_LinearInit(), and XQspiPs_SetClkPrescaler().

#define XQSPIPS_CR_REF_CLK_MASK 0x00000100

Ref clk bit - should be 0.

#define XQSPIPS_CR_SSCTRL_MASK 0x00000400

Slave Select Decode.

Referenced by XQspiPs_Abort(), XQspiPs_InterruptHandler(), XQspiPs_LinearInit(), XQspiPs_PolledTransfer(), XQspiPs_ResetHw(), XQspiPs_SetSlaveSelect(), and XQspiPs_Transfer().

#define XQSPIPS_CR_SSCTRL_SHIFT 10

Slave Select Decode shift.

#define XQSPIPS_CR_SSFORCE_MASK 0x00004000

Force Slave Select.

Referenced by XQspiPs_Abort(), and XQspiPs_ResetHw().

#define XQspiPs_Disable ( InstancePtr ) XQspiPs_Out32((InstancePtr->Config.BaseAddress) + XQSPIPS_ER_OFFSET, 0)

Disable the device.

Parameters

InstancePtr is a pointer to the XQspiPs instance.

Returns: None.

Note: C-Style signature: void XQspiPs_Disable(XQspiPs *InstancePtr)

Referenced by XQspiPs_Abort(), XQspiPs_InterruptHandler(), XQspiPs_LqspiRead(), and XQspiPs_PolledTransfer().

#define XQSPIPS_DR_AFTER_MASK 0x0000FF00

Delay After Transfers mask.

Referenced by XQspiPs_GetDelays().

#define XQSPIPS_DR_AFTER_SHIFT 8

Delay After Transfers shift.

Referenced by XQspiPs_GetDelays(), and XQspiPs_SetDelays().

#define XQSPIPS_DR_BTWN_MASK 0x00FF0000

Delay Between Transfers mask.

Referenced by XQspiPs_GetDelays().

#define XQSPIPS_DR_BTWN_SHIFT 16

Delay Between Transfers shift.

Referenced by XQspiPs_GetDelays(), and XQspiPs_SetDelays().

#define XQSPIPS_DR_INIT_MASK 0x000000FF

Delay Initially mask.

Referenced by XQspiPs_GetDelays().

#define XQSPIPS_DR_NSS_MASK 0xFF000000

Delay to de-assert slave select between two words mask.

Referenced by XQspiPs_GetDelays().

#define XQSPIPS_DR_NSS_SHIFT 24

Delay to de-assert slave select between two words shift.

Referenced by XQspiPs_GetDelays(), and XQspiPs_SetDelays().

#define XQSPIPS_DR_OFFSET 0x18

Delay Register.

Referenced by XQspiPs_GetDelays(), and XQspiPs_SetDelays().

#define XQspiPs_Enable ( InstancePtr )

Value:

XQspiPs_Out32((InstancePtr->Config.BaseAddress) + XQSPIPS_ER_OFFSET, \

XQSPIPS_ER_ENABLE_MASK)

XQSPIPS_ER_OFFSET

#define XQSPIPS_ER_OFFSET

Enable/Disable Register.

Definition: xqspips_hw.h:71

XQSPIPS_ER_ENABLE_MASK

#define XQSPIPS_ER_ENABLE_MASK

QSPI Enable Bit Mask.

Definition: xqspips_hw.h:196

Enable the device and uninhibit master transactions.

Parameters

InstancePtr is a pointer to the XQspiPs instance.

Returns: None.

Note: C-Style signature: void XQspiPs_Enable(XQspiPs *InstancePtr)

Referenced by XQspiPs_LqspiRead(), XQspiPs_PolledTransfer(), and XQspiPs_Transfer().

#define XQSPIPS_ER_ENABLE_MASK 0x00000001

QSPI Enable Bit Mask.

Referenced by XQspiPs_LinearInit().

#define XQSPIPS_ER_OFFSET 0x14

Enable/Disable Register.

Referenced by XQspiPs_LinearInit(), and XQspiPs_ResetHw().

#define XQSPIPS_EVENT_RECEIVE_OVERRUN 4

Receive data loss because RX FIFO full.

#define XQSPIPS_EVENT_TRANSFER_DONE 2

Transfer done.

#define XQSPIPS_EVENT_TRANSMIT_UNDERRUN 3

TX FIFO empty.

#define XQSPIPS_FIFO_DEPTH 63

FIFO depth (words)

Referenced by XQspiPs_PolledTransfer(), and XQspiPs_Transfer().

#define XQSPIPS_FORCE_SSELECT_OPTION 0x10

Force Slave Select.

Referenced by DualStackExample(), LinearQspiFlashExample(), QspiFlashIntrExample(), QspiFlashPolledExample(), and QspiG128FlashExample().

#define XQspiPs_GetLqspiConfigReg ( InstancePtr )

Value:

XQspiPs_In32((InstancePtr->Config.BaseAddress) + \

XQSPIPS_LQSPI_CR_OFFSET)

XQSPIPS_LQSPI_CR_OFFSET

#define XQSPIPS_LQSPI_CR_OFFSET

Linear QSPI config register.

Definition: xqspips_hw.h:83

Get the contents of the Linear QSPI Configuration register.

Parameters

InstancePtr is a pointer to the XQspiPs instance.

Returns: A 32-bit value representing the contents of the LQSPI Config register.

Note: C-Style signature: u32 XQspiPs_GetLqspiConfigReg(u32 *InstancePtr)

Referenced by FlashErase(), GetRealAddr(), and XQspiPs_LqspiRead().

#define XQspiPs_GetRXWatermark ( InstancePtr ) XQspiPs_In32((InstancePtr->Config.BaseAddress) + XQSPIPS_RXWR_OFFSET)

Get the contents of the receive FIFO watermark register.

Valid values are in the range 1-63.

Parameters

InstancePtr is a pointer to the XQspiPs instance.

Returns: A 6-bit value representing Rx Watermark level.

Note: C-Style signature: u32 XQspiPs_GetRXWatermark(XQspiPs *InstancePtr)

#define XQspiPs_GetSlaveIdle ( InstancePtr )

Value:

XQspiPs_In32(((InstancePtr)->Config.BaseAddress) + \

XQSPIPS_SICR_OFFSET)

XQSPIPS_SICR_OFFSET

#define XQSPIPS_SICR_OFFSET

Slave Idle Count.

Definition: xqspips_hw.h:75

Get the contents of the slave idle count register.

Use the XQSPIPS_SICR_* constants defined in xqspips_hw.h to interpret the bit-mask returned.

Parameters

InstancePtr is a pointer to the XQspiPs instance.

Returns: An 8-bit value representing Slave Idle Count.

Note: C-Style signature: u32 XQspiPs_GetSlaveIdle(XQspiPs *InstancePtr)

#define XQspiPs_GetTXWatermark ( InstancePtr ) XQspiPs_In32((InstancePtr->Config.BaseAddress) + XQSPIPS_TXWR_OFFSET)

Get the contents of the transmit FIFO watermark register.

Valid values are in the range 1-63.

Parameters

InstancePtr is a pointer to the XQspiPs instance.

Returns: A 6-bit value representing Tx Watermark level.

Note: C-Style signature: u32 XQspiPs_GetTXWatermark(XQspiPs *InstancePtr)

#define XQSPIPS_GPIO_OFFSET 0x30

GPIO Register.

#define XQSPIPS_HOLD_B_DRIVE_OPTION 0x100

Drive HOLD_B Pin.

Referenced by DualStackExample(), LinearQspiFlashExample(), QspiFlashIntrExample(), QspiFlashPolledExample(), and QspiG128FlashExample().

#define XQSPIPS_IDR_OFFSET 0x0c

Interrupt Disable.

Referenced by XQspiPs_InterruptHandler(), and XQspiPs_ResetHw().

#define XQSPIPS_IER_OFFSET 0x08

Interrupt Enable.

Referenced by XQspiPs_InterruptHandler(), and XQspiPs_Transfer().

#define XQSPIPS_IMR_OFFSET 0x10

Interrupt Enabled Mask.

#define XQSPIPS_ISR_RESET_STATE 0x00000004

Default to tx/rx empty.

#define XQSPIPS_IXR_DFLT_MASK 0x00000025

QSPI default interrupts mask.

#define XQSPIPS_IXR_DISABLE_ALL 0x0000007D

Disable all interrupts.

Referenced by XQspiPs_ResetHw().

#define XQSPIPS_IXR_RXFULL_MASK 0x00000020

QSPI Rx FIFO Full.

#define XQSPIPS_IXR_RXNEMPTY_MASK 0x00000010

QSPI Rx FIFO Not Empty.

Referenced by XQspiPs_InterruptHandler(), XQspiPs_PolledTransfer(), XQspiPs_ResetHw(), and XQspiPs_Transfer().

#define XQSPIPS_IXR_RXOVR_MASK 0x00000001

QSPI Rx FIFO Overrun.

Referenced by XQspiPs_InterruptHandler(), and XQspiPs_Transfer().

#define XQSPIPS_IXR_TXFULL_MASK 0x00000008

QSPI Tx FIFO Full.

#define XQSPIPS_IXR_TXOW_MASK 0x00000004

QSPI Tx FIFO Overwater.

Referenced by XQspiPs_InterruptHandler(), XQspiPs_PolledTransfer(), and XQspiPs_Transfer().

#define XQSPIPS_IXR_TXUF_MASK 0x00000040

QSPI Tx FIFO Underflow.

Referenced by XQspiPs_InterruptHandler(), and XQspiPs_Transfer().

#define XQSPIPS_IXR_WR_TO_CLR_MASK 0x00000041

Interrupts which need write to clear.

Referenced by XQspiPs_InterruptHandler(), XQspiPs_ResetHw(), and XQspiPs_Transfer().

#define XQSPIPS_LPBK_DLY_ADJ_OFFSET 0x38

Loopback Delay Adjust Reg.

#define XQSPIPS_LPBK_DLY_ADJ_USE_LPBK_MASK 0x00000020

Loopback Bit.

#define XQSPIPS_LQSPI_CR_DUMMY_MASK 0x00000700

Number of dummy bytes between addr and return read data.

#define XQSPIPS_LQSPI_CR_INST_MASK 0x000000FF

Read instr code.

#define XQSPIPS_LQSPI_CR_LINEAR_MASK 0x80000000

LQSPI mode enable.

Referenced by XQspiPs_GetOptions(), XQspiPs_LqspiRead(), and XQspiPs_SetOptions().

#define XQSPIPS_LQSPI_CR_MODE_BITS_MASK 0x00FF0000

Mode value for dual I/O or quad I/O.

#define XQSPIPS_LQSPI_CR_MODE_EN_MASK 0x02000000

Enable mode bits.

#define XQSPIPS_LQSPI_CR_MODE_ON_MASK 0x01000000

Mode on.

#define XQSPIPS_LQSPI_CR_OFFSET 0xA0

Linear QSPI config register.

Referenced by XQspiPs_GetOptions(), XQspiPs_LinearInit(), XQspiPs_ResetHw(), and XQspiPs_SetOptions().

#define XQSPIPS_LQSPI_CR_RST_STATE 0x8000016B

Default CR value.

Referenced by XQspiPs_LinearInit(), and XQspiPs_SetOptions().

#define XQSPIPS_LQSPI_CR_SEP_BUS_MASK 0x20000000

Separate memory bus.

Referenced by XQspiPs_LinearInit().

#define XQSPIPS_LQSPI_CR_TWO_MEM_MASK 0x40000000

Both memories or one.

Referenced by XQspiPs_LinearInit().

#define XQSPIPS_LQSPI_CR_U_PAGE_MASK 0x10000000

Upper memory page.

Referenced by FlashErase(), and GetRealAddr().

#define XQSPIPS_LQSPI_MODE_OPTION 0x80

Linear QPSI mode.

Referenced by DualStackExample(), LinearQspiFlashExample(), XQspiPs_GetOptions(), and XQspiPs_SetOptions().

#define XQSPIPS_LQSPI_SR_D_FSM_ERR_MASK 0x00000004

AXI Data FSM Error received.

#define XQSPIPS_LQSPI_SR_OFFSET 0xA4

Linear QSPI status register.

#define XQSPIPS_LQSPI_SR_WR_RECVD_MASK 0x00000002

AXI write command received.

#define XQSPIPS_MANUAL_START_OPTION 0x20

Manual Start enable.

Referenced by DualStackExample(), LinearQspiFlashExample(), QspiFlashIntrExample(), QspiFlashPolledExample(), and QspiG128FlashExample().

#define XQSPIPS_MOD_ID_OFFSET 0xFC

Module ID register.

#define XQspiPs_ReadReg	(	BaseAddress,
		RegOffset
	)	XQspiPs_In32((BaseAddress) + (RegOffset))

Read a register.

Parameters

BaseAddress	contains the base address of the device.
RegOffset	contains the offset from the 1st register of the device to the target register.

Returns: The value read from the register.

Note: C-Style signature: u32 XQspiPs_ReadReg(u32 BaseAddress. int RegOffset)

Referenced by XQspiPs_Abort(), XQspiPs_GetClkPrescaler(), XQspiPs_GetDelays(), XQspiPs_GetOptions(), XQspiPs_InterruptHandler(), XQspiPs_LinearInit(), XQspiPs_PolledTransfer(), XQspiPs_Reset(), XQspiPs_ResetHw(), XQspiPs_SetClkPrescaler(), XQspiPs_SetOptions(), XQspiPs_SetSlaveSelect(), and XQspiPs_Transfer().

#define XQSPIPS_RXD_OFFSET 0x20

Data Receive Register.

Referenced by XQspiPs_InterruptHandler(), XQspiPs_PolledTransfer(), and XQspiPs_ResetHw().

#define XQSPIPS_RXWR_MASK 0x0000003F

Receive Watermark Mask.

Referenced by XQspiPs_ResetHw().

#define XQSPIPS_RXWR_OFFSET 0x2C

Receive FIFO Watermark.

Referenced by XQspiPs_Abort(), XQspiPs_InterruptHandler(), XQspiPs_PolledTransfer(), XQspiPs_ResetHw(), and XQspiPs_Transfer().

#define XQSPIPS_RXWR_RESET_VALUE 0x00000001

Receive Watermark register reset value.

Referenced by XQspiPs_Abort(), XQspiPs_InterruptHandler(), XQspiPs_PolledTransfer(), and XQspiPs_ResetHw().

#define XQspiPs_SetLqspiConfigReg	(	InstancePtr,
		RegisterValue
	)

Value:

XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + \

XQSPIPS_LQSPI_CR_OFFSET, (RegisterValue))

XQSPIPS_LQSPI_CR_OFFSET

#define XQSPIPS_LQSPI_CR_OFFSET

Linear QSPI config register.

Definition: xqspips_hw.h:83

Set the contents of the Linear QSPI Configuration register.

Parameters

InstancePtr	is a pointer to the XQspiPs instance.
RegisterValue	is the value to be written to the Linear QSPI configuration register.

Returns: None.

Note: C-Style signature: void XQspiPs_SetLqspiConfigReg(XQspiPs *InstancePtr, u32 RegisterValue)

Referenced by DualStackExample(), FlashErase(), GetRealAddr(), LinearQspiFlashExample(), and QspiG128FlashExample().

#define XQspiPs_SetRXWatermark	(	InstancePtr,
		RegisterValue
	)

Value:

XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + \

XQSPIPS_RXWR_OFFSET, (RegisterValue))

XQSPIPS_RXWR_OFFSET

#define XQSPIPS_RXWR_OFFSET

Receive FIFO Watermark.

Definition: xqspips_hw.h:77

Set the contents of the receive FIFO watermark register.

Parameters

InstancePtr	is a pointer to the XQspiPs instance.
RegisterValue	is the value to be written, valid values are 1-63.

Returns: None.

Note: C-Style signature: void XQspiPs_SetRXWatermark(XQspiPs *InstancePtr, u32 RegisterValue)

#define XQspiPs_SetSlaveIdle	(	InstancePtr,
		RegisterValue
	)

Value:

XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + \

XQSPIPS_SICR_OFFSET, (RegisterValue))

XQSPIPS_SICR_OFFSET

#define XQSPIPS_SICR_OFFSET

Slave Idle Count.

Definition: xqspips_hw.h:75

Set the contents of the slave idle count register.

Parameters

InstancePtr	is a pointer to the XQspiPs instance.
RegisterValue	is the value to be written, valid values are 0-255.

Returns: None

Note: C-Style signature: void XQspiPs_SetSlaveIdle(XQspiPs *InstancePtr, u32 RegisterValue)

#define XQspiPs_SetTXWatermark	(	InstancePtr,
		RegisterValue
	)

Value:

XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + \

XQSPIPS_TXWR_OFFSET, (RegisterValue))

XQSPIPS_TXWR_OFFSET

#define XQSPIPS_TXWR_OFFSET

Transmit FIFO Watermark.

Definition: xqspips_hw.h:76

Set the contents of the transmit FIFO watermark register.

Parameters

InstancePtr	is a pointer to the XQspiPs instance.
RegisterValue	is the value to be written, valid values are 1-63.

Returns: None.

Note: C-Style signature: void XQspiPs_SetTXWatermark(XQspiPs *InstancePtr, u32 RegisterValue)

#define XQSPIPS_SICR_MASK 0x000000FF

Slave Idle Count Mask.

#define XQSPIPS_SICR_OFFSET 0x24

Slave Idle Count.

#define XQSPIPS_SR_OFFSET 0x04

Interrupt Status.

Referenced by XQspiPs_InterruptHandler(), XQspiPs_PolledTransfer(), XQspiPs_ResetHw(), and XQspiPs_Transfer().

#define XQSPIPS_TXD_00_OFFSET 0x1C

Transmit 4-byte inst/data.

Referenced by XQspiPs_InterruptHandler(), XQspiPs_PolledTransfer(), and XQspiPs_Transfer().

#define XQSPIPS_TXD_01_OFFSET 0x80

Transmit 1-byte inst.

Referenced by XQspiPs_PolledTransfer(), and XQspiPs_Transfer().

#define XQSPIPS_TXD_10_OFFSET 0x84

Transmit 2-byte inst.

Referenced by XQspiPs_PolledTransfer(), and XQspiPs_Transfer().

#define XQSPIPS_TXD_11_OFFSET 0x88

Transmit 3-byte inst.

Referenced by XQspiPs_PolledTransfer(), and XQspiPs_Transfer().

#define XQSPIPS_TXWR_MASK 0x0000003F

Transmit Watermark Mask.

Referenced by XQspiPs_ResetHw().

#define XQSPIPS_TXWR_OFFSET 0x28

Transmit FIFO Watermark.

Referenced by XQspiPs_Abort(), and XQspiPs_ResetHw().

#define XQSPIPS_TXWR_RESET_VALUE 0x00000001

Transmit Watermark register reset value.

Referenced by XQspiPs_Abort(), and XQspiPs_ResetHw().

#define XQspiPs_WriteReg	(	BaseAddress,
		RegOffset,
		RegisterValue
	)	XQspiPs_Out32((BaseAddress) + (RegOffset), (RegisterValue))

Write to a register.

Parameters

BaseAddress	contains the base address of the device.
RegOffset	contains the offset from the 1st register of the device to target register.
RegisterValue	is the value to be written to the register.

Returns: None.

Note: C-Style signature: void XQspiPs_WriteReg(u32 BaseAddress, int RegOffset, u32 RegisterValue)

Referenced by XQspiPs_Abort(), XQspiPs_InterruptHandler(), XQspiPs_LinearInit(), XQspiPs_PolledTransfer(), XQspiPs_Reset(), XQspiPs_ResetHw(), XQspiPs_SetClkPrescaler(), XQspiPs_SetDelays(), XQspiPs_SetOptions(), XQspiPs_SetSlaveSelect(), and XQspiPs_Transfer().

Typedef Documentation

typedef void(* XQspiPs_StatusHandler)(void *CallBackRef, u32 StatusEvent, unsigned ByteCount)

The handler data type allows the user to define a callback function to handle the asynchronous processing for the QSPI device.

The application using this driver is expected to define a handler of this type to support interrupt driven mode. The handler executes in an interrupt context, so only minimal processing should be performed.

Parameters

CallBackRef	is the callback reference passed in by the upper layer when setting the callback functions, and passed back to the upper layer when the callback is invoked. Its type is not important to the driver, so it is a void pointer.
StatusEvent	holds one or more status events that have occurred. See the XQspiPs_SetStatusHandler() for details on the status events that can be passed in the callback.
ByteCount	indicates how many bytes of data were successfully transferred. This may be less than the number of bytes requested if the status event indicates an error.

Function Documentation

void XQspiPs_Abort ( XQspiPs * InstancePtr )

Aborts a transfer in progress by disabling the device and flush the RxFIFO.

The byte counts are cleared, the busy flag is cleared.

Parameters

InstancePtr is a pointer to the XQspiPs instance.

Returns: None.

Note

This function does a read/modify/write of the config register. The user of this function needs to take care of critical sections.

References XQspiPs_Config::BaseAddress, XQspiPs::Config, XQspiPs::IsBusy, LQSPI_RST_CTRL, LQSPI_RST_CTRL_MASK, XQspiPs::RemainingBytes, XQspiPs::RequestedBytes, SLCR_LOCK, SLCR_LOCK_MASK, SLCR_LOCKSTA, SLCR_UNLOCK, SLCR_UNLOCK_MASK, XQSPIPS_CR_OFFSET, XQSPIPS_CR_SSCTRL_MASK, XQSPIPS_CR_SSFORCE_MASK, XQspiPs_Disable, XQspiPs_ReadReg, XQSPIPS_RXWR_OFFSET, XQSPIPS_RXWR_RESET_VALUE, XQSPIPS_TXWR_OFFSET, XQSPIPS_TXWR_RESET_VALUE, and XQspiPs_WriteReg.

Referenced by XQspiPs_Reset().

int XQspiPs_CfgInitialize	(	XQspiPs *	InstancePtr,
		XQspiPs_Config *	ConfigPtr,
		u32	EffectiveAddr
	)

Initializes a specific XQspiPs instance such that the driver is ready to use.

The state of the device after initialization is:

Master mode
Active high clock polarity
Clock phase 0
Baud rate divisor 2
Transfer width 32
Master reference clock = pclk
No chip select active
Manual CS and Manual Start disabled

Parameters

InstancePtr	is a pointer to the XQspiPs instance.
ConfigPtr	is a reference to a structure containing information about a specific QSPI device. This function initializes an InstancePtr object for a specific device specified by the contents of Config.
EffectiveAddr	is the device base address in the virtual memory address space. The caller is responsible for keeping the address mapping from EffectiveAddr to the device physical base address unchanged once this function is invoked. Unexpected errors may occur if the address mapping changes after this function is called. If address translation is not used, use ConfigPtr->Config.BaseAddress for this device.

Returns

XST_SUCCESS if successful.
XST_DEVICE_IS_STARTED if the device is already started. It must be stopped to re-initialize.

Note: None.

References XQspiPs_Config::BaseAddress, XQspiPs::Config, XQspiPs_Config::ConnectionMode, XQspiPs::IsBusy, XQspiPs::IsReady, XQspiPs::RecvBufferPtr, XQspiPs::RemainingBytes, XQspiPs::RequestedBytes, XQspiPs::SendBufferPtr, and XQspiPs_Reset().

Referenced by DualStackExample(), LinearQspiFlashExample(), QspiFlashIntrExample(), QspiFlashPolledExample(), QspiG128FlashExample(), and QspiPsSelfTestExample().

u8 XQspiPs_GetClkPrescaler ( XQspiPs * InstancePtr )

This function gets the clock prescaler of an QSPI device.

Parameters

InstancePtr is a pointer to the XQspiPs instance.

Returns: The prescaler value.

Note: None.

References XQspiPs_Config::BaseAddress, XQspiPs::Config, XQspiPs::IsReady, XQSPIPS_CR_OFFSET, XQSPIPS_CR_PRESC_MASK, XQSPIPS_CR_PRESC_SHIFT, and XQspiPs_ReadReg.

void XQspiPs_GetDelays	(	XQspiPs *	InstancePtr,
		u8 *	DelayNss,
		u8 *	DelayBtwn,
		u8 *	DelayAfter,
		u8 *	DelayInit
	)

This function gets the delay settings for an QSPI device.

The delay register controls the Delay Between Transfers, Delay After Transfers, and the Delay Initially. The default value is 0x0.

Parameters

InstancePtr	is a pointer to the XQspiPs instance.
DelayNss	is a pointer to the Delay to de-assert slave select between two word transfers.
DelayBtwn	is a pointer to the Delay Between transfers value. This is a return parameter.
DelayAfter	is a pointer to the Delay After transfer value. This is a return parameter.
DelayInit	is a pointer to the Delay Initially value. This is a return parameter.

Returns: None.

Note: None.

References XQspiPs_Config::BaseAddress, XQspiPs::Config, XQspiPs::IsReady, XQSPIPS_DR_AFTER_MASK, XQSPIPS_DR_AFTER_SHIFT, XQSPIPS_DR_BTWN_MASK, XQSPIPS_DR_BTWN_SHIFT, XQSPIPS_DR_INIT_MASK, XQSPIPS_DR_NSS_MASK, XQSPIPS_DR_NSS_SHIFT, XQSPIPS_DR_OFFSET, and XQspiPs_ReadReg.

Referenced by XQspiPs_SelfTest().

u32 XQspiPs_GetOptions ( XQspiPs * InstancePtr )

This function gets the options for the QSPI device.

The options control how the device behaves relative to the QSPI bus.

Parameters

InstancePtr is a pointer to the XQspiPs instance.

Returns

Options contains the specified options currently set. This is a bit value where a 1 means the option is on, and a 0 means the option is off. See the bit definitions named XQSPIPS_*_OPTIONS in file xqspips.h.

Note: None.

References XQspiPs_Config::BaseAddress, XQspiPs::Config, XQspiPs::IsReady, XQSPIPS_CR_OFFSET, XQSPIPS_LQSPI_CR_LINEAR_MASK, XQSPIPS_LQSPI_CR_OFFSET, XQSPIPS_LQSPI_MODE_OPTION, and XQspiPs_ReadReg.

void XQspiPs_InterruptHandler ( void * InstancePtr )

The interrupt handler for QSPI interrupts.

This function must be connected by the user to an interrupt controller.

The interrupts that are handled are:

Data Transmit Register (FIFO) Empty. This interrupt is generated when the transmit register or FIFO is empty. The driver uses this interrupt during a transmission to continually send/receive data until the transfer is done.
Data Transmit Register (FIFO) Underflow. This interrupt is generated when the QSPI device, when configured as a slave, attempts to read an empty DTR/FIFO. An empty DTR/FIFO usually means that software is not giving the device data in a timely manner. No action is taken by the driver other than to inform the upper layer software of the error.
Data Receive Register (FIFO) Overflow. This interrupt is generated when the QSPI device attempts to write a received byte to an already full DRR/FIFO. A full DRR/FIFO usually means software is not emptying the data in a timely manner. No action is taken by the driver other than to inform the upper layer software of the error.

Parameters

InstancePtr is a pointer to the XQspiPs instance.

Returns: None.

Note

The slave select register is being set to deselect the slave when a transfer is complete.

References XQspiPs_Config::BaseAddress, XQspiPs::Config, XQspiPs::IsBusy, XQspiPs::IsReady, XQspiPs::RecvBufferPtr, XQspiPs::RemainingBytes, XQspiPs::RequestedBytes, XQspiPs::SendBufferPtr, XQspiPs::StatusRef, XQSPIPS_CR_MANSTRT_MASK, XQSPIPS_CR_OFFSET, XQSPIPS_CR_SSCTRL_MASK, XQspiPs_Disable, XQSPIPS_IDR_OFFSET, XQSPIPS_IER_OFFSET, XQSPIPS_IXR_RXNEMPTY_MASK, XQSPIPS_IXR_RXOVR_MASK, XQSPIPS_IXR_TXOW_MASK, XQSPIPS_IXR_TXUF_MASK, XQSPIPS_IXR_WR_TO_CLR_MASK, XQspiPs_ReadReg, XQSPIPS_RXD_OFFSET, XQSPIPS_RXWR_OFFSET, XQSPIPS_RXWR_RESET_VALUE, XQSPIPS_SR_OFFSET, XQSPIPS_TXD_00_OFFSET, and XQspiPs_WriteReg.

Referenced by QspiFlashIntrExample().

void XQspiPs_LinearInit ( u32 BaseAddress )

Initializes QSPI to Linear mode with default QSPI boot settings.

Parameters

BaseAddress

Returns: None.

Note: None.

References XQSPIPS_CR_OFFSET, XQSPIPS_CR_PRESC_MASK, XQSPIPS_CR_PRESC_SHIFT, XQSPIPS_CR_SSCTRL_MASK, XQSPIPS_ER_ENABLE_MASK, XQSPIPS_ER_OFFSET, XQSPIPS_LQSPI_CR_OFFSET, XQSPIPS_LQSPI_CR_RST_STATE, XQSPIPS_LQSPI_CR_SEP_BUS_MASK, XQSPIPS_LQSPI_CR_TWO_MEM_MASK, XQspiPs_ReadReg, and XQspiPs_WriteReg.

XQspiPs_Config * XQspiPs_LookupConfig ( u16 DeviceId )

Looks up the device configuration based on the unique device ID.

A table contains the configuration info for each device in the system.

Parameters

DeviceId contains the ID of the device to look up the configuration for.

Returns

A pointer to the configuration found or NULL if the specified device ID was not found. See xqspips.h for the definition of XQspiPs_Config.

Note: None.

Referenced by DualStackExample(), LinearQspiFlashExample(), QspiFlashIntrExample(), QspiFlashPolledExample(), QspiG128FlashExample(), and QspiPsSelfTestExample().

int XQspiPs_LqspiRead	(	XQspiPs *	InstancePtr,
		u8 *	RecvBufPtr,
		u32	Address,
		unsigned	ByteCount
	)

Read the flash in Linear QSPI mode.

Parameters

InstancePtr	is a pointer to the XQspiPs instance.
RecvBufPtr	is a pointer to a buffer for received data.
Address	is the starting address within the flash from from where data needs to be read.
ByteCount	contains the number of bytes to receive.

Returns

XST_SUCCESS if read is performed
XST_FAILURE if Linear mode is not set

Note: None.

References XQspiPs::IsReady, XQspiPs_Disable, XQspiPs_Enable, XQspiPs_GetLqspiConfigReg, and XQSPIPS_LQSPI_CR_LINEAR_MASK.

Referenced by DualStackExample(), and LinearQspiFlashExample().

s32 XQspiPs_PolledTransfer	(	XQspiPs *	InstancePtr,
		u8 *	SendBufPtr,
		u8 *	RecvBufPtr,
		u32	ByteCount
	)

Transfers specified data on the QSPI bus in polled mode.

The caller has the option of providing two different buffers for send and receive, or one buffer for both send and receive, or no buffer for receive. The receive buffer must be at least as big as the send buffer to prevent unwanted memory writes. This implies that the byte count passed in as an argument must be the smaller of the two buffers if they differ in size. Here are some sample usages:

  XQspiPs_PolledTransfer(InstancePtr, SendBuf, RecvBuf, ByteCount)
      The caller wishes to send and receive, and provides two different
      buffers for send and receive.

  XQspiPs_PolledTransfer(InstancePtr, SendBuf, NULL, ByteCount)
      The caller wishes only to send and does not care about the received
      data. The driver ignores the received data in this case.

  XQspiPs_PolledTransfer(InstancePtr, SendBuf, SendBuf, ByteCount)
      The caller wishes to send and receive, but provides the same buffer
      for doing both. The driver sends the data and overwrites the send
      buffer with received data as it transfers the data.

  XQspiPs_PolledTransfer(InstancePtr, RecvBuf, RecvBuf, ByteCount)
      The caller wishes to only receive and does not care about sending
      data.  In this case, the caller must still provide a send buffer, but
      it can be the same as the receive buffer if the caller does not care
      what it sends.  The device must send N bytes of data if it wishes to
      receive N bytes of data.

Parameters

InstancePtr	is a pointer to the XQspiPs instance.
SendBufPtr	is a pointer to a data buffer that needs to be transmitted. This buffer must not be NULL.
RecvBufPtr	is a pointer to a buffer for received data. This argument can be NULL if do not care about receiving.
ByteCount	contains the number of bytes to send/receive. The number of bytes received always equals the number of bytes sent.

Returns

XST_SUCCESS if the buffers are successfully handed off to the device for transfer.
XST_DEVICE_BUSY indicates that a data transfer is already in progress. This is determined by the driver.

Note

This function is not thread-safe. The higher layer software must ensure that no two threads are transferring data on the QSPI bus at the same time.

References XQspiPs_Config::BaseAddress, XQspiPs::Config, XQspiPs::IsBusy, XQspiPs::IsReady, XQspiPs::RecvBufferPtr, XQspiPs::RemainingBytes, XQspiPs::RequestedBytes, XQspiPs::SendBufferPtr, XQspiPs::ShiftReadData, XQSPIPS_CR_MANSTRT_MASK, XQSPIPS_CR_OFFSET, XQSPIPS_CR_SSCTRL_MASK, XQspiPs_Disable, XQspiPs_Enable, XQSPIPS_FIFO_DEPTH, XQSPIPS_IXR_RXNEMPTY_MASK, XQSPIPS_IXR_TXOW_MASK, XQspiPs_ReadReg, XQSPIPS_RXD_OFFSET, XQSPIPS_RXWR_OFFSET, XQSPIPS_RXWR_RESET_VALUE, XQSPIPS_SR_OFFSET, XQSPIPS_TXD_00_OFFSET, XQSPIPS_TXD_01_OFFSET, XQSPIPS_TXD_10_OFFSET, XQSPIPS_TXD_11_OFFSET, and XQspiPs_WriteReg.

Referenced by BulkErase(), DieErase(), FlashErase(), FlashQuadEnable(), FlashRead(), FlashReadID(), FlashWrite(), and SendBankSelect().

void XQspiPs_Reset ( XQspiPs * InstancePtr )

Resets the QSPI device.

Reset must only be called after the driver has been initialized. Any data transfer that is in progress is aborted.

The upper layer software is responsible for re-configuring (if necessary) and restarting the QSPI device after the reset.

Parameters

InstancePtr is a pointer to the XQspiPs instance.

Returns: None.

Note: None.

References XQspiPs_Config::BaseAddress, XQspiPs::Config, XQspiPs::IsReady, XQspiPs_Abort(), XQSPIPS_CR_OFFSET, XQspiPs_ReadReg, and XQspiPs_WriteReg.

Referenced by XQspiPs_CfgInitialize(), and XQspiPs_SelfTest().

void XQspiPs_ResetHw ( u32 BaseAddress )

Resets QSPI by disabling the device and bringing it to reset state through register writes.

Parameters

BaseAddress

Returns: None.

Note: None.

References XQSPIPS_CR_OFFSET, XQSPIPS_CR_SSCTRL_MASK, XQSPIPS_CR_SSFORCE_MASK, XQSPIPS_ER_OFFSET, XQSPIPS_IDR_OFFSET, XQSPIPS_IXR_DISABLE_ALL, XQSPIPS_IXR_RXNEMPTY_MASK, XQSPIPS_IXR_WR_TO_CLR_MASK, XQSPIPS_LQSPI_CR_OFFSET, XQspiPs_ReadReg, XQSPIPS_RXD_OFFSET, XQSPIPS_RXWR_MASK, XQSPIPS_RXWR_OFFSET, XQSPIPS_RXWR_RESET_VALUE, XQSPIPS_SR_OFFSET, XQSPIPS_TXWR_MASK, XQSPIPS_TXWR_OFFSET, XQSPIPS_TXWR_RESET_VALUE, and XQspiPs_WriteReg.

int XQspiPs_SelfTest ( XQspiPs * InstancePtr )

Runs a self-test on the driver/device.

The self-test is destructive in that a reset of the device is performed in order to check the reset values of the registers and to get the device into a known state.

Upon successful return from the self-test, the device is reset.

Parameters

InstancePtr is a pointer to the XQspiPs instance.

Returns

XST_SUCCESS if successful

XST_REGISTER_ERROR indicates a register did not read or write correctly.

Note: None.

References XQspiPs::IsReady, XQspiPs_GetDelays(), XQspiPs_Reset(), and XQspiPs_SetDelays().

Referenced by DualStackExample(), LinearQspiFlashExample(), QspiFlashIntrExample(), QspiFlashPolledExample(), QspiG128FlashExample(), and QspiPsSelfTestExample().

s32 XQspiPs_SetClkPrescaler	(	XQspiPs *	InstancePtr,
		u8	Prescaler
	)

This function sets the clock prescaler for an QSPI device.

The device must be idle rather than busy transferring data before setting these device options.

Parameters

InstancePtr	is a pointer to the XQspiPs instance.
Prescaler	is the value that determine how much the clock should be divided by. Use the XQSPIPS_CLK_PRESCALE_* constants defined in xqspips.h for this setting.

Returns

XST_SUCCESS if options are successfully set.
XST_DEVICE_BUSY if the device is currently transferring data. The transfer must complete or be aborted before setting options.

Note: This function is not thread-safe.

References XQspiPs_Config::BaseAddress, XQspiPs::Config, XQspiPs::IsBusy, XQspiPs::IsReady, XQSPIPS_CR_OFFSET, XQSPIPS_CR_PRESC_MASK, XQSPIPS_CR_PRESC_MAXIMUM, XQSPIPS_CR_PRESC_SHIFT, XQspiPs_ReadReg, and XQspiPs_WriteReg.

Referenced by DualStackExample(), LinearQspiFlashExample(), QspiFlashIntrExample(), QspiFlashPolledExample(), and QspiG128FlashExample().

int XQspiPs_SetDelays	(	XQspiPs *	InstancePtr,
		u8	DelayNss,
		u8	DelayBtwn,
		u8	DelayAfter,
		u8	DelayInit
	)

This function sets the delay register for the QSPI device driver.

The delay register controls the Delay Between Transfers, Delay After Transfers, and the Delay Initially. The default value is 0x0. The range of each delay value is 0-255.

Parameters

InstancePtr	is a pointer to the XQspiPs instance.
DelayNss	is the delay to de-assert slave select between two word transfers.
DelayBtwn	is the delay between one Slave Select being de-activated and the activation of another slave. The delay is the number of master clock periods given by DelayBtwn + 2.
DelayAfter	define the delay between the last bit of the current byte transfer and the first bit of the next byte transfer. The delay in number of master clock periods is given as: CHPA=0:DelayInit+DelayAfter+3 CHPA=1:DelayAfter+1
DelayInit	is the delay between asserting the slave select signal and the first bit transfer. The delay int number of master clock periods is DelayInit+1.

Returns

XST_SUCCESS if delays are successfully set.
XST_DEVICE_BUSY if the device is currently transferring data. The transfer must complete or be aborted before setting options.

Note: None.

References XQspiPs_Config::BaseAddress, XQspiPs::Config, XQspiPs::IsBusy, XQspiPs::IsReady, XQSPIPS_DR_AFTER_SHIFT, XQSPIPS_DR_BTWN_SHIFT, XQSPIPS_DR_NSS_SHIFT, XQSPIPS_DR_OFFSET, and XQspiPs_WriteReg.

Referenced by XQspiPs_SelfTest().

s32 XQspiPs_SetOptions	(	XQspiPs *	InstancePtr,
		u32	Options
	)

This function sets the options for the QSPI device driver.

The options control how the device behaves relative to the QSPI bus. The device must be idle rather than busy transferring data before setting these device options.

Parameters

InstancePtr	is a pointer to the XQspiPs instance.
Options	contains the specified options to be set. This is a bit mask where a 1 means to turn the option on, and a 0 means to turn the option off. One or more bit values may be contained in the mask. See the bit definitions named XQSPIPS_*_OPTIONS in the file xqspips.h.

Returns

XST_SUCCESS if options are successfully set.
XST_DEVICE_BUSY if the device is currently transferring data. The transfer must complete or be aborted before setting options.

Note: This function is not thread-safe.

References XQspiPs_Config::BaseAddress, XQspiPs::Config, XQspiPs::IsBusy, XQspiPs::IsReady, XQSPIPS_CR_OFFSET, XQSPIPS_LQSPI_CR_LINEAR_MASK, XQSPIPS_LQSPI_CR_OFFSET, XQSPIPS_LQSPI_CR_RST_STATE, XQSPIPS_LQSPI_MODE_OPTION, XQspiPs_ReadReg, XQspiPs_SetSlaveSelect(), and XQspiPs_WriteReg.

Referenced by DualStackExample(), LinearQspiFlashExample(), QspiFlashIntrExample(), QspiFlashPolledExample(), and QspiG128FlashExample().

int XQspiPs_SetSlaveSelect ( XQspiPs * InstancePtr )

Selects the slave with which the master communicates.

The user is not allowed to select the slave while a transfer is in progress.

Parameters

InstancePtr is a pointer to the XQspiPs instance.

Returns

XST_SUCCESS if the slave is selected or deselected successfully.
XST_DEVICE_BUSY if a transfer is in progress, slave cannot be changed.

Note

This function only sets the slave which will be selected when a transfer occurs. The slave is not selected when the QSPI is idle.

References XQspiPs_Config::BaseAddress, XQspiPs::Config, XQspiPs::IsBusy, XQspiPs::IsReady, XQSPIPS_CR_OFFSET, XQSPIPS_CR_SSCTRL_MASK, XQspiPs_ReadReg, and XQspiPs_WriteReg.

Referenced by DualStackExample(), FlashErase(), GetRealAddr(), LinearQspiFlashExample(), QspiFlashIntrExample(), QspiFlashPolledExample(), QspiG128FlashExample(), and XQspiPs_SetOptions().

void XQspiPs_SetStatusHandler	(	XQspiPs *	InstancePtr,
		void *	CallBackRef,
		XQspiPs_StatusHandler	FuncPtr
	)

Sets the status callback function, the status handler, which the driver calls when it encounters conditions that should be reported to upper layer software.

The handler executes in an interrupt context, so it must minimize the amount of processing performed. One of the following status events is passed to the status handler.

XST_SPI_TRANSFER_DONE           The requested data transfer is done

XST_SPI_TRANSMIT_UNDERRUN       As a slave device, the master clocked data
                        but there were none available in the transmit
                        register/FIFO. This typically means the slave
                        application did not issue a transfer request
                        fast enough, or the processor/driver could not
                        fill the transmit register/FIFO fast enough.

XST_SPI_RECEIVE_OVERRUN The QSPI device lost data. Data was received
                        but the receive data register/FIFO was full.

Parameters

InstancePtr	is a pointer to the XQspiPs instance.
CallBackRef	is the upper layer callback reference passed back when the callback function is invoked.
FuncPtr	is the pointer to the callback function.

Returns: None.

Note

The handler is called within interrupt context, so it should do its work quickly and queue potentially time-consuming work to a task-level thread.

References XQspiPs::IsReady, and XQspiPs::StatusRef.

Referenced by QspiFlashIntrExample().

s32 XQspiPs_Transfer	(	XQspiPs *	InstancePtr,
		u8 *	SendBufPtr,
		u8 *	RecvBufPtr,
		u32	ByteCount
	)

Transfers specified data on the QSPI bus.

Initiates bus communication and sends/receives data to/from the selected QSPI slave. For every byte sent, a byte is received.

The caller has the option of providing two different buffers for send and receive, or one buffer for both send and receive, or no buffer for receive. The receive buffer must be at least as big as the send buffer to prevent unwanted memory writes. This implies that the byte count passed in as an argument must be the smaller of the two buffers if they differ in size. Here are some sample usages:

  XQspiPs_Transfer(InstancePtr, SendBuf, RecvBuf, ByteCount)
      The caller wishes to send and receive, and provides two different
      buffers for send and receive.

  XQspiPs_Transfer(InstancePtr, SendBuf, NULL, ByteCount)
      The caller wishes only to send and does not care about the received
      data. The driver ignores the received data in this case.

  XQspiPs_Transfer(InstancePtr, SendBuf, SendBuf, ByteCount)
      The caller wishes to send and receive, but provides the same buffer
      for doing both. The driver sends the data and overwrites the send
      buffer with received data as it transfers the data.

  XQspiPs_Transfer(InstancePtr, RecvBuf, RecvBuf, ByteCount)
      The caller wishes to only receive and does not care about sending
      data.  In this case, the caller must still provide a send buffer, but
      it can be the same as the receive buffer if the caller does not care
      what it sends.  The device must send N bytes of data if it wishes to
      receive N bytes of data.

Although this function takes entire buffers as arguments, the driver can only transfer a limited number of bytes at a time, limited by the size of the FIFO. A call to this function only starts the transfer, then subsequent transfers of the data is performed by the interrupt service routine until the entire buffer has been transferred. The status callback function is called when the entire buffer has been sent/received.

This function is non-blocking. The SetSlaveSelect function must be called prior to this function.

Parameters

InstancePtr	is a pointer to the XQspiPs instance.
SendBufPtr	is a pointer to a data buffer that needs to be transmitted. This buffer must not be NULL.
RecvBufPtr	is a pointer to a buffer for received data. This argument can be NULL if do not care about receiving.
ByteCount	contains the number of bytes to send/receive. The number of bytes received always equals the number of bytes sent.

Returns

XST_SUCCESS if the buffers are successfully handed off to the device for transfer.
XST_DEVICE_BUSY indicates that a data transfer is already in progress. This is determined by the driver.

Note

This function is not thread-safe. The higher layer software must ensure that no two threads are transferring data on the QSPI bus at the same time.

References XQspiPs_Config::BaseAddress, XQspiPs::Config, XQspiPs::IsBusy, XQspiPs::IsReady, XQspiPs::RecvBufferPtr, XQspiPs::RemainingBytes, XQspiPs::RequestedBytes, XQspiPs::SendBufferPtr, XQspiPs::ShiftReadData, XQSPIPS_CR_MANSTRT_MASK, XQSPIPS_CR_OFFSET, XQSPIPS_CR_SSCTRL_MASK, XQspiPs_Enable, XQSPIPS_FIFO_DEPTH, XQSPIPS_IER_OFFSET, XQSPIPS_IXR_RXNEMPTY_MASK, XQSPIPS_IXR_RXOVR_MASK, XQSPIPS_IXR_TXOW_MASK, XQSPIPS_IXR_TXUF_MASK, XQSPIPS_IXR_WR_TO_CLR_MASK, XQspiPs_ReadReg, XQSPIPS_RXWR_OFFSET, XQSPIPS_SR_OFFSET, XQSPIPS_TXD_00_OFFSET, XQSPIPS_TXD_01_OFFSET, XQSPIPS_TXD_10_OFFSET, XQSPIPS_TXD_11_OFFSET, and XQspiPs_WriteReg.

Referenced by FlashRead().

Variable Documentation

XQspiPs_Config XQspiPs_ConfigTable[]

This table contains configuration information for each QSPI device in the system.

XQspiPs_Config XQspiPs_ConfigTable[XPAR_XQSPIPS_NUM_INSTANCES]

Initial value:

= {
        {
                XPAR_XQSPIPS_0_DEVICE_ID, 
                XPAR_XQSPIPS_0_BASEADDR,  
                XPAR_XQSPIPS_0_QSPI_CLK_FREQ_HZ,
                XPAR_XQSPIPS_0_QSPI_MODE
        },
}

This table contains configuration information for each QSPI device in the system.

Data Structures

Macros

Typedefs

Functions

Variables

Configuration options

QSPI Clock Prescaler options

Callback events

Flash commands

Instruction size

ConnectionMode

FIFO threshold value

Pre-scaler value for divided by 4

Register Map

Configuration Register

QSPI Interrupt Registers

Enable Register

Delay Register

Slave Idle Count Registers

Transmit FIFO Watermark Register

Receive FIFO Watermark Register

FIFO Depth

Linear QSPI Configuration Register

Linear QSPI Status Register

Loopback Delay Adjust Register

SLCR Register

Macro Definition Documentation

Typedef Documentation

Function Documentation

Variable Documentation