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resetps
Vitis Drivers API Documentation
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The Xilinx Reset Controller driver supports the following features:
This driver is intended to be RTOS and processor independent. It works with physical addresses only. Any needs for dynamic memory management, threads or thread mutual exclusion, virtual memory, or cache control must be satisfied by the layer above this driver.
MODIFICATION HISTORY: Ver Who Date Changes
1.00 cjp 09/05/17 First release 1.1 Nava 04/20/18 Fixed compilation warnings. 1.2 cjp 04/27/18 Updated for clockps interdependency 1.2 sd 07/20/18 Fixed Doxygen Reported warnings. 1.4 sk 09/01/20 Updated the Makefile to support parallel make execution. 1.5 sk 11/30/21 Fix compilation warnings reported with "-Wundef" flag. 1.6 sd 07/07/23 Added SDT support. 1.7 sd 11/07/23 Remove the unused pss ref frequency