This section explains the implementation of the XSdPs driver.See xsdps.h for a detailed description of the device and driver.

This driver is used initialize read from and write to the SD card. Features such as switching bus width to 4-bit and switching to high speed, changing clock frequency, block size etc. are supported. SD 2.0 uses 1/4 bus width and speeds of 25/50KHz. Initialization, however is done using 1-bit bus width and 400KHz clock frequency. SD commands are classified as broadcast and addressed. Commands can be those with response only (using only command line) or response + data (using command and data lines). Only one command can be sent at a time. During a data transfer however, when dsta lines are in use, certain commands (which use only the command line) can be sent, most often to obtain status. This driver does not support multi card slots at present.

Initialization & Configuration

This includes initialization on the host controller side to select clock frequency, bus power and default transfer related parameters. The default voltage is 3.3V. On the SD card side, the initialization and identification state diagram is implemented. This resets the card, gives it a unique address/ID and identifies key card related specifications.

Data transfer

The SD card is put in transfer state to read from or write to it. The default block size is 512 bytes and if supported, default bus width is 4-bit and bus speed is High speed. The read and write functions are implemented in polled mode using ADMA2.

At any point, when key parameters such as block size or clock/speed or bus width are modified, this driver takes care of maintaining the same selection on host and card. All error bits in host controller are monitored by the driver and in the event one of them is set, driver will clear the interrupt status and communicate failure to the upper layer.

File system use

This driver can be used with xilffs library to read and write files to SD. (Please refer to procedure in diskio.c). The file system read/write example in polled mode can used for reference.

There is no example for using SD driver without file system at present. However, the driver can be used without the file system. The glue layer in filesystem can be used as reference for the same. The block count passed to the read/write function in one call is limited by the ADMA2 descriptor table and hence care will have to be taken to call read/write API's in a loop for large file sizes.

Interrupt mode is not supported because it offers no improvement when used with file system.

eMMC support

SD driver supports SD and eMMC based on the "enable MMC" parameter in SDK. The features of eMMC supported by the driver will depend on those supported by the host controller. The current driver supports read/write on eMMC card using 4-bit and high speed mode currently.

Features not supported include - card write protect, password setting, lock/unlock, interrupts, SDMA mode, programmed I/O mode and 64-bit addressed ADMA2, erase/pre-erase commands.

MODIFICATION HISTORY:

Ver Who Date Changes

1.00a hk/sg 10/17/13 Initial release 2.0 hk 03/07/14 Version number revised. 2.1 hk 04/18/14 Increase sleep for eMMC switch command. Add sleep for microblaze designs. CR# 781117. 2.2 hk 07/28/14 Make changes to enable use of data cache. 2.3 sk 09/23/14 Send command for relative card address when re-initialization is done.CR# 819614. Use XSdPs_Change_ClkFreq API whenever changing clock.CR# 816586. 2.4 sk 12/04/14 Added support for micro SD without WP/CD. CR# 810655. Checked for DAT Inhibit mask instead of CMD Inhibit mask in Cmd Transfer API. Added Support for SD Card v1.0 2.5 sg 07/09/15 Added SD 3.0 features kvn 07/15/15 Modified the code according to MISRAC-2012. 2.6 sk 10/12/15 Added support for SD card v1.0 CR# 840601. 2.7 sk 11/24/15 Considered the slot type befoe checking CD/WP pins. sk 12/10/15 Added support for MMC cards. 01/08/16 Added workaround for issue in auto tuning mode of SDR50, SDR104 and HS200. sk 02/16/16 Corrected the Tuning logic. sk 03/01/16 Removed Bus Width check for eMMC. CR# 938311. 2.8 sk 04/20/16 Added new workaround for auto tuning. 05/03/16 Standard Speed for SD to 19MHz in ZynqMPSoC. CR#951024 3.0 sk 06/09/16 Added support for mkfs to calculate sector count. sk 07/16/16 Added support for UHS modes. sk 07/07/16 Used usleep API for both arm and microblaze. sk 07/16/16 Added Tap delays accordingly to different SD/eMMC operating modes. sk 08/13/16 Removed sleep.h from xsdps.h as a temporary fix for CR#956899. 3.1 mi 09/07/16 Removed compilation warnings with extra compiler flags. sk 10/13/16 Reduced the delay during power cycle to 1ms as per spec sk 10/19/16 Used emmc_hwreset pin to reset eMMC. sk 11/07/16 Enable Rst_n bit in ext_csd reg if not enabled. sk 11/16/16 Issue DLL reset at 31 iteration to load new zero value. 3.2 sk 11/30/16 Modified the voltage switching sequence as per spec. sk 02/01/17 Added HSD and DDR mode support for eMMC. sk 02/01/17 Consider bus width parameter from design for switching vns 02/09/17 Added ARMA53_32 support for ZynqMP CR#968397 sk 03/20/17 Add support for EL1 non-secure mode. 3.3 mn 05/17/17 Add support for 64bit DMA addressing mn 08/07/17 Modify driver to support 64-bit DMA in arm64 only mn 08/17/17 Enabled CCI support for A53 by adding cache coherency information. mn 09/06/17 Resolved compilation errors with IAR toolchain 3.6 mn 08/01/18 Add support for using 64Bit DMA with 32-Bit Processor 3.7 mn 02/01/19 Add support for idling of SDIO 3.8 mn 04/12/19 Modified TapDelay code for supporting ZynqMP and Versal mn 09/17/19 Modified ADMA handling API for 32bit and 64bit addresses 3.9 mn 03/03/20 Restructured the code for more readability and modularity mn 03/16/20 Move XSdPs_Select_Card API to User APIs 3.10 mn 06/05/20 Check Transfer completion separately from XSdPs_Read and XSdPs_Write APIs mn 06/05/20 Modified code for SD Non-Blocking Read support 3.11 sk 12/01/20 Tap programming sequence updates like disable OTAPEN always, write zero to tap register for zero tap value. sk 12/07/20 Fix eMMC DDR52 mode write/read issue. sk 12/17/20 Removed checking platform specific SD macros and used Baseaddress instead. 3.12 sk 01/28/21 Added support for non-blocking write. sk 02/12/21 Fix the issue in reading CID and CSD. sk 04/08/21 Fixed doxygen warnings in all source files. sk 05/25/21 Fix the compilation issue in Cortex-A72 + EL1_NS by removing the DLL reset logic (Dead code for Versal). 3.13 sk 08/10/21 Limit the SD operating frequency to 19MHz for Versal. 3.14 sk 10/22/21 Add support for Erase feature. sk 11/29/21 Fix compilation warnings reported with "-Wundef" flag. sk 01/10/22 Add support to read slot_type parameter. 4.0 sk 02/25/22 Add support for eMMC5.1. sk 04/07/22 Add support to read custom tap delay values from design for SD/eMMC. sk 06/03/22 Fix issue in internal clock divider calculation logic. 4.1 sk 11/10/22 Add SD/eMMC Tap delay support for Versal Net. 4.1 sa 01/03/23 Report error if Transfer size is greater than 2MB. 4.1 sa 12/19/22 Enable eMMC HS400 mode for Versal Net. sa 01/25/23 Use instance structure to store DMA descriptor tables. 4.2 ro 06/12/23 Added support for system device-tree flow. 4.2 ap 08/09/23 Reordered XSdPs_FrameCmd XSdPs_Identify_UhsMode functions