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spips
Vitis Drivers API Documentation
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spips
Vitis Drivers API Documentation
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Macros | |
| #define | XSpiPs_ReadReg(BaseAddress, RegOffset) XSpiPs_In32((BaseAddress) + (RegOffset)) |
| Read a register. More... | |
| #define | XSpiPs_WriteReg(BaseAddress, RegOffset, RegisterValue) XSpiPs_Out32((BaseAddress) + (RegOffset), (RegisterValue)) |
| Write to a register. More... | |
Register Map | |
Register offsets from the base address of an SPI device. | |
| #define | XSPIPS_CR_OFFSET 0x00U |
| Configuration. More... | |
| #define | XSPIPS_SR_OFFSET 0x04U |
| Interrupt Status. More... | |
| #define | XSPIPS_IER_OFFSET 0x08U |
| Interrupt Enable. More... | |
| #define | XSPIPS_IDR_OFFSET 0x0CU |
| Interrupt Disable. More... | |
| #define | XSPIPS_IMR_OFFSET 0x10U |
| Interrupt Enabled Mask. More... | |
| #define | XSPIPS_ER_OFFSET 0x14U |
| Enable/Disable Register. More... | |
| #define | XSPIPS_DR_OFFSET 0x18U |
| Delay Register. More... | |
| #define | XSPIPS_TXD_OFFSET 0x1CU |
| Data Transmit Register. More... | |
| #define | XSPIPS_RXD_OFFSET 0x20U |
| Data Receive Register. More... | |
| #define | XSPIPS_SICR_OFFSET 0x24U |
| Slave Idle Count. More... | |
| #define | XSPIPS_TXWR_OFFSET 0x28U |
| Transmit FIFO Watermark. More... | |
| #define | XSPIPS_RXWR_OFFSET 0x2CU |
| Receive FIFO Watermark. More... | |
Configuration Register | |
This register contains various control bits that affects the operation of an SPI device. Read/Write. | |
| #define | XSPIPS_CR_MODF_GEN_EN_MASK 0x00020000U |
| Modefail Generation Enable. More... | |
| #define | XSPIPS_CR_MANSTRT_MASK 0x00010000U |
| Manual Transmission Start. More... | |
| #define | XSPIPS_CR_MANSTRTEN_MASK 0x00008000U |
| Manual Transmission Start Enable. More... | |
| #define | XSPIPS_CR_SSFORCE_MASK 0x00004000U |
| Force Slave Select. More... | |
| #define | XSPIPS_CR_SSCTRL_MASK 0x00003C00U |
| Slave Select Decode. More... | |
| #define | XSPIPS_CR_SSCTRL_SHIFT 10U |
| Slave Select Decode shift. More... | |
| #define | XSPIPS_CR_SSCTRL_MAXIMUM 0xFU |
| Slave Select maximum value. More... | |
| #define | XSPIPS_CR_SSDECEN_MASK 0x00000200U |
| Slave Select Decode Enable. More... | |
| #define | XSPIPS_CR_PRESC_MASK 0x00000038U |
| Prescaler Setting. More... | |
| #define | XSPIPS_CR_PRESC_SHIFT 3U |
| Prescaler shift. More... | |
| #define | XSPIPS_CR_PRESC_MAXIMUM 0x07U |
| Prescaler maximum value. More... | |
| #define | XSPIPS_CR_CPHA_MASK 0x00000004U |
| Phase Configuration. More... | |
| #define | XSPIPS_CR_CPOL_MASK 0x00000002U |
| Polarity Configuration. More... | |
| #define | XSPIPS_CR_MSTREN_MASK 0x00000001U |
| Master Mode Enable. More... | |
| #define | XSPIPS_CR_RESET_STATE 0x00020000U |
| Mode Fail Generation Enable. More... | |
SPI Interrupt Registers | |
SPI Status Register This register holds the interrupt status flags for an SPI device. Some of the flags are level triggered, which means that they are set as long as the interrupt condition exists. Other flags are edge triggered, which means they are set once the interrupt condition occurs and remain set until they are cleared by software. The interrupts are cleared by writing a '1' to the interrupt bit position in the Status Register. Read/Write. SPI Interrupt Enable Register This register is used to enable chosen interrupts for an SPI device. Writing a '1' to a bit in this register sets the corresponding bit in the SPI Interrupt Mask register. Write only. SPI Interrupt Disable Register This register is used to disable chosen interrupts for an SPI device. Writing a '1' to a bit in this register clears the corresponding bit in the SPI Interrupt Mask register. Write only. SPI Interrupt Mask Register This register shows the enabled/disabled interrupts of an SPI device. Read only. All four registers have the same bit definitions. They are only defined once for each of the Interrupt Enable Register, Interrupt Disable Register, Interrupt Mask Register, and Channel Interrupt Status Register | |
| #define | XSPIPS_IXR_TXUF_MASK 0x00000040U |
| Tx FIFO Underflow. More... | |
| #define | XSPIPS_IXR_RXFULL_MASK 0x00000020U |
| Rx FIFO Full. More... | |
| #define | XSPIPS_IXR_RXNEMPTY_MASK 0x00000010U |
| Rx FIFO Not Empty. More... | |
| #define | XSPIPS_IXR_TXFULL_MASK 0x00000008U |
| Tx FIFO Full. More... | |
| #define | XSPIPS_IXR_TXOW_MASK 0x00000004U |
| Tx FIFO Overwater. More... | |
| #define | XSPIPS_IXR_MODF_MASK 0x00000002U |
| Mode Fault. More... | |
| #define | XSPIPS_IXR_RXOVR_MASK 0x00000001U |
| Rx FIFO Overrun. More... | |
| #define | XSPIPS_IXR_DFLT_MASK 0x00000027U |
| Default interrupts mask. More... | |
| #define | XSPIPS_IXR_WR_TO_CLR_MASK 0x00000043U |
| Interrupts which need write to clear. More... | |
| #define | XSPIPS_ISR_RESET_STATE 0x04U |
| Default to tx/rx reg empty. More... | |
| #define | XSPIPS_IXR_DISABLE_ALL_MASK 0x00000043U |
| Disable all interrupts. More... | |
Enable Register | |
This register is used to enable or disable an SPI device. Read/Write | |
| #define | XSPIPS_ER_ENABLE_MASK 0x00000001U |
| SPI Enable Bit Mask. More... | |
Delay Register | |
This register is used to program timing delays in slave mode. Read/Write | |
| #define | XSPIPS_DR_NSS_MASK 0xFF000000U |
| Delay for slave select de-assertion between word transfers mask. More... | |
| #define | XSPIPS_DR_NSS_SHIFT 24U |
| Delay for slave select de-assertion between word transfers shift. More... | |
| #define | XSPIPS_DR_BTWN_MASK 0x00FF0000U |
| Delay Between Transfers mask. More... | |
| #define | XSPIPS_DR_BTWN_SHIFT 16U |
| Delay Between Transfers shift. More... | |
| #define | XSPIPS_DR_AFTER_MASK 0x0000FF00U |
| Delay After Transfers mask. More... | |
| #define | XSPIPS_DR_AFTER_SHIFT 8U |
| Delay After Transfers shift. More... | |
| #define | XSPIPS_DR_INIT_MASK 0x000000FFU |
| Delay Initially mask. More... | |
Slave Idle Count Registers | |
This register defines the number of pclk cycles the slave waits for a the SPI clock to become stable in quiescent state before it can detect the start of the next transfer in CPHA = 1 mode. Read/Write | |
| #define | XSPIPS_SICR_MASK 0x000000FFU |
| Slave Idle Count Mask. More... | |
Transmit FIFO Watermark Register | |
This register defines the watermark setting for the Transmit FIFO. The transmit FIFO is 128 bytes deep, so the register is 7 bits. Valid values are 1 to 128. | |
| #define | XSPIPS_TXWR_MASK 0x0000007FU |
| Transmit Watermark Mask. More... | |
| #define | XSPIPS_TXWR_RESET_VALUE 0x00000001U |
| Transmit Watermark register reset value. More... | |
Receive FIFO Watermark Register | |
This register defines the watermark setting for the Receive FIFO. The receive FIFO is 128 bytes deep, so the register is 7 bits. Valid values are 1 to 128. | |
| #define | XSPIPS_RXWR_MASK 0x0000007FU |
| Receive Watermark Mask. More... | |
| #define | XSPIPS_RXWR_RESET_VALUE 0x00000001U |
| Receive Watermark register reset value. More... | |
FIFO Depth | |
This macro provides the depth of transmit FIFO and receive FIFO. | |
| #define | XSPIPS_FIFO_DEPTH 128U |
| FIFO depth of Tx and Rx. More... | |
Functions | |
| void | XSpiPs_ResetHw (u32 BaseAddress) |
| Resets the spi module. More... | |