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ttcps
Vitis Drivers API Documentation
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ttcps
Vitis Drivers API Documentation
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Macros | |
| #define | XTtcPs_ReadReg(BaseAddress, RegOffset) (Xil_In32((BaseAddress) + (u32)(RegOffset))) |
| Read the given Timer Counter register. More... | |
| #define | XTtcPs_WriteReg(BaseAddress, RegOffset, Data) (Xil_Out32((BaseAddress) + (u32)(RegOffset), (u32)(Data))) |
| Write the given Timer Counter register. More... | |
| #define | XTtcPs_Match_N_Offset(MatchIndex) ((u32)XTTCPS_MATCH_0_OFFSET + ((u32)(12U) * (u32)(MatchIndex))) |
| Calculate a match register offset using the Match Register index. More... | |
Register Map | |
Register offsets from the base address of the device. | |
| #define | XTTCPS_CLK_CNTRL_OFFSET 0x00000000U |
| Clock Control Register. More... | |
| #define | XTTCPS_CNT_CNTRL_OFFSET 0x0000000CU |
| Counter Control Register. More... | |
| #define | XTTCPS_COUNT_VALUE_OFFSET 0x00000018U |
| Current Counter Value. More... | |
| #define | XTTCPS_INTERVAL_VAL_OFFSET 0x00000024U |
| Interval Count Value. More... | |
| #define | XTTCPS_MATCH_0_OFFSET 0x00000030U |
| Match 1 value. More... | |
| #define | XTTCPS_MATCH_1_OFFSET 0x0000003CU |
| Match 2 value. More... | |
| #define | XTTCPS_MATCH_2_OFFSET 0x00000048U |
| Match 3 value. More... | |
| #define | XTTCPS_ISR_OFFSET 0x00000054U |
| Interrupt Status Register. More... | |
| #define | XTTCPS_IER_OFFSET 0x00000060U |
| Interrupt Enable Register. More... | |
Clock Control Register | |
Clock Control Register definitions | |
| #define | XTTCPS_CLK_CNTRL_PS_EN_MASK 0x00000001U |
| Prescale enable. More... | |
| #define | XTTCPS_CLK_CNTRL_PS_VAL_MASK 0x0000001EU |
| Prescale value. More... | |
| #define | XTTCPS_CLK_CNTRL_PS_VAL_SHIFT 1U |
| Prescale shift. More... | |
| #define | XTTCPS_CLK_CNTRL_PS_DISABLE 16U |
| Prescale disable. More... | |
| #define | XTTCPS_CLK_CNTRL_SRC_MASK 0x00000020U |
| Clock source. More... | |
| #define | XTTCPS_CLK_CNTRL_EXT_EDGE_MASK 0x00000040U |
| External Clock edge. More... | |
Counter Control Register | |
Counter Control Register definitions | |
| #define | XTTCPS_CNT_CNTRL_DIS_MASK 0x00000001U |
| Disable the counter. More... | |
| #define | XTTCPS_CNT_CNTRL_INT_MASK 0x00000002U |
| Interval mode. More... | |
| #define | XTTCPS_CNT_CNTRL_DECR_MASK 0x00000004U |
| Decrement mode. More... | |
| #define | XTTCPS_CNT_CNTRL_MATCH_MASK 0x00000008U |
| Match mode. More... | |
| #define | XTTCPS_CNT_CNTRL_RST_MASK 0x00000010U |
| Reset counter. More... | |
| #define | XTTCPS_CNT_CNTRL_EN_WAVE_MASK 0x00000020U |
| Enable waveform. More... | |
| #define | XTTCPS_CNT_CNTRL_POL_WAVE_MASK 0x00000040U |
| Waveform polarity. More... | |
| #define | XTTCPS_CNT_CNTRL_RESET_VALUE 0x00000021U |
| Reset value. More... | |
Current Counter Value Register | |
Current Counter Value Register definitions | |
| #define | XTTCPS_COUNT_VALUE_MASK 0x0000FFFFU |
| 16-bit counter value More... | |
Interval Value Register | |
Interval Value Register is the maximum value the counter will count up or down to. | |
| #define | XTTCPS_INTERVAL_VAL_MASK 0x0000FFFFU |
| 16-bit Interval value More... | |
Match Registers | |
Definitions for Match registers, each timer counter has three match registers. | |
| #define | XTTCPS_MATCH_MASK 0x0000FFFFU |
| 16-bit Match value More... | |
| #define | XTTCPS_NUM_MATCH_REG 3U |
| Num of Match reg. More... | |
Interrupt Registers | |
Following register bit mask is for all interrupt registers. | |
| #define | XTTCPS_IXR_INTERVAL_MASK 0x00000001U |
| Interval Interrupt. More... | |
| #define | XTTCPS_IXR_MATCH_0_MASK 0x00000002U |
| Match 1 Interrupt. More... | |
| #define | XTTCPS_IXR_MATCH_1_MASK 0x00000004U |
| Match 2 Interrupt. More... | |
| #define | XTTCPS_IXR_MATCH_2_MASK 0x00000008U |
| Match 3 Interrupt. More... | |
| #define | XTTCPS_IXR_CNT_OVR_MASK 0x00000010U |
| Counter Overflow. More... | |
| #define | XTTCPS_IXR_ALL_MASK 0x0000001FU |
| All valid Interrupts. More... | |