Data Structures
struct	XTtcPs_Config
	This typedef contains configuration information for the device. More...

struct	XTtcPs
	The XTtcPs driver instance data. More...

Macros
#define	XTtcPs_Start(InstancePtr)
	This function starts the counter/timer without resetting the counter value. More...

#define	XTtcPs_Stop(InstancePtr)
	This function stops the counter/timer. More...

#define	XTtcPs_IsStarted(InstancePtr)
	This function checks whether the timer counter has already started. More...

#define	XTtcPs_GetCounterValue(InstancePtr) (u16)InstReadReg((InstancePtr), XTTCPS_COUNT_VALUE_OFFSET)
	This function returns the current 16-bit counter value. More...

#define	XTtcPs_SetInterval(InstancePtr, Value) InstWriteReg((InstancePtr), XTTCPS_INTERVAL_VAL_OFFSET, (Value))
	This function sets the interval value to be used in interval mode. More...

#define	XTtcPs_GetInterval(InstancePtr) (u16)InstReadReg((InstancePtr), XTTCPS_INTERVAL_VAL_OFFSET)
	This function gets the interval value from the interval register. More...

#define	XTtcPs_ResetCounterValue(InstancePtr)
	This macro resets the count register. More...

#define	XTtcPs_EnableInterrupts(InstancePtr, InterruptMask)
	This function enables the interrupts. More...

#define	XTtcPs_DisableInterrupts(InstancePtr, InterruptMask)
	This function disables the interrupts. More...

#define	XTtcPs_GetInterruptStatus(InstancePtr) InstReadReg((InstancePtr), XTTCPS_ISR_OFFSET)
	This function reads the interrupt status. More...

#define	XTtcPs_ClearInterruptStatus(InstancePtr, InterruptMask)
	This function clears the interrupt status. More...

#define	XTtcPs_ReadReg(BaseAddress, RegOffset) (Xil_In32((BaseAddress) + (u32)(RegOffset)))
	Read the given Timer Counter register. More...

#define	XTtcPs_WriteReg(BaseAddress, RegOffset, Data) (Xil_Out32((BaseAddress) + (u32)(RegOffset), (u32)(Data)))
	Write the given Timer Counter register. More...

#define	XTtcPs_Match_N_Offset(MatchIndex) ((u32)XTTCPS_MATCH_0_OFFSET + ((u32)(12U) * (u32)(MatchIndex)))
	Calculate a match register offset using the Match Register index. More...

Typedefs
typedef u16	XInterval
	This typedef contains interval count and Match register value. More...

Functions
s32	XTtcPs_CfgInitialize (XTtcPs InstancePtr, XTtcPs_Config ConfigPtr, u32 EffectiveAddr)
	Initializes a specific XTtcPs instance such that the driver is ready to use. More...

u32	XTtcPs_Release (XTtcPs *InstancePtr)
	This routine releases resources of XTtcPs instance/driver. More...

void	XTtcPs_SetMatchValue (XTtcPs *InstancePtr, u8 MatchIndex, XMatchRegValue Value)
	This function is used to set the match registers. More...

XMatchRegValue	XTtcPs_GetMatchValue (XTtcPs *InstancePtr, u8 MatchIndex)
	This function is used to get the value of the match registers. More...

void	XTtcPs_SetPrescaler (XTtcPs *InstancePtr, u8 PrescalerValue)
	This function sets the prescaler enable bit and if needed sets the prescaler bits in the control register. More...

u8	XTtcPs_GetPrescaler (XTtcPs *InstancePtr)
	This function gets the input clock prescaler. More...

void	XTtcPs_CalcIntervalFromFreq (XTtcPs InstancePtr, u32 Freq, XInterval Interval, u8 *Prescaler)
	This function calculates the interval value as well as the prescaler value for a given frequency. More...

u32	XTtcPs_InterruptHandler (XTtcPs *InstancePtr)
	Handles interrupts by resetting the counter value and clearing the status register. More...

void	XTtcPs_SetStatusHandler (XTtcPs InstancePtr, void CallBackRef, XTtcPs_StatusHandler FuncPointer)
	Sets the status callback function, the status handler, which the driver calls when it encounters conditions that should be reported to upper layer software. More...

XTtcPs_Config *	XTtcPs_LookupConfig (u16 DeviceId)
	Looks up the device configuration based on the unique device ID. More...

s32	XTtcPs_SetOptions (XTtcPs *InstancePtr, u32 Options)
	This function sets the options for the TTC device. More...

u32	XTtcPs_GetOptions (XTtcPs *InstancePtr)
	This function gets the settings for the options for the TTC device. More...

s32	XTtcPs_SelfTest (XTtcPs *InstancePtr)
	Runs a self-test on the driver/device. More...

Variables
XTtcPs_Config	XTtcPs_ConfigTable [XPAR_XTTCPS_NUM_INSTANCES]
	This table contains configuration information for each TTC device in the system. More...

XTtcPs_Config	XTtcPs_ConfigTable [XPAR_XTTCPS_NUM_INSTANCES]
	This table contains configuration information for each TTC device in the system. More...

Configuration options
Options for the device. Each of the options is bit field, so more than one options can be specified.
#define	XTTCPS_OPTION_EXTERNAL_CLK 0x00000001U
	External clock source. More...

#define	XTTCPS_OPTION_CLK_EDGE_NEG 0x00000002U
	Clock on trailing edge for external clock. More...

#define	XTTCPS_OPTION_INTERVAL_MODE 0x00000004U
	Interval mode. More...

#define	XTTCPS_OPTION_DECREMENT 0x00000008U
	Decrement the counter. More...

#define	XTTCPS_OPTION_MATCH_MODE 0x00000010U
	Match mode. More...

#define	XTTCPS_OPTION_WAVE_DISABLE 0x00000020U
	No waveform output. More...

#define	XTTCPS_OPTION_WAVE_POLARITY 0x00000040U
	Waveform polarity. More...

Register Map
Register offsets from the base address of the device.
#define	XTTCPS_CLK_CNTRL_OFFSET 0x00000000U
	Clock Control Register. More...

#define	XTTCPS_CNT_CNTRL_OFFSET 0x0000000CU
	Counter Control Register. More...

#define	XTTCPS_COUNT_VALUE_OFFSET 0x00000018U
	Current Counter Value. More...

#define	XTTCPS_INTERVAL_VAL_OFFSET 0x00000024U
	Interval Count Value. More...

#define	XTTCPS_MATCH_0_OFFSET 0x00000030U
	Match 1 value. More...

#define	XTTCPS_MATCH_1_OFFSET 0x0000003CU
	Match 2 value. More...

#define	XTTCPS_MATCH_2_OFFSET 0x00000048U
	Match 3 value. More...

#define	XTTCPS_ISR_OFFSET 0x00000054U
	Interrupt Status Register. More...

#define	XTTCPS_IER_OFFSET 0x00000060U
	Interrupt Enable Register. More...

Clock Control Register
Clock Control Register definitions
#define	XTTCPS_CLK_CNTRL_PS_EN_MASK 0x00000001U
	Prescale enable. More...

#define	XTTCPS_CLK_CNTRL_PS_VAL_MASK 0x0000001EU
	Prescale value. More...

#define	XTTCPS_CLK_CNTRL_PS_VAL_SHIFT 1U
	Prescale shift. More...

#define	XTTCPS_CLK_CNTRL_PS_DISABLE 16U
	Prescale disable. More...

#define	XTTCPS_CLK_CNTRL_SRC_MASK 0x00000020U
	Clock source. More...

#define	XTTCPS_CLK_CNTRL_EXT_EDGE_MASK 0x00000040U
	External Clock edge. More...

Counter Control Register
Counter Control Register definitions
#define	XTTCPS_CNT_CNTRL_DIS_MASK 0x00000001U
	Disable the counter. More...

#define	XTTCPS_CNT_CNTRL_INT_MASK 0x00000002U
	Interval mode. More...

#define	XTTCPS_CNT_CNTRL_DECR_MASK 0x00000004U
	Decrement mode. More...

#define	XTTCPS_CNT_CNTRL_MATCH_MASK 0x00000008U
	Match mode. More...

#define	XTTCPS_CNT_CNTRL_RST_MASK 0x00000010U
	Reset counter. More...

#define	XTTCPS_CNT_CNTRL_EN_WAVE_MASK 0x00000020U
	Enable waveform. More...

#define	XTTCPS_CNT_CNTRL_POL_WAVE_MASK 0x00000040U
	Waveform polarity. More...

#define	XTTCPS_CNT_CNTRL_RESET_VALUE 0x00000021U
	Reset value. More...

Current Counter Value Register
Current Counter Value Register definitions
#define	XTTCPS_COUNT_VALUE_MASK 0x0000FFFFU
	16-bit counter value More...

Interval Value Register
Interval Value Register is the maximum value the counter will count up or down to.
#define	XTTCPS_INTERVAL_VAL_MASK 0x0000FFFFU
	16-bit Interval value More...

Match Registers
Definitions for Match registers, each timer counter has three match registers.
#define	XTTCPS_MATCH_MASK 0x0000FFFFU
	16-bit Match value More...

#define	XTTCPS_NUM_MATCH_REG 3U
	Num of Match reg. More...

Interrupt Registers
Following register bit mask is for all interrupt registers.
#define	XTTCPS_IXR_INTERVAL_MASK 0x00000001U
	Interval Interrupt. More...

#define	XTTCPS_IXR_MATCH_0_MASK 0x00000002U
	Match 1 Interrupt. More...

#define	XTTCPS_IXR_MATCH_1_MASK 0x00000004U
	Match 2 Interrupt. More...

#define	XTTCPS_IXR_MATCH_2_MASK 0x00000008U
	Match 3 Interrupt. More...

#define	XTTCPS_IXR_CNT_OVR_MASK 0x00000010U
	Counter Overflow. More...

#define	XTTCPS_IXR_ALL_MASK 0x0000001FU
	All valid Interrupts. More...

Macro Definition Documentation

#define XTtcPs_ClearInterruptStatus	(	InstancePtr,
		InterruptMask
	)

Value:

(void) InterruptMask; \

InstReadReg((InstancePtr), XTTCPS_ISR_OFFSET)

XTTCPS_ISR_OFFSET

#define XTTCPS_ISR_OFFSET

Interrupt Status Register.

Definition: xttcps_hw.h:67

This function clears the interrupt status.

Parameters

InstancePtr	is a pointer to the XTtcPs instance.
InterruptMask	defines which interrupt should be cleared. Constants are defined in xttcps_hw.h as XTTCPS_IXR_*. This is a bit mask, all set bits will be cleared, cleared bits will not be cleared.

Returns: None.

Note: C-style signature: void XTtcPs_ClearInterruptStatus(XTtcPs *InstancePtr, u32 InterruptMask)

Referenced by XTtcPs_Release().

#define XTTCPS_CLK_CNTRL_EXT_EDGE_MASK 0x00000040U

External Clock edge.

#define XTTCPS_CLK_CNTRL_OFFSET 0x00000000U

Clock Control Register.

Referenced by XTtcPs_CfgInitialize(), XTtcPs_GetPrescaler(), XTtcPs_SetOptions(), and XTtcPs_SetPrescaler().

#define XTTCPS_CLK_CNTRL_PS_DISABLE 16U

Prescale disable.

Referenced by XTtcPs_CalcIntervalFromFreq(), XTtcPs_GetPrescaler(), and XTtcPs_SetPrescaler().

#define XTTCPS_CLK_CNTRL_PS_EN_MASK 0x00000001U

Prescale enable.

Referenced by XTtcPs_GetPrescaler(), and XTtcPs_SetPrescaler().

#define XTTCPS_CLK_CNTRL_PS_VAL_MASK 0x0000001EU

Prescale value.

Referenced by XTtcPs_GetPrescaler(), and XTtcPs_SetPrescaler().

#define XTTCPS_CLK_CNTRL_PS_VAL_SHIFT 1U

Prescale shift.

Referenced by XTtcPs_GetPrescaler(), and XTtcPs_SetPrescaler().

#define XTTCPS_CLK_CNTRL_SRC_MASK 0x00000020U

Clock source.

#define XTTCPS_CNT_CNTRL_DECR_MASK 0x00000004U

Decrement mode.

#define XTTCPS_CNT_CNTRL_DIS_MASK 0x00000001U

Disable the counter.

#define XTTCPS_CNT_CNTRL_EN_WAVE_MASK 0x00000020U

Enable waveform.

#define XTTCPS_CNT_CNTRL_INT_MASK 0x00000002U

Interval mode.

#define XTTCPS_CNT_CNTRL_MATCH_MASK 0x00000008U

Match mode.

#define XTTCPS_CNT_CNTRL_OFFSET 0x0000000CU

Counter Control Register.

Referenced by XTtcPs_CfgInitialize(), XTtcPs_SelfTest(), and XTtcPs_SetOptions().

#define XTTCPS_CNT_CNTRL_POL_WAVE_MASK 0x00000040U

Waveform polarity.

#define XTTCPS_CNT_CNTRL_RESET_VALUE 0x00000021U

Reset value.

Referenced by XTtcPs_CfgInitialize(), and XTtcPs_SelfTest().

#define XTTCPS_CNT_CNTRL_RST_MASK 0x00000010U

Reset counter.

#define XTTCPS_COUNT_VALUE_MASK 0x0000FFFFU

16-bit counter value

#define XTTCPS_COUNT_VALUE_OFFSET 0x00000018U

Current Counter Value.

#define XTtcPs_DisableInterrupts	(	InstancePtr,
		InterruptMask
	)

Value:

InstWriteReg((InstancePtr), XTTCPS_IER_OFFSET,  \
                (InstReadReg((InstancePtr), XTTCPS_IER_OFFSET) &        \
                 ~(InterruptMask)))

This function disables the interrupts.

Parameters

InstancePtr	is a pointer to the XTtcPs instance.
InterruptMask	defines which interrupt should be disabled. Constants are defined in xttcps_hw.h as XTTCPS_IXR_*. This is a bit mask, all set bits will be disabled, cleared bits will not be disabled.

Returns: None.

Note: C-style signature: void XTtcPs_DisableInterrupts(XTtcPs *InstancePtr, u32 InterruptMask)

Referenced by XTtcPs_Release().

#define XTtcPs_EnableInterrupts	(	InstancePtr,
		InterruptMask
	)

Value:

InstWriteReg((InstancePtr), XTTCPS_IER_OFFSET,          \
                (InstReadReg((InstancePtr), XTTCPS_IER_OFFSET) |        \
                 (InterruptMask)))

This function enables the interrupts.

Parameters

InstancePtr	is a pointer to the XTtcPs instance.
InterruptMask	defines which interrupt should be enabled. Constants are defined in xttcps_hw.h as XTTCPS_IXR_*. This is a bit mask, all set bits will be enabled, cleared bits will not be disabled.

Returns: None.

Note: C-style signature: void XTtcPs_EnableInterrupts(XTtcPs *InstancePtr, u32 InterruptMask)

#define XTtcPs_GetCounterValue ( InstancePtr ) (u16)InstReadReg((InstancePtr), XTTCPS_COUNT_VALUE_OFFSET)

This function returns the current 16-bit counter value.

It may be called at any time.

Parameters

InstancePtr is a pointer to the XTtcPs instance.

Returns: zynq:16 bit counter value. zynq ultrascale+mpsoc:32 bit counter value.

Note: C-style signature: zynq: u16 XTtcPs_GetCounterValue(XTtcPs *InstancePtr) zynq ultrascale+mpsoc: u32 XTtcPs_GetCounterValue(XTtcPs *InstancePtr)

#define XTtcPs_GetInterruptStatus ( InstancePtr ) InstReadReg((InstancePtr), XTTCPS_ISR_OFFSET)

This function reads the interrupt status.

Parameters

InstancePtr is a pointer to the XTtcPs instance.

Returns: None.

Note: C-style signature: u32 XTtcPs_GetInterruptStatus(XTtcPs *InstancePtr)

Referenced by XTtcPs_InterruptHandler(), and XTtcPs_Release().

#define XTtcPs_GetInterval ( InstancePtr ) (u16)InstReadReg((InstancePtr), XTTCPS_INTERVAL_VAL_OFFSET)

This function gets the interval value from the interval register.

Parameters

InstancePtr is a pointer to the XTtcPs instance.

Returns: zynq:16 bit interval value. zynq ultrascale+mpsoc:32 bit interval value.

Note: C-style signature: zynq: u16 XTtcPs_GetInterval(XTtcPs *InstancePtr) zynq ultrascale+mpsoc: u32 XTtcPs_GetInterval(XTtcPs *InstancePtr)

#define XTTCPS_IER_OFFSET 0x00000060U

Interrupt Enable Register.

Referenced by XTtcPs_CfgInitialize().

#define XTTCPS_INTERVAL_VAL_MASK 0x0000FFFFU

16-bit Interval value

#define XTTCPS_INTERVAL_VAL_OFFSET 0x00000024U

Interval Count Value.

Referenced by XTtcPs_CfgInitialize().

#define XTTCPS_ISR_OFFSET 0x00000054U

Interrupt Status Register.

Referenced by XTtcPs_CfgInitialize().

#define XTtcPs_IsStarted ( InstancePtr )

Value:

((InstReadReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET) & \

XTTCPS_CNT_CNTRL_DIS_MASK) == 0U)

XTTCPS_CNT_CNTRL_OFFSET

#define XTTCPS_CNT_CNTRL_OFFSET

Counter Control Register.

Definition: xttcps_hw.h:61

XTTCPS_CNT_CNTRL_DIS_MASK

#define XTTCPS_CNT_CNTRL_DIS_MASK

Disable the counter.

Definition: xttcps_hw.h:87

This function checks whether the timer counter has already started.

Parameters

InstancePtr is a pointer to the XTtcPs instance

Returns: Non-zero if the device has started, '0' otherwise.

Note: C-style signature: int XTtcPs_IsStarted(XTtcPs *InstancePtr)

Referenced by XTtcPs_CfgInitialize().

#define XTTCPS_IXR_ALL_MASK 0x0000001FU

All valid Interrupts.

Referenced by XTtcPs_CfgInitialize(), and XTtcPs_Release().

#define XTTCPS_IXR_CNT_OVR_MASK 0x00000010U

Counter Overflow.

#define XTTCPS_IXR_INTERVAL_MASK 0x00000001U

Interval Interrupt.

#define XTTCPS_IXR_MATCH_0_MASK 0x00000002U

Match 1 Interrupt.

#define XTTCPS_IXR_MATCH_1_MASK 0x00000004U

Match 2 Interrupt.

#define XTTCPS_IXR_MATCH_2_MASK 0x00000008U

Match 3 Interrupt.

#define XTTCPS_MATCH_0_OFFSET 0x00000030U

Match 1 value.

Referenced by XTtcPs_CfgInitialize().

#define XTTCPS_MATCH_1_OFFSET 0x0000003CU

Match 2 value.

Referenced by XTtcPs_CfgInitialize().

#define XTTCPS_MATCH_2_OFFSET 0x00000048U

Match 3 value.

Referenced by XTtcPs_CfgInitialize().

#define XTTCPS_MATCH_MASK 0x0000FFFFU

16-bit Match value

#define XTtcPs_Match_N_Offset ( MatchIndex ) ((u32)XTTCPS_MATCH_0_OFFSET + ((u32)(12U) * (u32)(MatchIndex)))

Calculate a match register offset using the Match Register index.

Parameters

MatchIndex is the 0-2 value of the match register

Returns: MATCH_N_OFFSET.

Note: C-style signature: u32 XTtcPs_Match_N_Offset(u8 MatchIndex)

Referenced by XTtcPs_GetMatchValue(), and XTtcPs_SetMatchValue().

#define XTTCPS_NUM_MATCH_REG 3U

Num of Match reg.

Referenced by XTtcPs_GetMatchValue(), and XTtcPs_SetMatchValue().

#define XTTCPS_OPTION_CLK_EDGE_NEG 0x00000002U

Clock on trailing edge for external clock.

#define XTTCPS_OPTION_DECREMENT 0x00000008U

Decrement the counter.

#define XTTCPS_OPTION_EXTERNAL_CLK 0x00000001U

External clock source.

#define XTTCPS_OPTION_INTERVAL_MODE 0x00000004U

Interval mode.

#define XTTCPS_OPTION_MATCH_MODE 0x00000010U

Match mode.

#define XTTCPS_OPTION_WAVE_DISABLE 0x00000020U

No waveform output.

#define XTTCPS_OPTION_WAVE_POLARITY 0x00000040U

Waveform polarity.

#define XTtcPs_ReadReg	(	BaseAddress,
		RegOffset
	)	(Xil_In32((BaseAddress) + (u32)(RegOffset)))

Read the given Timer Counter register.

Parameters

BaseAddress	is the base address of the timer counter device.
RegOffset	is the register offset to be read

Returns: The 32-bit value of the register

Note: C-style signature: u32 XTtcPs_ReadReg(u32 BaseAddress, u32 RegOffset)

Referenced by XTtcPs_GetMatchValue(), XTtcPs_GetOptions(), XTtcPs_GetPrescaler(), XTtcPs_SelfTest(), XTtcPs_SetOptions(), and XTtcPs_SetPrescaler().

#define XTtcPs_ResetCounterValue ( InstancePtr )

Value:

InstWriteReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET,    \
                (InstReadReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET) | \
                 (u32)XTTCPS_CNT_CNTRL_RST_MASK))

This macro resets the count register.

It may be called at any time. The counter is reset to either 0 or 0xFFFF, or the interval value, depending on the increment/decrement mode. The state of the counter, as started or stopped, is not affected by calling reset.

Parameters

InstancePtr is a pointer to the XTtcPs instance.

Returns: None

Note: C-style signature: void XTtcPs_ResetCounterValue(XTtcPs *InstancePtr)

Referenced by XTtcPs_CfgInitialize().

#define XTtcPs_SetInterval	(	InstancePtr,
		Value
	)	InstWriteReg((InstancePtr), XTTCPS_INTERVAL_VAL_OFFSET, (Value))

This function sets the interval value to be used in interval mode.

Parameters

InstancePtr	is a pointer to the XTtcPs instance.
Value	is the 16-bit value to be set in the interval register.

Returns: None

Note: C-style signature: void XTtcPs_SetInterval(XTtcPs *InstancePtr, XInterval Value)

#define XTtcPs_Start ( InstancePtr )

Value:

InstWriteReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET,    \
                (InstReadReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET) &  \
                 ~XTTCPS_CNT_CNTRL_DIS_MASK))

This function starts the counter/timer without resetting the counter value.

Parameters

InstancePtr is a pointer to the XTtcPs instance.

Returns: None

Note: C-style signature: void XTtcPs_Start(XTtcPs *InstancePtr)

#define XTtcPs_Stop ( InstancePtr )

Value:

InstWriteReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET,    \
                (InstReadReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET) |  \
                 XTTCPS_CNT_CNTRL_DIS_MASK))

This function stops the counter/timer.

This macro may be called at any time to stop the counter. The counter holds the last value until it is reset, restarted or enabled.

Parameters

InstancePtr is a pointer to the XTtcPs instance.

Returns: None

Note: C-style signature: void XTtcPs_Stop(XTtcPs *InstancePtr)

Referenced by TmrInterruptExample(), XTtcPs_CfgInitialize(), and XTtcPs_Release().

#define XTtcPs_WriteReg	(	BaseAddress,
		RegOffset,
		Data
	)	(Xil_Out32((BaseAddress) + (u32)(RegOffset), (u32)(Data)))

Write the given Timer Counter register.

Parameters

BaseAddress	is the base address of the timer counter device.
RegOffset	is the register offset to be written
Data	is the 32-bit value to write to the register

Returns: None.

Note: C-style signature: void XTtcPs_WriteReg(XTtcPs BaseAddress, u32 RegOffset, u32 Data)

Referenced by XTtcPs_CfgInitialize(), XTtcPs_SetMatchValue(), XTtcPs_SetOptions(), and XTtcPs_SetPrescaler().

Typedef Documentation

typedef u16 XInterval

This typedef contains interval count and Match register value.

Function Documentation

void XTtcPs_CalcIntervalFromFreq	(	XTtcPs *	InstancePtr,
		u32	Freq,
		XInterval *	Interval,
		u8 *	Prescaler
	)

This function calculates the interval value as well as the prescaler value for a given frequency.

Parameters

InstancePtr	is a pointer to the XTtcPs instance.
Freq	is the requested output frequency for the device. valid values are: 1 - (2^32)-1
Interval	is the interval value for the given frequency, it is the output value for this function.
Prescaler	is the prescaler value for the given frequency, it is the output value for this function.

Returns: None.

Note: Upon successful calculation for the given frequency, Interval and Prescaler carry the settings for the timer counter; Upon unsuccessful calculation, Interval and Prescaler are set to 0xFF(FF) for their maximum values to signal the caller of failure. Therefore, caller needs to check the return interval or prescaler values for whether the function has succeeded.

References XTtcPs::Config, XTtcPs_Config::InputClockHz, and XTTCPS_CLK_CNTRL_PS_DISABLE.

s32 XTtcPs_CfgInitialize	(	XTtcPs *	InstancePtr,
		XTtcPs_Config *	ConfigPtr,
		u32	EffectiveAddr
	)

Initializes a specific XTtcPs instance such that the driver is ready to use.

This function initializes a single timer counter in the triple timer counter function block.

The state of the device after initialization is:

Overflow Mode
Internal (pclk) selected
Counter disabled
All Interrupts disabled
Output waveforms disabled

Parameters

InstancePtr	is a pointer to the XTtcPs instance.
ConfigPtr	is a reference to a structure containing information about a specific TTC device.
EffectiveAddr	is the device base address in the virtual memory address space. The caller is responsible for keeping the address mapping from EffectiveAddr to the device physical base address unchanged once this function is invoked. Unexpected errors may occur if the address mapping changes after this function is called. If address translation is not used, then use ConfigPtr->BaseAddress for this parameter, passing the physical address instead.

Returns

            - XST_SUCCESS if the initialization is successful.
    - XST_DEVICE_IS_STARTED if the device is started. It must be
      stopped to re-initialize.

Note: Device has to be stopped first to call this function to initialize it.

References XTtcPs_Config::BaseAddress, XTtcPs::Config, XTtcPs_Config::DeviceId, XTtcPs_Config::InputClockHz, XTtcPs::IsReady, XTTCPS_CLK_CNTRL_OFFSET, XTTCPS_CNT_CNTRL_OFFSET, XTTCPS_CNT_CNTRL_RESET_VALUE, XTTCPS_IER_OFFSET, XTTCPS_INTERVAL_VAL_OFFSET, XTTCPS_ISR_OFFSET, XTtcPs_IsStarted, XTTCPS_IXR_ALL_MASK, XTTCPS_MATCH_0_OFFSET, XTTCPS_MATCH_1_OFFSET, XTTCPS_MATCH_2_OFFSET, XTtcPs_ResetCounterValue, XTtcPs_Stop, and XTtcPs_WriteReg.

XMatchRegValue XTtcPs_GetMatchValue	(	XTtcPs *	InstancePtr,
		u8	MatchIndex
	)

This function is used to get the value of the match registers.

There are three match registers.

Parameters

InstancePtr	is a pointer to the XTtcPs instance.
MatchIndex	is the index to the match register to be set. There are three match registers are there. Valid values are: 0 - 2.

Returns: The match register value

Note: None

References XTtcPs_Config::BaseAddress, XTtcPs::Config, XTtcPs::IsReady, XTtcPs_Match_N_Offset, XTTCPS_NUM_MATCH_REG, and XTtcPs_ReadReg.

u32 XTtcPs_GetOptions ( XTtcPs * InstancePtr )

This function gets the settings for the options for the TTC device.

Parameters

InstancePtr is a pointer to the XTtcPs instance.

Returns

The return u32 contains the specified options that are set. This is a bit mask where a '1' means the option is on, and a'0' means the option is off. One or more bit values may be contained in the mask. See the bit definitions named XTTCPS_*_OPTION in the file xttcps.h.

Note: None.

References XTtcPs_Config::BaseAddress, XTtcPs::Config, XTtcPs::IsReady, and XTtcPs_ReadReg.

u8 XTtcPs_GetPrescaler ( XTtcPs * InstancePtr )

This function gets the input clock prescaler.

Parameters

InstancePtr is a pointer to the XTtcPs instance.

Returns
 The value(n) from which the prescalar value is calculated
            as 2^(n+1). Some example values are given below :
        Value           Prescaler
        0               2
        1               4
        N               2^(n+1)
        15              65536
        16              1

          Valid values are: 0 - 16

Note: None.

References XTtcPs_Config::BaseAddress, XTtcPs::Config, XTtcPs::IsReady, XTTCPS_CLK_CNTRL_OFFSET, XTTCPS_CLK_CNTRL_PS_DISABLE, XTTCPS_CLK_CNTRL_PS_EN_MASK, XTTCPS_CLK_CNTRL_PS_VAL_MASK, XTTCPS_CLK_CNTRL_PS_VAL_SHIFT, and XTtcPs_ReadReg.

u32 XTtcPs_InterruptHandler ( XTtcPs * InstancePtr )

Handles interrupts by resetting the counter value and clearing the status register.

Parameters

InstancePtr is a pointer to the XTtcPs instance.

Returns

XST_SUCCESS if successful.

Note: None.

References XTtcPs::StatusRef, and XTtcPs_GetInterruptStatus.

XTtcPs_Config * XTtcPs_LookupConfig ( u16 DeviceId )

Looks up the device configuration based on the unique device ID.

A table contains the configuration info for each device in the system.

Parameters

DeviceId contains the unique ID of the device

Returns

A pointer to the configuration found or NULL if the specified device ID was not found. See xttcps.h for the definition of XTtcPs_Config.

Note: None.

u32 XTtcPs_Release ( XTtcPs * InstancePtr )

This routine releases resources of XTtcPs instance/driver.

Parameters

None

Returns

- XST_SUCCESS if node release was successful

XST_FAILURE if node release was fail, Node won't be released if any other counter/counters in that TTC in use.

Note: None.

References XTtcPs::Config, XTtcPs_Config::DeviceId, XTtcPs_ClearInterruptStatus, XTtcPs_DisableInterrupts, XTtcPs_GetInterruptStatus, XTTCPS_IXR_ALL_MASK, and XTtcPs_Stop.

Referenced by TmrInterruptExample().

s32 XTtcPs_SelfTest ( XTtcPs * InstancePtr )

Runs a self-test on the driver/device.

Parameters

InstancePtr is a pointer to the XTtcPs instance.

Returns

  - XST_SUCCESS if successful
  - XST_FAILURE indicates a register did not read or write correctly

Note: This test fails if it is not called right after initialization.

References XTtcPs_Config::BaseAddress, XTtcPs::Config, XTtcPs::IsReady, XTTCPS_CNT_CNTRL_OFFSET, XTTCPS_CNT_CNTRL_RESET_VALUE, and XTtcPs_ReadReg.

void XTtcPs_SetMatchValue	(	XTtcPs *	InstancePtr,
		u8	MatchIndex,
		XMatchRegValue	Value
	)

This function is used to set the match registers.

There are three match registers.

The match 0 register is special. If the waveform output mode is enabled, the waveform will change polarity when the count matches the value in the match 0 register. The polarity of the waveform output can also be set using the XTtcPs_SetOptions() function.

Parameters

InstancePtr	is a pointer to the XTtcPs instance.
MatchIndex	is the index to the match register to be set. Valid values are: 0 - 2.
Value	is the 16-bit value to be set in the match register. Valid Values are: (For Zynq): 0 - ((2^16)-1) (For Zynq UltraScale + MpSoc) and Versal: 0 - ((2^32) - 1)

Returns: None

Note: None

References XTtcPs_Config::BaseAddress, XTtcPs::Config, XTtcPs::IsReady, XTtcPs_Match_N_Offset, XTTCPS_NUM_MATCH_REG, and XTtcPs_WriteReg.

s32 XTtcPs_SetOptions	(	XTtcPs *	InstancePtr,
		u32	Options
	)

This function sets the options for the TTC device.

Parameters

InstancePtr	is a pointer to the XTtcPs instance.
Options	contains the specified options to be set. This is a bit mask where a 1 means to turn the option on, and a 0 means to turn the option off. One or more bit values may be contained in the mask. See the bit definitions named XTTCPS_*_OPTION in the file xttcps.h.

Returns

XST_SUCCESS if options are successfully set.
XST_FAILURE if any of the options are unknown.

Note: None

References XTtcPs_Config::BaseAddress, XTtcPs::Config, XTtcPs::IsReady, XTTCPS_CLK_CNTRL_OFFSET, XTTCPS_CNT_CNTRL_OFFSET, XTtcPs_ReadReg, and XTtcPs_WriteReg.

void XTtcPs_SetPrescaler	(	XTtcPs *	InstancePtr,
		u8	PrescalerValue
	)

This function sets the prescaler enable bit and if needed sets the prescaler bits in the control register.

Parameters

InstancePtr	is a pointer to the XTtcPs instance.
PrescalerValue	is a number from 0-16 that sets the prescaler to use. If the parameter is 0 - 15, use a prescaler on the clock of 2^(PrescalerValue+1), or 2-65536. If the parameter is XTTCPS_CLK_CNTRL_PS_DISABLE, do not use a prescaler.

Valid values are: 0 - 15

Returns: None

Note: None

References XTtcPs_Config::BaseAddress, XTtcPs::Config, XTtcPs::IsReady, XTTCPS_CLK_CNTRL_OFFSET, XTTCPS_CLK_CNTRL_PS_DISABLE, XTTCPS_CLK_CNTRL_PS_EN_MASK, XTTCPS_CLK_CNTRL_PS_VAL_MASK, XTTCPS_CLK_CNTRL_PS_VAL_SHIFT, XTtcPs_ReadReg, and XTtcPs_WriteReg.

void XTtcPs_SetStatusHandler	(	XTtcPs *	InstancePtr,
		void *	CallBackRef,
		XTtcPs_StatusHandler	FuncPointer
	)

Sets the status callback function, the status handler, which the driver calls when it encounters conditions that should be reported to upper layer software.

The handler executes in an interrupt context, so it must minimize the amount of processing performed. One of the following status events is passed to the status handler.

Parameters

InstancePtr	is a pointer to the XTtcPs instance.
CallBackRef	is the upper layer callback reference passed back when the callback function is invoked.
FuncPointer	is the pointer to the callback function.

Returns: None.

Note

The handler is called within interrupt context, so it should do its work quickly and queue potentially time-consuming work to a task-level thread.

References XTtcPs::IsReady, and XTtcPs::StatusRef.

Variable Documentation

XTtcPs_Config XTtcPs_ConfigTable[XPAR_XTTCPS_NUM_INSTANCES]

This table contains configuration information for each TTC device in the system.

XTtcPs_Config XTtcPs_ConfigTable[XPAR_XTTCPS_NUM_INSTANCES]

This table contains configuration information for each TTC device in the system.

Data Structures

Macros

Typedefs

Functions

Variables

Configuration options

Register Map

Clock Control Register

Counter Control Register

Current Counter Value Register

Interval Value Register

Match Registers

Interrupt Registers

Macro Definition Documentation

Typedef Documentation

Function Documentation

Variable Documentation