Macros
#define	XUartPs_ReadReg(BaseAddress, RegOffset) Xil_In32((BaseAddress) + (u32)(RegOffset))
	Read a UART register. More...

#define	XUartPs_WriteReg(BaseAddress, RegOffset, RegisterValue) Xil_Out32((BaseAddress) + (u32)(RegOffset), (u32)(RegisterValue))
	Write a UART register. More...

#define	XUartPs_IsReceiveData(BaseAddress)
	Determine if there is receive data in the receiver and/or FIFO. More...

#define	XUartPs_IsTransmitFull(BaseAddress)
	Determine if a byte of data can be sent with the transmitter. More...

#define	XUartPs_IsTransmitFifoEmpty(BaseAddress)
	Check if transmission FIFO is empty. More...

#define	XUartPs_IsTransmitActive(BaseAddress)
	Check if transmission state machine is active. More...

Register Map
Register offsets for the UART.
#define	XUARTPS_CR_OFFSET 0x0000U
	Control Register [8:0]. More...

#define	XUARTPS_MR_OFFSET 0x0004U
	Mode Register [9:0]. More...

#define	XUARTPS_IER_OFFSET 0x0008U
	Interrupt Enable [12:0]. More...

#define	XUARTPS_IDR_OFFSET 0x000CU
	Interrupt Disable [12:0]. More...

#define	XUARTPS_IMR_OFFSET 0x0010U
	Interrupt Mask [12:0]. More...

#define	XUARTPS_ISR_OFFSET 0x0014U
	Interrupt Status [12:0]. More...

#define	XUARTPS_BAUDGEN_OFFSET 0x0018U
	Baud Rate Generator [15:0]. More...

#define	XUARTPS_RXTOUT_OFFSET 0x001CU
	RX Timeout [7:0]. More...

#define	XUARTPS_RXWM_OFFSET 0x0020U
	RX FIFO Trigger Level [5:0]. More...

#define	XUARTPS_MODEMCR_OFFSET 0x0024U
	Modem Control [5:0]. More...

#define	XUARTPS_MODEMSR_OFFSET 0x0028U
	Modem Status [8:0]. More...

#define	XUARTPS_SR_OFFSET 0x002CU
	Channel Status [14:0]. More...

#define	XUARTPS_FIFO_OFFSET 0x0030U
	FIFO [7:0]. More...

#define	XUARTPS_BAUDDIV_OFFSET 0x0034U
	Baud Rate Divider [7:0]. More...

#define	XUARTPS_FLOWDEL_OFFSET 0x0038U
	Flow Delay [5:0]. More...

#define	XUARTPS_TXWM_OFFSET 0x0044U
	TX FIFO Trigger Level [5:0]. More...

#define	XUARTPS_RXBS_OFFSET 0x0048U
	RX FIFO Byte Status [11:0]. More...

Control Register
The Control register (CR) controls the major functions of the device. Control Register Bit Definition
#define	XUARTPS_CR_STOPBRK 0x00000100U
	Stop transmission of break. More...

#define	XUARTPS_CR_STARTBRK 0x00000080U
	Set break. More...

#define	XUARTPS_CR_TORST 0x00000040U
	RX timeout counter restart. More...

#define	XUARTPS_CR_TX_DIS 0x00000020U
	TX disabled. More...

#define	XUARTPS_CR_TX_EN 0x00000010U
	TX enabled. More...

#define	XUARTPS_CR_RX_DIS 0x00000008U
	RX disabled. More...

#define	XUARTPS_CR_RX_EN 0x00000004U
	RX enabled. More...

#define	XUARTPS_CR_EN_DIS_MASK 0x0000003CU
	Enable/disable Mask. More...

#define	XUARTPS_CR_TXRST 0x00000002U
	TX logic reset. More...

#define	XUARTPS_CR_RXRST 0x00000001U
	RX logic reset. More...

Mode Register
The mode register (MR) defines the mode of transfer as well as the data format. If this register is modified during transmission or reception, data validity cannot be guaranteed. Mode Register Bit Definition
#define	XUARTPS_MR_CCLK 0x00000400U
	Input clock selection. More...

#define	XUARTPS_MR_CHMODE_R_LOOP 0x00000300U
	Remote loopback mode. More...

#define	XUARTPS_MR_CHMODE_L_LOOP 0x00000200U
	Local loopback mode. More...

#define	XUARTPS_MR_CHMODE_ECHO 0x00000100U
	Auto echo mode. More...

#define	XUARTPS_MR_CHMODE_NORM 0x00000000U
	Normal mode. More...

#define	XUARTPS_MR_CHMODE_SHIFT 8U
	Mode shift. More...

#define	XUARTPS_MR_CHMODE_MASK 0x00000300U
	Mode mask. More...

#define	XUARTPS_MR_STOPMODE_2_BIT 0x00000080U
	2 stop bits More...

#define	XUARTPS_MR_STOPMODE_1_5_BIT 0x00000040U
	1.5 stop bits More...

#define	XUARTPS_MR_STOPMODE_1_BIT 0x00000000U
	1 stop bit More...

#define	XUARTPS_MR_STOPMODE_SHIFT 6U
	Stop bits shift. More...

#define	XUARTPS_MR_STOPMODE_MASK 0x000000A0U
	Stop bits mask. More...

#define	XUARTPS_MR_PARITY_NONE 0x00000020U
	No parity mode. More...

#define	XUARTPS_MR_PARITY_MARK 0x00000018U
	Mark parity mode. More...

#define	XUARTPS_MR_PARITY_SPACE 0x00000010U
	Space parity mode. More...

#define	XUARTPS_MR_PARITY_ODD 0x00000008U
	Odd parity mode. More...

#define	XUARTPS_MR_PARITY_EVEN 0x00000000U
	Even parity mode. More...

#define	XUARTPS_MR_PARITY_SHIFT 3U
	Parity setting shift. More...

#define	XUARTPS_MR_PARITY_MASK 0x00000038U
	Parity mask. More...

#define	XUARTPS_MR_CHARLEN_6_BIT 0x00000006U
	6 bits data More...

#define	XUARTPS_MR_CHARLEN_7_BIT 0x00000004U
	7 bits data More...

#define	XUARTPS_MR_CHARLEN_8_BIT 0x00000000U
	8 bits data More...

#define	XUARTPS_MR_CHARLEN_SHIFT 1U
	Data Length shift. More...

#define	XUARTPS_MR_CHARLEN_MASK 0x00000006U
	Data length mask. More...

#define	XUARTPS_MR_CLKSEL 0x00000001U
	Input clock selection. More...

Interrupt Registers
Interrupt control logic uses the interrupt enable register (IER) and the interrupt disable register (IDR) to set the value of the bits in the interrupt mask register (IMR). The IMR determines whether to pass an interrupt to the interrupt status register (ISR). Writing a 1 to IER Enbables an interrupt, writing a 1 to IDR disables an interrupt. IMR and ISR are read only, and IER and IDR are write only. Reading either IER or IDR returns 0x00. All four registers have the same bit definitions.
#define	XUARTPS_IXR_RBRK 0x00002000U
	Rx FIFO break detect interrupt. More...

#define	XUARTPS_IXR_TOVR 0x00001000U
	Tx FIFO Overflow interrupt. More...

#define	XUARTPS_IXR_TNFUL 0x00000800U
	Tx FIFO Nearly Full interrupt. More...

#define	XUARTPS_IXR_TTRIG 0x00000400U
	Tx Trig interrupt. More...

#define	XUARTPS_IXR_DMS 0x00000200U
	Modem status change interrupt. More...

#define	XUARTPS_IXR_TOUT 0x00000100U
	Timeout error interrupt. More...

#define	XUARTPS_IXR_PARITY 0x00000080U
	Parity error interrupt. More...

#define	XUARTPS_IXR_FRAMING 0x00000040U
	Framing error interrupt. More...

#define	XUARTPS_IXR_OVER 0x00000020U
	Overrun error interrupt. More...

#define	XUARTPS_IXR_TXFULL 0x00000010U
	TX FIFO full interrupt. More...

#define	XUARTPS_IXR_TXEMPTY 0x00000008U
	TX FIFO empty interrupt. More...

#define	XUARTPS_IXR_RXFULL 0x00000004U
	RX FIFO full interrupt. More...

#define	XUARTPS_IXR_RXEMPTY 0x00000002U
	RX FIFO empty interrupt. More...

#define	XUARTPS_IXR_RXOVR 0x00000001U
	RX FIFO trigger interrupt. More...

#define	XUARTPS_IXR_MASK 0x00003FFFU
	Valid bit mask. More...

Baud Rate Generator Register
The baud rate generator control register (BRGR) is a 16 bit register that controls the receiver bit sample clock and baud rate. Valid values are 1 - 65535. Bit Sample Rate = CCLK / BRGR, where the CCLK is selected by the MR_CCLK bit in the MR register.
#define	XUARTPS_BAUDGEN_DISABLE 0x00000000U
	Disable clock. More...

#define	XUARTPS_BAUDGEN_MASK 0x0000FFFFU
	Valid bits mask. More...

#define	XUARTPS_BAUDGEN_RESET_VAL 0x0000028BU
	Reset value. More...

Baud Divisor Rate register
The baud rate divider register (BDIV) controls how much the bit sample rate is divided by. It sets the baud rate. Valid values are 0x04 to 0xFF. Writing a value less than 4 will be ignored. Baud rate = CCLK / ((BAUDDIV + 1) x BRGR), where the CCLK is selected by the MR_CCLK bit in the MR register.
#define	XUARTPS_BAUDDIV_MASK 0x000000FFU
	8 bit baud divider mask More...

#define	XUARTPS_BAUDDIV_RESET_VAL 0x0000000FU
	Reset value. More...

Receiver Timeout Register
Use the receiver timeout register (RTR) to detect an idle condition on the receiver data line.
#define	XUARTPS_RXTOUT_DISABLE 0x00000000U
	Disable time out. More...

#define	XUARTPS_RXTOUT_MASK 0x000000FFU
	Valid bits mask. More...

Receiver FIFO Trigger Level Register
Use the Receiver FIFO Trigger Level Register (RTRIG) to set the value at which the RX FIFO triggers an interrupt event.
#define	XUARTPS_RXWM_DISABLE 0x00000000U
	Disable RX trigger interrupt. More...

#define	XUARTPS_RXWM_MASK 0x0000003FU
	Valid bits mask. More...

#define	XUARTPS_RXWM_RESET_VAL 0x00000020U
	Reset value. More...

Transmit FIFO Trigger Level Register
Use the Transmit FIFO Trigger Level Register (TTRIG) to set the value at which the TX FIFO triggers an interrupt event.
#define	XUARTPS_TXWM_MASK 0x0000003FU
	Valid bits mask. More...

#define	XUARTPS_TXWM_RESET_VAL 0x00000020U
	Reset value. More...

Modem Control Register
This register (MODEMCR) controls the interface with the modem or data set, or a peripheral device emulating a modem.
#define	XUARTPS_MODEMCR_FCM 0x00000020U
	Flow control mode. More...

#define	XUARTPS_MODEMCR_RTS 0x00000002U
	Request to send. More...

#define	XUARTPS_MODEMCR_DTR 0x00000001U
	Data terminal ready. More...

Modem Status Register
This register (MODEMSR) indicates the current state of the control lines from a modem, or another peripheral device, to the CPU. In addition, four bits of the modem status register provide change information. These bits are set to a logic 1 whenever a control input from the modem changes state. Note: Whenever the DCTS, DDSR, TERI, or DDCD bit is set to logic 1, a modem status interrupt is generated and this is reflected in the modem status register.
#define	XUARTPS_MODEMSR_FCMS 0x00000100U
	Flow control mode (FCMS) More...

#define	XUARTPS_MODEMSR_DCD 0x00000080U
	Complement of DCD input. More...

#define	XUARTPS_MODEMSR_RI 0x00000040U
	Complement of RI input. More...

#define	XUARTPS_MODEMSR_DSR 0x00000020U
	Complement of DSR input. More...

#define	XUARTPS_MODEMSR_CTS 0x00000010U
	Complement of CTS input. More...

#define	XUARTPS_MODEMSR_DDCD 0x00000008U
	Delta DCD indicator. More...

#define	XUARTPS_MODEMSR_TERI 0x00000004U
	Trailing Edge Ring Indicator. More...

#define	XUARTPS_MODEMSR_DDSR 0x00000002U
	Change of DSR. More...

#define	XUARTPS_MODEMSR_DCTS 0x00000001U
	Change of CTS. More...

Channel Status Register
The channel status register (CSR) is provided to enable the control logic to monitor the status of bits in the channel interrupt status register, even if these are masked out by the interrupt mask register.
#define	XUARTPS_SR_TNFUL 0x00004000U
	TX FIFO Nearly Full Status. More...

#define	XUARTPS_SR_TTRIG 0x00002000U
	TX FIFO Trigger Status. More...

#define	XUARTPS_SR_FLOWDEL 0x00001000U
	RX FIFO fill over flow delay. More...

#define	XUARTPS_SR_TACTIVE 0x00000800U
	TX active. More...

#define	XUARTPS_SR_RACTIVE 0x00000400U
	RX active. More...

#define	XUARTPS_SR_TXFULL 0x00000010U
	TX FIFO full. More...

#define	XUARTPS_SR_TXEMPTY 0x00000008U
	TX FIFO empty. More...

#define	XUARTPS_SR_RXFULL 0x00000004U
	RX FIFO full. More...

#define	XUARTPS_SR_RXEMPTY 0x00000002U
	RX FIFO empty. More...

#define	XUARTPS_SR_RXOVR 0x00000001U
	RX FIFO fill over trigger. More...

Flow Delay Register
Operation of the flow delay register (FLOWDEL) is very similar to the receive FIFO trigger register. An internal trigger signal activates when the FIFO is filled to the level set by this register. This trigger will not cause an interrupt, although it can be read through the channel status register. In hardware flow control mode, RTS is deactivated when the trigger becomes active. RTS only resets when the FIFO level is four less than the level of the flow delay trigger and the flow delay trigger is not activated. A value less than 4 disables the flow delay.
#define	XUARTPS_FLOWDEL_MASK XUARTPS_RXWM_MASK
	Valid bit mask. More...

Receiver FIFO Byte Status Register
The Receiver FIFO Status register is used to have a continuous monitoring of the raw unmasked byte status information. The register contains frame, parity and break status information for the top four bytes in the RX FIFO. Receiver FIFO Byte Status Register Bit Definition
#define	XUARTPS_RXBS_BYTE3_BRKE 0x00000800U
	Byte3 Break Error. More...

#define	XUARTPS_RXBS_BYTE3_FRME 0x00000400U
	Byte3 Frame Error. More...

#define	XUARTPS_RXBS_BYTE3_PARE 0x00000200U
	Byte3 Parity Error. More...

#define	XUARTPS_RXBS_BYTE2_BRKE 0x00000100U
	Byte2 Break Error. More...

#define	XUARTPS_RXBS_BYTE2_FRME 0x00000080U
	Byte2 Frame Error. More...

#define	XUARTPS_RXBS_BYTE2_PARE 0x00000040U
	Byte2 Parity Error. More...

#define	XUARTPS_RXBS_BYTE1_BRKE 0x00000020U
	Byte1 Break Error. More...

#define	XUARTPS_RXBS_BYTE1_FRME 0x00000010U
	Byte1 Frame Error. More...

#define	XUARTPS_RXBS_BYTE1_PARE 0x00000008U
	Byte1 Parity Error. More...

#define	XUARTPS_RXBS_BYTE0_BRKE 0x00000004U
	Byte0 Break Error. More...

#define	XUARTPS_RXBS_BYTE0_FRME 0x00000002U
	Byte0 Frame Error. More...

#define	XUARTPS_RXBS_BYTE0_PARE 0x00000001U
	Byte0 Parity Error. More...

#define	XUARTPS_RXBS_MASK 0x00000007U
	3 bit RX byte status mask More...

Functions
void	XUartPs_SendByte (u32 BaseAddress, u8 Data)
	This function sends one byte using the device. More...

u8	XUartPs_RecvByte (u32 BaseAddress)
	This function receives a byte from the device. More...

void	XUartPs_ResetHw (u32 BaseAddress)
	This function resets UART. More...

void	XUartPs_WaitTransmitDone (u32 BaseAddress)
	This function waits for transmission to complete. More...

Macros

Functions