Data Structures
struct	XUartPs_Config
	This typedef contains configuration information for the device. More...

struct	XUartPsFormat
	Keep track of data format setting of a device. More...

struct	XUartPs
	The XUartPs driver instance data structure. More...

Macros
#define	TIMEOUT_VAL 1000000U
	Wait for 1 sec in worst case. More...

#define	XUartPs_GetChannelStatus(InstancePtr) Xil_In32(((InstancePtr)->Config.BaseAddress) + (u32)XUARTPS_SR_OFFSET)
	Get the UART Channel Status Register. More...

#define	XUartPs_GetModeControl(InstancePtr) Xil_In32(((InstancePtr)->Config.BaseAddress) + (u32)XUARTPS_CR_OFFSET)
	Get the UART Mode Control Register. More...

#define	XUartPs_SetModeControl(InstancePtr, RegisterValue)
	Set the UART Mode Control Register. More...

#define	XUartPs_EnableUart(InstancePtr)
	Enable the transmitter and receiver of the UART. More...

#define	XUartPs_DisableUart(InstancePtr)
	Disable the transmitter and receiver of the UART. More...

#define	XUartPs_IsTransmitEmpty(InstancePtr)
	Determine if the transmitter FIFO is empty. More...

#define	XUartPs_ReadReg(BaseAddress, RegOffset) Xil_In32((BaseAddress) + (u32)(RegOffset))
	Read a UART register. More...

#define	XUartPs_WriteReg(BaseAddress, RegOffset, RegisterValue) Xil_Out32((BaseAddress) + (u32)(RegOffset), (u32)(RegisterValue))
	Write a UART register. More...

#define	XUartPs_IsReceiveData(BaseAddress)
	Determine if there is receive data in the receiver and/or FIFO. More...

#define	XUartPs_IsTransmitFull(BaseAddress)
	Determine if a byte of data can be sent with the transmitter. More...

Typedefs
typedef void(*	XUartPs_Handler )(void *CallBackRef, u32 Event, u32 EventData)
	This data type defines a handler that an application defines to communicate with interrupt system to retrieve state information about an application. More...

typedef void(*	Handler )(XUartPs *InstancePtr)
	This function is the handler which performs processing to handle data events from the device. More...

Functions
s32	XUartPs_CfgInitialize (XUartPs InstancePtr, XUartPs_Config Config, u32 EffectiveAddr)
	Initializes a specific XUartPs instance such that it is ready to be used. More...

u32	XUartPs_Send (XUartPs InstancePtr, u8 BufferPtr, u32 NumBytes)
	This functions sends the specified buffer using the device in either polled or interrupt driven mode. More...

u32	XUartPs_Recv (XUartPs InstancePtr, u8 BufferPtr, u32 NumBytes)
	This function attempts to receive a specified number of bytes of data from the device and store it into the specified buffer. More...

s32	XUartPs_SetBaudRate (XUartPs *InstancePtr, u32 BaudRate)
	Sets the baud rate for the device. More...

XUartPs_Config *	XUartPs_LookupConfig (u16 DeviceId)
	Looks up the device configuration based on the unique device ID. More...

void	XUartPs_SetOptions (XUartPs *InstancePtr, u16 Options)
	Sets the options for the specified driver instance. More...

u16	XUartPs_GetOptions (XUartPs *InstancePtr)
	Gets the options for the specified driver instance. More...

void	XUartPs_SetFifoThreshold (XUartPs *InstancePtr, u8 TriggerLevel)
	This functions sets the receive FIFO trigger level. More...

u8	XUartPs_GetFifoThreshold (XUartPs *InstancePtr)
	This function gets the receive FIFO trigger level. More...

u16	XUartPs_GetModemStatus (XUartPs *InstancePtr)
	This function gets the modem status from the specified UART. More...

u32	XUartPs_IsSending (XUartPs *InstancePtr)
	This function determines if the specified UART is sending data. More...

u8	XUartPs_GetOperMode (XUartPs *InstancePtr)
	This function gets the operational mode of the UART. More...

void	XUartPs_SetOperMode (XUartPs *InstancePtr, u8 OperationMode)
	This function sets the operational mode of the UART. More...

u8	XUartPs_GetFlowDelay (XUartPs *InstancePtr)
	This function sets the Flow Delay. More...

void	XUartPs_SetFlowDelay (XUartPs *InstancePtr, u8 FlowDelayValue)
	This function sets the Flow Delay. More...

u8	XUartPs_GetRecvTimeout (XUartPs *InstancePtr)
	This function gets the Receive Timeout of the UART. More...

void	XUartPs_SetRecvTimeout (XUartPs *InstancePtr, u8 RecvTimeout)
	This function sets the Receive Timeout of the UART. More...

s32	XUartPs_SetDataFormat (XUartPs InstancePtr, XUartPsFormat FormatPtr)
	Sets the data format for the device. More...

void	XUartPs_GetDataFormat (XUartPs InstancePtr, XUartPsFormat FormatPtr)
	Gets the data format for the specified UART. More...

u32	XUartPs_GetInterruptMask (XUartPs *InstancePtr)
	This function gets the interrupt mask. More...

void	XUartPs_SetInterruptMask (XUartPs *InstancePtr, u32 Mask)
	This function sets the interrupt mask. More...

void	XUartPs_InterruptHandler (XUartPs *InstancePtr)
	This function is the interrupt handler for the driver. More...

void	XUartPs_SetHandler (XUartPs InstancePtr, XUartPs_Handler FuncPtr, void CallBackRef)
	This function sets the handler that will be called when an event (interrupt) occurs that needs application's attention. More...

s32	XUartPs_SelfTest (XUartPs *InstancePtr)
	This function runs a self-test on the driver and hardware device. More...

void	XUartPs_SendByte (u32 BaseAddress, u8 Data)
	This function sends one byte using the device. More...

u8	XUartPs_RecvByte (u32 BaseAddress)
	This function receives a byte from the device. More...

void	XUartPs_ResetHw (u32 BaseAddress)
	This function resets UART. More...

Variables
XUartPs_Config	XUartPs_ConfigTable [XPAR_XUARTPS_NUM_INSTANCES]
	Each XUartPs device in the system has an entry in this table. More...

XUartPs_Config	XUartPs_ConfigTable [XPAR_XUARTPS_NUM_INSTANCES]
	Each XUartPs device in the system has an entry in this table. More...

Configuration options
#define	XUARTPS_OPTION_SET_BREAK 0x0080U
	These constants specify the options that may be set or retrieved with the driver, each is a unique bit mask such that multiple options may be specified. More...

#define	XUARTPS_OPTION_STOP_BREAK 0x0040U
	Stops break transmission. More...

#define	XUARTPS_OPTION_RESET_TMOUT 0x0020U
	Reset the receive timeout. More...

#define	XUARTPS_OPTION_RESET_TX 0x0010U
	Reset the transmitter. More...

#define	XUARTPS_OPTION_RESET_RX 0x0008U
	Reset the receiver. More...

#define	XUARTPS_OPTION_ASSERT_RTS 0x0004U
	Assert the RTS bit. More...

#define	XUARTPS_OPTION_ASSERT_DTR 0x0002U
	Assert the DTR bit. More...

#define	XUARTPS_OPTION_SET_FCM 0x0001U
	Turn on flow control mode. More...

Channel Operational Mode
The UART can operate in one of four modes: Normal, Local Loopback, Remote Loopback, or automatic echo.
#define	XUARTPS_OPER_MODE_NORMAL (u8)0x00U
	Normal Mode. More...

#define	XUARTPS_OPER_MODE_AUTO_ECHO (u8)0x01U
	Auto Echo Mode. More...

#define	XUARTPS_OPER_MODE_LOCAL_LOOP (u8)0x02U
	Local Loopback Mode. More...

#define	XUARTPS_OPER_MODE_REMOTE_LOOP (u8)0x03U
	Remote Loopback Mode. More...

Data format values
These constants specify the data format that the driver supports. The data format includes the number of data bits, the number of stop bits and parity.
#define	XUARTPS_FORMAT_8_BITS 0U
	8 data bits More...

#define	XUARTPS_FORMAT_7_BITS 2U
	7 data bits More...

#define	XUARTPS_FORMAT_6_BITS 3U
	6 data bits More...

#define	XUARTPS_FORMAT_NO_PARITY 4U
	No parity. More...

#define	XUARTPS_FORMAT_MARK_PARITY 3U
	Mark parity. More...

#define	XUARTPS_FORMAT_SPACE_PARITY 2U
	parity More...

#define	XUARTPS_FORMAT_ODD_PARITY 1U
	Odd parity. More...

#define	XUARTPS_FORMAT_EVEN_PARITY 0U
	Even parity. More...

#define	XUARTPS_FORMAT_2_STOP_BIT 2U
	2 stop bits More...

#define	XUARTPS_FORMAT_1_5_STOP_BIT 1U
	1.5 stop bits More...

#define	XUARTPS_FORMAT_1_STOP_BIT 0U
	1 stop bit More...

Callback events
These constants specify the handler events that an application can handle using its specific handler function. Note that these constants are not bit mask, so only one event can be passed to an application at a time.
#define	XUARTPS_EVENT_RECV_DATA 1U
	Data receiving done. More...

#define	XUARTPS_EVENT_RECV_TOUT 2U
	A receive timeout occurred. More...

#define	XUARTPS_EVENT_SENT_DATA 3U
	Data transmission done. More...

#define	XUARTPS_EVENT_RECV_ERROR 4U
	A receive error detected. More...

#define	XUARTPS_EVENT_MODEM 5U
	Modem status changed. More...

#define	XUARTPS_EVENT_PARE_FRAME_BRKE 6U
	A receive parity, frame, break error detected. More...

#define	XUARTPS_EVENT_RECV_ORERR 7U
	A receive overrun error detected. More...

Register Map
Register offsets for the UART.
#define	XUARTPS_CR_OFFSET 0x0000U
	Control Register [8:0]. More...

#define	XUARTPS_MR_OFFSET 0x0004U
	Mode Register [9:0]. More...

#define	XUARTPS_IER_OFFSET 0x0008U
	Interrupt Enable [12:0]. More...

#define	XUARTPS_IDR_OFFSET 0x000CU
	Interrupt Disable [12:0]. More...

#define	XUARTPS_IMR_OFFSET 0x0010U
	Interrupt Mask [12:0]. More...

#define	XUARTPS_ISR_OFFSET 0x0014U
	Interrupt Status [12:0]. More...

#define	XUARTPS_BAUDGEN_OFFSET 0x0018U
	Baud Rate Generator [15:0]. More...

#define	XUARTPS_RXTOUT_OFFSET 0x001CU
	RX Timeout [7:0]. More...

#define	XUARTPS_RXWM_OFFSET 0x0020U
	RX FIFO Trigger Level [5:0]. More...

#define	XUARTPS_MODEMCR_OFFSET 0x0024U
	Modem Control [5:0]. More...

#define	XUARTPS_MODEMSR_OFFSET 0x0028U
	Modem Status [8:0]. More...

#define	XUARTPS_SR_OFFSET 0x002CU
	Channel Status [14:0]. More...

#define	XUARTPS_FIFO_OFFSET 0x0030U
	FIFO [7:0]. More...

#define	XUARTPS_BAUDDIV_OFFSET 0x0034U
	Baud Rate Divider [7:0]. More...

#define	XUARTPS_FLOWDEL_OFFSET 0x0038U
	Flow Delay [5:0]. More...

#define	XUARTPS_TXWM_OFFSET 0x0044U
	TX FIFO Trigger Level [5:0]. More...

#define	XUARTPS_RXBS_OFFSET 0x0048U
	RX FIFO Byte Status [11:0]. More...

Control Register
The Control register (CR) controls the major functions of the device. Control Register Bit Definition
#define	XUARTPS_CR_STOPBRK 0x00000100U
	Stop transmission of break. More...

#define	XUARTPS_CR_STARTBRK 0x00000080U
	Set break. More...

#define	XUARTPS_CR_TORST 0x00000040U
	RX timeout counter restart. More...

#define	XUARTPS_CR_TX_DIS 0x00000020U
	TX disabled. More...

#define	XUARTPS_CR_TX_EN 0x00000010U
	TX enabled. More...

#define	XUARTPS_CR_RX_DIS 0x00000008U
	RX disabled. More...

#define	XUARTPS_CR_RX_EN 0x00000004U
	RX enabled. More...

#define	XUARTPS_CR_EN_DIS_MASK 0x0000003CU
	Enable/disable Mask. More...

#define	XUARTPS_CR_TXRST 0x00000002U
	TX logic reset. More...

#define	XUARTPS_CR_RXRST 0x00000001U
	RX logic reset. More...

Mode Register
The mode register (MR) defines the mode of transfer as well as the data format. If this register is modified during transmission or reception, data validity cannot be guaranteed. Mode Register Bit Definition
#define	XUARTPS_MR_CCLK 0x00000400U
	Input clock selection. More...

#define	XUARTPS_MR_CHMODE_R_LOOP 0x00000300U
	Remote loopback mode. More...

#define	XUARTPS_MR_CHMODE_L_LOOP 0x00000200U
	Local loopback mode. More...

#define	XUARTPS_MR_CHMODE_ECHO 0x00000100U
	Auto echo mode. More...

#define	XUARTPS_MR_CHMODE_NORM 0x00000000U
	Normal mode. More...

#define	XUARTPS_MR_CHMODE_SHIFT 8U
	Mode shift. More...

#define	XUARTPS_MR_CHMODE_MASK 0x00000300U
	Mode mask. More...

#define	XUARTPS_MR_STOPMODE_2_BIT 0x00000080U
	2 stop bits More...

#define	XUARTPS_MR_STOPMODE_1_5_BIT 0x00000040U
	1.5 stop bits More...

#define	XUARTPS_MR_STOPMODE_1_BIT 0x00000000U
	1 stop bit More...

#define	XUARTPS_MR_STOPMODE_SHIFT 6U
	Stop bits shift. More...

#define	XUARTPS_MR_STOPMODE_MASK 0x000000A0U
	Stop bits mask. More...

#define	XUARTPS_MR_PARITY_NONE 0x00000020U
	No parity mode. More...

#define	XUARTPS_MR_PARITY_MARK 0x00000018U
	Mark parity mode. More...

#define	XUARTPS_MR_PARITY_SPACE 0x00000010U
	Space parity mode. More...

#define	XUARTPS_MR_PARITY_ODD 0x00000008U
	Odd parity mode. More...

#define	XUARTPS_MR_PARITY_EVEN 0x00000000U
	Even parity mode. More...

#define	XUARTPS_MR_PARITY_SHIFT 3U
	Parity setting shift. More...

#define	XUARTPS_MR_PARITY_MASK 0x00000038U
	Parity mask. More...

#define	XUARTPS_MR_CHARLEN_6_BIT 0x00000006U
	6 bits data More...

#define	XUARTPS_MR_CHARLEN_7_BIT 0x00000004U
	7 bits data More...

#define	XUARTPS_MR_CHARLEN_8_BIT 0x00000000U
	8 bits data More...

#define	XUARTPS_MR_CHARLEN_SHIFT 1U
	Data Length shift. More...

#define	XUARTPS_MR_CHARLEN_MASK 0x00000006U
	Data length mask. More...

#define	XUARTPS_MR_CLKSEL 0x00000001U
	Input clock selection. More...

Interrupt Registers
Interrupt control logic uses the interrupt enable register (IER) and the interrupt disable register (IDR) to set the value of the bits in the interrupt mask register (IMR). The IMR determines whether to pass an interrupt to the interrupt status register (ISR). Writing a 1 to IER Enbables an interrupt, writing a 1 to IDR disables an interrupt. IMR and ISR are read only, and IER and IDR are write only. Reading either IER or IDR returns 0x00. All four registers have the same bit definitions.
#define	XUARTPS_IXR_RBRK 0x00002000U
	Rx FIFO break detect interrupt. More...

#define	XUARTPS_IXR_TOVR 0x00001000U
	Tx FIFO Overflow interrupt. More...

#define	XUARTPS_IXR_TNFUL 0x00000800U
	Tx FIFO Nearly Full interrupt. More...

#define	XUARTPS_IXR_TTRIG 0x00000400U
	Tx Trig interrupt. More...

#define	XUARTPS_IXR_DMS 0x00000200U
	Modem status change interrupt. More...

#define	XUARTPS_IXR_TOUT 0x00000100U
	Timeout error interrupt. More...

#define	XUARTPS_IXR_PARITY 0x00000080U
	Parity error interrupt. More...

#define	XUARTPS_IXR_FRAMING 0x00000040U
	Framing error interrupt. More...

#define	XUARTPS_IXR_OVER 0x00000020U
	Overrun error interrupt. More...

#define	XUARTPS_IXR_TXFULL 0x00000010U
	TX FIFO full interrupt. More...

#define	XUARTPS_IXR_TXEMPTY 0x00000008U
	TX FIFO empty interrupt. More...

#define	XUARTPS_IXR_RXFULL 0x00000004U
	RX FIFO full interrupt. More...

#define	XUARTPS_IXR_RXEMPTY 0x00000002U
	RX FIFO empty interrupt. More...

#define	XUARTPS_IXR_RXOVR 0x00000001U
	RX FIFO trigger interrupt. More...

#define	XUARTPS_IXR_MASK 0x00003FFFU
	Valid bit mask. More...

Baud Rate Generator Register
The baud rate generator control register (BRGR) is a 16 bit register that controls the receiver bit sample clock and baud rate. Valid values are 1 - 65535. Bit Sample Rate = CCLK / BRGR, where the CCLK is selected by the MR_CCLK bit in the MR register.
#define	XUARTPS_BAUDGEN_DISABLE 0x00000000U
	Disable clock. More...

#define	XUARTPS_BAUDGEN_MASK 0x0000FFFFU
	Valid bits mask. More...

#define	XUARTPS_BAUDGEN_RESET_VAL 0x0000028BU
	Reset value. More...

Baud Divisor Rate register
The baud rate divider register (BDIV) controls how much the bit sample rate is divided by. It sets the baud rate. Valid values are 0x04 to 0xFF. Writing a value less than 4 will be ignored. Baud rate = CCLK / ((BAUDDIV + 1) x BRGR), where the CCLK is selected by the MR_CCLK bit in the MR register.
#define	XUARTPS_BAUDDIV_MASK 0x000000FFU
	8 bit baud divider mask More...

#define	XUARTPS_BAUDDIV_RESET_VAL 0x0000000FU
	Reset value. More...

Receiver Timeout Register
Use the receiver timeout register (RTR) to detect an idle condition on the receiver data line.
#define	XUARTPS_RXTOUT_DISABLE 0x00000000U
	Disable time out. More...

#define	XUARTPS_RXTOUT_MASK 0x000000FFU
	Valid bits mask. More...

Receiver FIFO Trigger Level Register
Use the Receiver FIFO Trigger Level Register (RTRIG) to set the value at which the RX FIFO triggers an interrupt event.
#define	XUARTPS_RXWM_DISABLE 0x00000000U
	Disable RX trigger interrupt. More...

#define	XUARTPS_RXWM_MASK 0x0000003FU
	Valid bits mask. More...

#define	XUARTPS_RXWM_RESET_VAL 0x00000020U
	Reset value. More...

Transmit FIFO Trigger Level Register
Use the Transmit FIFO Trigger Level Register (TTRIG) to set the value at which the TX FIFO triggers an interrupt event.
#define	XUARTPS_TXWM_MASK 0x0000003FU
	Valid bits mask. More...

#define	XUARTPS_TXWM_RESET_VAL 0x00000020U
	Reset value. More...

Modem Control Register
This register (MODEMCR) controls the interface with the modem or data set, or a peripheral device emulating a modem.
#define	XUARTPS_MODEMCR_FCM 0x00000020U
	Flow control mode. More...

#define	XUARTPS_MODEMCR_RTS 0x00000002U
	Request to send. More...

#define	XUARTPS_MODEMCR_DTR 0x00000001U
	Data terminal ready. More...

Modem Status Register
This register (MODEMSR) indicates the current state of the control lines from a modem, or another peripheral device, to the CPU. In addition, four bits of the modem status register provide change information. These bits are set to a logic 1 whenever a control input from the modem changes state. Note: Whenever the DCTS, DDSR, TERI, or DDCD bit is set to logic 1, a modem status interrupt is generated and this is reflected in the modem status register.
#define	XUARTPS_MODEMSR_FCMS 0x00000100U
	Flow control mode (FCMS) More...

#define	XUARTPS_MODEMSR_DCD 0x00000080U
	Complement of DCD input. More...

#define	XUARTPS_MODEMSR_RI 0x00000040U
	Complement of RI input. More...

#define	XUARTPS_MODEMSR_DSR 0x00000020U
	Complement of DSR input. More...

#define	XUARTPS_MODEMSR_CTS 0x00000010U
	Complement of CTS input. More...

#define	XUARTPS_MODEMSR_DDCD 0x00000008U
	Delta DCD indicator. More...

#define	XUARTPS_MODEMSR_TERI 0x00000004U
	Trailing Edge Ring Indicator. More...

#define	XUARTPS_MODEMSR_DDSR 0x00000002U
	Change of DSR. More...

#define	XUARTPS_MODEMSR_DCTS 0x00000001U
	Change of CTS. More...

Channel Status Register
The channel status register (CSR) is provided to enable the control logic to monitor the status of bits in the channel interrupt status register, even if these are masked out by the interrupt mask register.
#define	XUARTPS_SR_TNFUL 0x00004000U
	TX FIFO Nearly Full Status. More...

#define	XUARTPS_SR_TTRIG 0x00002000U
	TX FIFO Trigger Status. More...

#define	XUARTPS_SR_FLOWDEL 0x00001000U
	RX FIFO fill over flow delay. More...

#define	XUARTPS_SR_TACTIVE 0x00000800U
	TX active. More...

#define	XUARTPS_SR_RACTIVE 0x00000400U
	RX active. More...

#define	XUARTPS_SR_TXFULL 0x00000010U
	TX FIFO full. More...

#define	XUARTPS_SR_TXEMPTY 0x00000008U
	TX FIFO empty. More...

#define	XUARTPS_SR_RXFULL 0x00000004U
	RX FIFO full. More...

#define	XUARTPS_SR_RXEMPTY 0x00000002U
	RX FIFO empty. More...

#define	XUARTPS_SR_RXOVR 0x00000001U
	RX FIFO fill over trigger. More...

Flow Delay Register
Operation of the flow delay register (FLOWDEL) is very similar to the receive FIFO trigger register. An internal trigger signal activates when the FIFO is filled to the level set by this register. This trigger will not cause an interrupt, although it can be read through the channel status register. In hardware flow control mode, RTS is deactivated when the trigger becomes active. RTS only resets when the FIFO level is four less than the level of the flow delay trigger and the flow delay trigger is not activated. A value less than 4 disables the flow delay.
#define	XUARTPS_FLOWDEL_MASK XUARTPS_RXWM_MASK
	Valid bit mask. More...

Receiver FIFO Byte Status Register
The Receiver FIFO Status register is used to have a continuous monitoring of the raw unmasked byte status information. The register contains frame, parity and break status information for the top four bytes in the RX FIFO. Receiver FIFO Byte Status Register Bit Definition
#define	XUARTPS_RXBS_BYTE3_BRKE 0x00000800U
	Byte3 Break Error. More...

#define	XUARTPS_RXBS_BYTE3_FRME 0x00000400U
	Byte3 Frame Error. More...

#define	XUARTPS_RXBS_BYTE3_PARE 0x00000200U
	Byte3 Parity Error. More...

#define	XUARTPS_RXBS_BYTE2_BRKE 0x00000100U
	Byte2 Break Error. More...

#define	XUARTPS_RXBS_BYTE2_FRME 0x00000080U
	Byte2 Frame Error. More...

#define	XUARTPS_RXBS_BYTE2_PARE 0x00000040U
	Byte2 Parity Error. More...

#define	XUARTPS_RXBS_BYTE1_BRKE 0x00000020U
	Byte1 Break Error. More...

#define	XUARTPS_RXBS_BYTE1_FRME 0x00000010U
	Byte1 Frame Error. More...

#define	XUARTPS_RXBS_BYTE1_PARE 0x00000008U
	Byte1 Parity Error. More...

#define	XUARTPS_RXBS_BYTE0_BRKE 0x00000004U
	Byte0 Break Error. More...

#define	XUARTPS_RXBS_BYTE0_FRME 0x00000002U
	Byte0 Frame Error. More...

#define	XUARTPS_RXBS_BYTE0_PARE 0x00000001U
	Byte0 Parity Error. More...

#define	XUARTPS_RXBS_MASK 0x00000007U
	3 bit RX byte status mask More...

Macro Definition Documentation

#define TIMEOUT_VAL 1000000U

Wait for 1 sec in worst case.

Referenced by XUartPs_SelfTest().

#define XUARTPS_BAUDDIV_MASK 0x000000FFU

8 bit baud divider mask

#define XUARTPS_BAUDDIV_OFFSET 0x0034U

Baud Rate Divider [7:0].

Referenced by XUartPs_ResetHw(), and XUartPs_SetBaudRate().

#define XUARTPS_BAUDDIV_RESET_VAL 0x0000000FU

Reset value.

Referenced by XUartPs_ResetHw().

#define XUARTPS_BAUDGEN_DISABLE 0x00000000U

Disable clock.

#define XUARTPS_BAUDGEN_MASK 0x0000FFFFU

Valid bits mask.

#define XUARTPS_BAUDGEN_OFFSET 0x0018U

Baud Rate Generator [15:0].

Referenced by XUartPs_ResetHw(), and XUartPs_SetBaudRate().

#define XUARTPS_BAUDGEN_RESET_VAL 0x0000028BU

Reset value.

Referenced by XUartPs_ResetHw().

#define XUARTPS_CR_EN_DIS_MASK 0x0000003CU

Enable/disable Mask.

Referenced by UartPsEchoExample().

#define XUARTPS_CR_OFFSET 0x0000U

Control Register [8:0].

Referenced by UartPsEchoExample(), XUartPs_ResetHw(), XUartPs_SetBaudRate(), and XUartPs_SetRecvTimeout().

#define XUARTPS_CR_RX_DIS 0x00000008U

RX disabled.

Referenced by XUartPs_ResetHw().

#define XUARTPS_CR_RX_EN 0x00000004U

RX enabled.

Referenced by UartPsEchoExample().

#define XUARTPS_CR_RXRST 0x00000001U

RX logic reset.

Referenced by XUartPs_ResetHw(), and XUartPs_SetBaudRate().

#define XUARTPS_CR_STARTBRK 0x00000080U

Set break.

#define XUARTPS_CR_STOPBRK 0x00000100U

Stop transmission of break.

Referenced by XUartPs_ResetHw(), and XUartPs_SetOptions().

#define XUARTPS_CR_TORST 0x00000040U

RX timeout counter restart.

Referenced by XUartPs_SetRecvTimeout().

#define XUARTPS_CR_TX_DIS 0x00000020U

TX disabled.

Referenced by XUartPs_ResetHw().

#define XUARTPS_CR_TX_EN 0x00000010U

TX enabled.

Referenced by UartPsEchoExample().

#define XUARTPS_CR_TXRST 0x00000002U

TX logic reset.

Referenced by XUartPs_ResetHw(), and XUartPs_SetBaudRate().

#define XUartPs_DisableUart ( InstancePtr )

Value:

Xil_Out32(((InstancePtr)->Config.BaseAddress + (u32)XUARTPS_CR_OFFSET), \
          (((Xil_In32((InstancePtr)->Config.BaseAddress + (u32)XUARTPS_CR_OFFSET)) & \
          (u32)(~XUARTPS_CR_EN_DIS_MASK)) | ((u32)XUARTPS_CR_RX_DIS | (u32)XUARTPS_CR_TX_DIS)))

Disable the transmitter and receiver of the UART.

Parameters

InstancePtr is a pointer to the XUartPs instance.

Returns: None.

Note: C-Style signature: void XUartPs_DisableUart(XUartPs *InstancePtr)

Referenced by XUartPs_SetBaudRate().

#define XUartPs_EnableUart ( InstancePtr )

Value:

Xil_Out32(((InstancePtr)->Config.BaseAddress + (u32)XUARTPS_CR_OFFSET), \
          ((Xil_In32((InstancePtr)->Config.BaseAddress + (u32)XUARTPS_CR_OFFSET) & \
          (u32)(~XUARTPS_CR_EN_DIS_MASK)) | ((u32)XUARTPS_CR_RX_EN | (u32)XUARTPS_CR_TX_EN)))

Enable the transmitter and receiver of the UART.

Parameters

InstancePtr is a pointer to the XUartPs instance.

Returns: None.

Note: C-Style signature: void XUartPs_EnableUart(XUartPs *InstancePtr)

Referenced by XUartPs_SetBaudRate().

#define XUARTPS_EVENT_MODEM 5U

Modem status changed.

#define XUARTPS_EVENT_PARE_FRAME_BRKE 6U

A receive parity, frame, break error detected.

#define XUARTPS_EVENT_RECV_DATA 1U

Data receiving done.

#define XUARTPS_EVENT_RECV_ERROR 4U

A receive error detected.

#define XUARTPS_EVENT_RECV_ORERR 7U

A receive overrun error detected.

#define XUARTPS_EVENT_RECV_TOUT 2U

A receive timeout occurred.

#define XUARTPS_EVENT_SENT_DATA 3U

Data transmission done.

#define XUARTPS_FIFO_OFFSET 0x0030U

FIFO [7:0].

Referenced by UartPsEchoExample(), XUartPs_RecvByte(), and XUartPs_SendByte().

#define XUARTPS_FLOWDEL_MASK XUARTPS_RXWM_MASK

Valid bit mask.

Referenced by XUartPs_GetFlowDelay(), and XUartPs_SetFlowDelay().

#define XUARTPS_FLOWDEL_OFFSET 0x0038U

Flow Delay [5:0].

Referenced by XUartPs_GetFlowDelay(), and XUartPs_SetFlowDelay().

#define XUARTPS_FORMAT_1_5_STOP_BIT 1U

1.5 stop bits

#define XUARTPS_FORMAT_1_STOP_BIT 0U

1 stop bit

#define XUARTPS_FORMAT_2_STOP_BIT 2U

2 stop bits

Referenced by XUartPs_SetDataFormat().

#define XUARTPS_FORMAT_6_BITS 3U

6 data bits

Referenced by XUartPs_SetDataFormat().

#define XUARTPS_FORMAT_7_BITS 2U

7 data bits

#define XUARTPS_FORMAT_8_BITS 0U

8 data bits

#define XUARTPS_FORMAT_EVEN_PARITY 0U

Even parity.

#define XUARTPS_FORMAT_MARK_PARITY 3U

Mark parity.

#define XUARTPS_FORMAT_NO_PARITY 4U

No parity.

Referenced by XUartPs_SetDataFormat().

#define XUARTPS_FORMAT_ODD_PARITY 1U

Odd parity.

#define XUARTPS_FORMAT_SPACE_PARITY 2U

parity

#define XUartPs_GetChannelStatus ( InstancePtr ) Xil_In32(((InstancePtr)->Config.BaseAddress) + (u32)XUARTPS_SR_OFFSET)

Get the UART Channel Status Register.

Parameters

InstancePtr is a pointer to the XUartPs instance.

Returns: The value read from the register.

Note: C-Style signature: u16 XUartPs_GetChannelStatus(XUartPs *InstancePtr)

#define XUartPs_GetModeControl ( InstancePtr ) Xil_In32(((InstancePtr)->Config.BaseAddress) + (u32)XUARTPS_CR_OFFSET)

Get the UART Mode Control Register.

Parameters

InstancePtr is a pointer to the XUartPs instance.

Returns: The value read from the register.

Note: C-Style signature: u32 XUartPs_GetControl(XUartPs *InstancePtr)

#define XUARTPS_IDR_OFFSET 0x000CU

Interrupt Disable [12:0].

Referenced by XUartPs_CfgInitialize(), XUartPs_Recv(), XUartPs_ResetHw(), XUartPs_SelfTest(), XUartPs_Send(), and XUartPs_SetInterruptMask().

#define XUARTPS_IER_OFFSET 0x0008U

Interrupt Enable [12:0].

Referenced by XUartPs_Recv(), XUartPs_SelfTest(), and XUartPs_SetInterruptMask().

#define XUARTPS_IMR_OFFSET 0x0010U

Interrupt Mask [12:0].

Referenced by XUartPs_GetInterruptMask(), XUartPs_InterruptHandler(), XUartPs_Recv(), and XUartPs_SelfTest().

#define XUARTPS_ISR_OFFSET 0x0014U

Interrupt Status [12:0].

Referenced by XUartPs_InterruptHandler(), and XUartPs_ResetHw().

#define XUartPs_IsReceiveData ( BaseAddress )

Value:

!((Xil_In32((BaseAddress) + XUARTPS_SR_OFFSET) & \

(u32)XUARTPS_SR_RXEMPTY) == (u32)XUARTPS_SR_RXEMPTY)

XUARTPS_SR_OFFSET

#define XUARTPS_SR_OFFSET

Channel Status [14:0].

Definition: xuartps_hw.h:71

XUARTPS_SR_RXEMPTY

#define XUARTPS_SR_RXEMPTY

RX FIFO empty.

Definition: xuartps_hw.h:282

Determine if there is receive data in the receiver and/or FIFO.

Parameters

BaseAddress contains the base address of the device.

Returns: TRUE if there is receive data, FALSE otherwise.

Note: C-Style signature: u32 XUartPs_IsReceiveData(u32 BaseAddress)

Referenced by UartPsEchoExample(), and XUartPs_RecvByte().

#define XUartPs_IsTransmitEmpty ( InstancePtr )

Value:

((Xil_In32(((InstancePtr)->Config.BaseAddress) + (u32)XUARTPS_SR_OFFSET) & \

(u32)XUARTPS_SR_TXEMPTY) == (u32)XUARTPS_SR_TXEMPTY)

XUARTPS_SR_OFFSET

#define XUARTPS_SR_OFFSET

Channel Status [14:0].

Definition: xuartps_hw.h:71

XUARTPS_SR_TXEMPTY

#define XUARTPS_SR_TXEMPTY

TX FIFO empty.

Definition: xuartps_hw.h:280

Determine if the transmitter FIFO is empty.

Parameters

InstancePtr is a pointer to the XUartPs instance.

Returns

TRUE if a byte can be sent
FALSE if the Transmitter Fifo is not empty

Note: C-Style signature: u32 XUartPs_IsTransmitEmpty(XUartPs InstancePtr)

#define XUartPs_IsTransmitFull ( BaseAddress )

Value:

((Xil_In32((BaseAddress) + XUARTPS_SR_OFFSET) & \

(u32)XUARTPS_SR_TXFULL) == (u32)XUARTPS_SR_TXFULL)

XUARTPS_SR_OFFSET

#define XUARTPS_SR_OFFSET

Channel Status [14:0].

Definition: xuartps_hw.h:71

XUARTPS_SR_TXFULL

#define XUARTPS_SR_TXFULL

TX FIFO full.

Definition: xuartps_hw.h:279

Determine if a byte of data can be sent with the transmitter.

Parameters

BaseAddress contains the base address of the device.

Returns: TRUE if the TX FIFO is full, FALSE if a byte can be put in the FIFO.

Note: C-Style signature: u32 XUartPs_IsTransmitFull(u32 BaseAddress)

Referenced by UartPsEchoExample(), and XUartPs_SendByte().

#define XUARTPS_IXR_DMS 0x00000200U

Modem status change interrupt.

Referenced by XUartPs_InterruptHandler().

#define XUARTPS_IXR_FRAMING 0x00000040U

Framing error interrupt.

Referenced by UartPsIntrExample(), and XUartPs_InterruptHandler().

#define XUARTPS_IXR_MASK 0x00003FFFU

Valid bit mask.

Referenced by XUartPs_CfgInitialize(), XUartPs_Recv(), XUartPs_ResetHw(), XUartPs_SelfTest(), and XUartPs_SetInterruptMask().

#define XUARTPS_IXR_OVER 0x00000020U

Overrun error interrupt.

Referenced by UartPsIntrExample(), and XUartPs_InterruptHandler().

#define XUARTPS_IXR_PARITY 0x00000080U

Parity error interrupt.

Referenced by UartPsIntrExample(), and XUartPs_InterruptHandler().

#define XUARTPS_IXR_RBRK 0x00002000U

Rx FIFO break detect interrupt.

Referenced by UartPsIntrExample(), and XUartPs_InterruptHandler().

#define XUARTPS_IXR_RXEMPTY 0x00000002U

RX FIFO empty interrupt.

Referenced by XUartPs_InterruptHandler().

#define XUARTPS_IXR_RXFULL 0x00000004U

RX FIFO full interrupt.

Referenced by UartPsIntrExample(), and XUartPs_InterruptHandler().

#define XUARTPS_IXR_RXOVR 0x00000001U

RX FIFO trigger interrupt.

Referenced by UartPsIntrExample(), and XUartPs_InterruptHandler().

#define XUARTPS_IXR_TNFUL 0x00000800U

Tx FIFO Nearly Full interrupt.

#define XUARTPS_IXR_TOUT 0x00000100U

Timeout error interrupt.

Referenced by UartPsIntrExample(), and XUartPs_InterruptHandler().

#define XUARTPS_IXR_TOVR 0x00001000U

Tx FIFO Overflow interrupt.

#define XUARTPS_IXR_TTRIG 0x00000400U

Tx Trig interrupt.

#define XUARTPS_IXR_TXEMPTY 0x00000008U

TX FIFO empty interrupt.

Referenced by UartPsIntrExample(), XUartPs_InterruptHandler(), and XUartPs_Send().

#define XUARTPS_IXR_TXFULL 0x00000010U

TX FIFO full interrupt.

Referenced by XUartPs_InterruptHandler(), and XUartPs_Send().

#define XUARTPS_MODEMCR_DTR 0x00000001U

Data terminal ready.

#define XUARTPS_MODEMCR_FCM 0x00000020U

Flow control mode.

#define XUARTPS_MODEMCR_OFFSET 0x0024U

Modem Control [5:0].

#define XUARTPS_MODEMCR_RTS 0x00000002U

Request to send.

#define XUARTPS_MODEMSR_CTS 0x00000010U

Complement of CTS input.

#define XUARTPS_MODEMSR_DCD 0x00000080U

Complement of DCD input.

#define XUARTPS_MODEMSR_DCTS 0x00000001U

Change of CTS.

#define XUARTPS_MODEMSR_DDCD 0x00000008U

Delta DCD indicator.

#define XUARTPS_MODEMSR_DDSR 0x00000002U

Change of DSR.

#define XUARTPS_MODEMSR_DSR 0x00000020U

Complement of DSR input.

#define XUARTPS_MODEMSR_FCMS 0x00000100U

Flow control mode (FCMS)

#define XUARTPS_MODEMSR_OFFSET 0x0028U

Modem Status [8:0].

Referenced by XUartPs_GetModemStatus().

#define XUARTPS_MODEMSR_RI 0x00000040U

Complement of RI input.

#define XUARTPS_MODEMSR_TERI 0x00000004U

Trailing Edge Ring Indicator.

#define XUARTPS_MR_CCLK 0x00000400U

Input clock selection.

#define XUARTPS_MR_CHARLEN_6_BIT 0x00000006U

6 bits data

#define XUARTPS_MR_CHARLEN_7_BIT 0x00000004U

7 bits data

#define XUARTPS_MR_CHARLEN_8_BIT 0x00000000U

8 bits data

Referenced by XUartPs_CfgInitialize().

#define XUARTPS_MR_CHARLEN_MASK 0x00000006U

Data length mask.

Referenced by XUartPs_CfgInitialize(), XUartPs_GetDataFormat(), and XUartPs_SetDataFormat().

#define XUARTPS_MR_CHARLEN_SHIFT 1U

Data Length shift.

Referenced by XUartPs_GetDataFormat(), and XUartPs_SetDataFormat().

#define XUARTPS_MR_CHMODE_ECHO 0x00000100U

Auto echo mode.

Referenced by XUartPs_GetOperMode(), and XUartPs_SetOperMode().

#define XUARTPS_MR_CHMODE_L_LOOP 0x00000200U

Local loopback mode.

Referenced by XUartPs_GetOperMode(), XUartPs_SelfTest(), and XUartPs_SetOperMode().

#define XUARTPS_MR_CHMODE_MASK 0x00000300U

Mode mask.

Referenced by XUartPs_GetOperMode(), XUartPs_SelfTest(), and XUartPs_SetOperMode().

#define XUARTPS_MR_CHMODE_NORM 0x00000000U

Normal mode.

Referenced by XUartPs_GetOperMode(), XUartPs_ResetHw(), and XUartPs_SetOperMode().

#define XUARTPS_MR_CHMODE_R_LOOP 0x00000300U

Remote loopback mode.

Referenced by XUartPs_GetOperMode(), and XUartPs_SetOperMode().

#define XUARTPS_MR_CHMODE_SHIFT 8U

Mode shift.

Referenced by XUartPs_GetOperMode().

#define XUARTPS_MR_CLKSEL 0x00000001U

Input clock selection.

Referenced by XUartPs_SetBaudRate().

#define XUARTPS_MR_OFFSET 0x0004U

Mode Register [9:0].

Referenced by XUartPs_CfgInitialize(), XUartPs_GetDataFormat(), XUartPs_GetOperMode(), XUartPs_ResetHw(), XUartPs_SelfTest(), XUartPs_SetBaudRate(), XUartPs_SetDataFormat(), and XUartPs_SetOperMode().

#define XUARTPS_MR_PARITY_EVEN 0x00000000U

Even parity mode.

#define XUARTPS_MR_PARITY_MARK 0x00000018U

Mark parity mode.

#define XUARTPS_MR_PARITY_MASK 0x00000038U

Parity mask.

Referenced by XUartPs_CfgInitialize(), XUartPs_GetDataFormat(), and XUartPs_SetDataFormat().

#define XUARTPS_MR_PARITY_NONE 0x00000020U

No parity mode.

Referenced by XUartPs_CfgInitialize().

#define XUARTPS_MR_PARITY_ODD 0x00000008U

Odd parity mode.

#define XUARTPS_MR_PARITY_SHIFT 3U

Parity setting shift.

Referenced by XUartPs_GetDataFormat(), and XUartPs_SetDataFormat().

#define XUARTPS_MR_PARITY_SPACE 0x00000010U

Space parity mode.

#define XUARTPS_MR_STOPMODE_1_5_BIT 0x00000040U

1.5 stop bits

#define XUARTPS_MR_STOPMODE_1_BIT 0x00000000U

1 stop bit

Referenced by XUartPs_CfgInitialize().

#define XUARTPS_MR_STOPMODE_2_BIT 0x00000080U

2 stop bits

#define XUARTPS_MR_STOPMODE_MASK 0x000000A0U

Stop bits mask.

Referenced by XUartPs_CfgInitialize(), XUartPs_GetDataFormat(), and XUartPs_SetDataFormat().

#define XUARTPS_MR_STOPMODE_SHIFT 6U

Stop bits shift.

Referenced by XUartPs_GetDataFormat(), and XUartPs_SetDataFormat().

#define XUARTPS_OPER_MODE_AUTO_ECHO (u8)0x01U

Auto Echo Mode.

Referenced by XUartPs_GetOperMode(), and XUartPs_SetOperMode().

#define XUARTPS_OPER_MODE_LOCAL_LOOP (u8)0x02U

Local Loopback Mode.

Referenced by UartPsIntrExample(), UartPsPolledExample(), XUartPs_GetOperMode(), and XUartPs_SetOperMode().

#define XUARTPS_OPER_MODE_NORMAL (u8)0x00U

Normal Mode.

Referenced by UartPsIntrExample(), UartPsPolledExample(), XUartPs_GetOperMode(), and XUartPs_SetOperMode().

#define XUARTPS_OPER_MODE_REMOTE_LOOP (u8)0x03U

Remote Loopback Mode.

Referenced by XUartPs_GetOperMode(), and XUartPs_SetOperMode().

#define XUARTPS_OPTION_ASSERT_DTR 0x0002U

Assert the DTR bit.

#define XUARTPS_OPTION_ASSERT_RTS 0x0004U

Assert the RTS bit.

#define XUARTPS_OPTION_RESET_RX 0x0008U

Reset the receiver.

#define XUARTPS_OPTION_RESET_TMOUT 0x0020U

Reset the receive timeout.

#define XUARTPS_OPTION_RESET_TX 0x0010U

Reset the transmitter.

#define XUARTPS_OPTION_SET_BREAK 0x0080U

These constants specify the options that may be set or retrieved with the driver, each is a unique bit mask such that multiple options may be specified.

These constants indicate the available options in active state.Starts break transmission

Referenced by XUartPs_SetOptions().

#define XUARTPS_OPTION_SET_FCM 0x0001U

Turn on flow control mode.

#define XUARTPS_OPTION_STOP_BREAK 0x0040U

Stops break transmission.

#define XUartPs_ReadReg	(	BaseAddress,
		RegOffset
	)	Xil_In32((BaseAddress) + (u32)(RegOffset))

Read a UART register.

Parameters

BaseAddress	contains the base address of the device.
RegOffset	contains the offset from the base address of the device.

Returns: The value read from the register.

Note: C-Style signature: u32 XUartPs_ReadReg(u32 BaseAddress, int RegOffset)

Referenced by UartPsEchoExample(), XUartPs_CfgInitialize(), XUartPs_GetDataFormat(), XUartPs_GetFifoThreshold(), XUartPs_GetFlowDelay(), XUartPs_GetInterruptMask(), XUartPs_GetModemStatus(), XUartPs_GetOperMode(), XUartPs_GetOptions(), XUartPs_GetRecvTimeout(), XUartPs_InterruptHandler(), XUartPs_IsSending(), XUartPs_Recv(), XUartPs_RecvByte(), XUartPs_SelfTest(), XUartPs_SetBaudRate(), XUartPs_SetDataFormat(), XUartPs_SetOperMode(), XUartPs_SetOptions(), and XUartPs_SetRecvTimeout().

#define XUARTPS_RXBS_BYTE0_BRKE 0x00000004U

Byte0 Break Error.

#define XUARTPS_RXBS_BYTE0_FRME 0x00000002U

Byte0 Frame Error.

#define XUARTPS_RXBS_BYTE0_PARE 0x00000001U

Byte0 Parity Error.

#define XUARTPS_RXBS_BYTE1_BRKE 0x00000020U

Byte1 Break Error.

#define XUARTPS_RXBS_BYTE1_FRME 0x00000010U

Byte1 Frame Error.

#define XUARTPS_RXBS_BYTE1_PARE 0x00000008U

Byte1 Parity Error.

#define XUARTPS_RXBS_BYTE2_BRKE 0x00000100U

Byte2 Break Error.

#define XUARTPS_RXBS_BYTE2_FRME 0x00000080U

Byte2 Frame Error.

#define XUARTPS_RXBS_BYTE2_PARE 0x00000040U

Byte2 Parity Error.

#define XUARTPS_RXBS_BYTE3_BRKE 0x00000800U

Byte3 Break Error.

#define XUARTPS_RXBS_BYTE3_FRME 0x00000400U

Byte3 Frame Error.

#define XUARTPS_RXBS_BYTE3_PARE 0x00000200U

Byte3 Parity Error.

#define XUARTPS_RXBS_MASK 0x00000007U

3 bit RX byte status mask

#define XUARTPS_RXBS_OFFSET 0x0048U

RX FIFO Byte Status [11:0].

#define XUARTPS_RXTOUT_DISABLE 0x00000000U

Disable time out.

Referenced by XUartPs_ResetHw().

#define XUARTPS_RXTOUT_MASK 0x000000FFU

Valid bits mask.

Referenced by XUartPs_GetRecvTimeout(), and XUartPs_SetRecvTimeout().

#define XUARTPS_RXTOUT_OFFSET 0x001CU

RX Timeout [7:0].

Referenced by XUartPs_CfgInitialize(), XUartPs_GetRecvTimeout(), XUartPs_ResetHw(), and XUartPs_SetRecvTimeout().

#define XUARTPS_RXWM_DISABLE 0x00000000U

Disable RX trigger interrupt.

#define XUARTPS_RXWM_MASK 0x0000003FU

Valid bits mask.

Referenced by XUartPs_GetFifoThreshold(), and XUartPs_SetFifoThreshold().

#define XUARTPS_RXWM_OFFSET 0x0020U

RX FIFO Trigger Level [5:0].

Referenced by XUartPs_CfgInitialize(), XUartPs_GetFifoThreshold(), XUartPs_ResetHw(), and XUartPs_SetFifoThreshold().

#define XUARTPS_RXWM_RESET_VAL 0x00000020U

Reset value.

Referenced by XUartPs_ResetHw().

#define XUartPs_SetModeControl	(	InstancePtr,
		RegisterValue
	)

Value:

Xil_Out32(((InstancePtr)->Config.BaseAddress) + (u32)XUARTPS_CR_OFFSET, \

(u32)(RegisterValue))

XUARTPS_CR_OFFSET

#define XUARTPS_CR_OFFSET

Control Register [8:0].

Definition: xuartps_hw.h:60

Set the UART Mode Control Register.

Parameters

InstancePtr	is a pointer to the XUartPs instance.
RegisterValue	is the value to be written to the register.

Returns: None.

Note: C-Style signature: void XUartPs_SetModeControl(XUartPs *InstancePtr, u16 RegisterValue)

#define XUARTPS_SR_FLOWDEL 0x00001000U

RX FIFO fill over flow delay.

#define XUARTPS_SR_OFFSET 0x002CU

Channel Status [14:0].

Referenced by XUartPs_IsSending(), and XUartPs_SelfTest().

#define XUARTPS_SR_RACTIVE 0x00000400U

RX active.

#define XUARTPS_SR_RXEMPTY 0x00000002U

RX FIFO empty.

Referenced by XUartPs_SelfTest().

#define XUARTPS_SR_RXFULL 0x00000004U

RX FIFO full.

#define XUARTPS_SR_RXOVR 0x00000001U

RX FIFO fill over trigger.

#define XUARTPS_SR_TACTIVE 0x00000800U

TX active.

Referenced by XUartPs_IsSending().

#define XUARTPS_SR_TNFUL 0x00004000U

TX FIFO Nearly Full Status.

#define XUARTPS_SR_TTRIG 0x00002000U

TX FIFO Trigger Status.

#define XUARTPS_SR_TXEMPTY 0x00000008U

TX FIFO empty.

Referenced by XUartPs_IsSending().

#define XUARTPS_SR_TXFULL 0x00000010U

TX FIFO full.

#define XUARTPS_TXWM_MASK 0x0000003FU

Valid bits mask.

#define XUARTPS_TXWM_OFFSET 0x0044U

TX FIFO Trigger Level [5:0].

Referenced by XUartPs_ResetHw().

#define XUARTPS_TXWM_RESET_VAL 0x00000020U

Reset value.

Referenced by XUartPs_ResetHw().

#define XUartPs_WriteReg	(	BaseAddress,
		RegOffset,
		RegisterValue
	)	Xil_Out32((BaseAddress) + (u32)(RegOffset), (u32)(RegisterValue))

Write a UART register.

Parameters

BaseAddress	contains the base address of the device.
RegOffset	contains the offset from the base address of the device.
RegisterValue	is the value to be written to the register.

Returns: None.

Note: C-Style signature: void XUartPs_WriteReg(u32 BaseAddress, int RegOffset, u16 RegisterValue)

Referenced by UartPsEchoExample(), XUartPs_CfgInitialize(), XUartPs_InterruptHandler(), XUartPs_Recv(), XUartPs_ResetHw(), XUartPs_SelfTest(), XUartPs_Send(), XUartPs_SendByte(), XUartPs_SetBaudRate(), XUartPs_SetDataFormat(), XUartPs_SetFifoThreshold(), XUartPs_SetFlowDelay(), XUartPs_SetInterruptMask(), XUartPs_SetOperMode(), XUartPs_SetOptions(), and XUartPs_SetRecvTimeout().

Typedef Documentation

void Handler

This function is the handler which performs processing to handle data events from the device.

It is called from an interrupt context. so the amount of processing should be minimal.

This handler provides an example of how to handle data for the device and is application specific.

Parameters

CallBackRef	contains a callback reference from the driver, in this case it is the instance pointer for the XUartPs driver.
Event	contains the specific kind of event that has occurred.
EventData	contains the number of bytes sent or received for sent and receive events.

Returns: None.

Note: None.

typedef void(* XUartPs_Handler)(void *CallBackRef, u32 Event, u32 EventData)

This data type defines a handler that an application defines to communicate with interrupt system to retrieve state information about an application.

Parameters

CallBackRef	is a callback reference passed in by the upper layer when setting the handler, and is passed back to the upper layer when the handler is called. It is used to find the device driver instance.
Event	contains one of the event constants indicating events that have occurred.
EventData	contains the number of bytes sent or received at the time of the call for send and receive events and contains the modem status for modem events.

Function Documentation

s32 XUartPs_CfgInitialize	(	XUartPs *	InstancePtr,
		XUartPs_Config *	Config,
		u32	EffectiveAddr
	)

Initializes a specific XUartPs instance such that it is ready to be used.

The data format of the device is setup for 8 data bits, 1 stop bit, and no parity by default. The baud rate is set to a default value specified by Config->DefaultBaudRate if set, otherwise it is set to 19.2K baud. The receive FIFO threshold is set for 8 bytes. The default operating mode of the driver is polled mode.

Parameters

InstancePtr	is a pointer to the XUartPs instance.
Config	is a reference to a structure containing information about a specific XUartPs driver.
EffectiveAddr	is the device base address in the virtual memory address space. The caller is responsible for keeping the address mapping from EffectiveAddr to the device physical base address unchanged once this function is invoked. Unexpected errors may occur if the address mapping changes after this function is called. If address translation is not used, pass in the physical address instead.

Returns

    - XST_SUCCESS if initialization was successful
    - XST_UART_BAUD_ERROR if the baud rate is not possible because
      the inputclock frequency is not divisible with an acceptable
      amount of error

Note

The default configuration for the UART after initialization is:

19,200 bps or XPAR_DFT_BAUDRATE if defined
8 data bits
1 stop bit
no parity
FIFO's are enabled with a receive threshold of 8 bytes
The RX timeout is enabled with a timeout of 1 (4 char times)

All interrupts are disabled.

References XUartPs_Config::BaseAddress, XUartPs_Config::InputClockHz, XUARTPS_IDR_OFFSET, XUARTPS_IXR_MASK, XUARTPS_MR_CHARLEN_8_BIT, XUARTPS_MR_CHARLEN_MASK, XUARTPS_MR_OFFSET, XUARTPS_MR_PARITY_MASK, XUARTPS_MR_PARITY_NONE, XUARTPS_MR_STOPMODE_1_BIT, XUARTPS_MR_STOPMODE_MASK, XUartPs_ReadReg, XUARTPS_RXTOUT_OFFSET, XUARTPS_RXWM_OFFSET, XUartPs_SetBaudRate(), and XUartPs_WriteReg.

Referenced by UartPsHelloWorldExample(), UartPsIntrExample(), UartPsPolledExample(), and UartPsSelfTestExample().

void XUartPs_GetDataFormat	(	XUartPs *	InstancePtr,
		XUartPsFormat *	FormatPtr
	)

Gets the data format for the specified UART.

The data format includes the baud rate, number of data bits, number of stop bits, and parity.

Parameters

InstancePtr	is a pointer to the XUartPs instance.
FormatPtr	is a pointer to a format structure that will contain the data format after this call completes.

Returns: None.

Note: None.

References XUartPs_Config::BaseAddress, XUartPsFormat::BaudRate, XUartPsFormat::DataBits, XUartPsFormat::Parity, XUartPsFormat::StopBits, XUARTPS_MR_CHARLEN_MASK, XUARTPS_MR_CHARLEN_SHIFT, XUARTPS_MR_OFFSET, XUARTPS_MR_PARITY_MASK, XUARTPS_MR_PARITY_SHIFT, XUARTPS_MR_STOPMODE_MASK, XUARTPS_MR_STOPMODE_SHIFT, and XUartPs_ReadReg.

u8 XUartPs_GetFifoThreshold ( XUartPs * InstancePtr )

This function gets the receive FIFO trigger level.

The receive trigger level indicates the number of bytes in the receive FIFO that cause a receive data event (interrupt) to be generated.

Parameters

InstancePtr is a pointer to the XUartPs instance.

Returns: The current receive FIFO trigger level. This is a value from 0-31.

Note: None.

References XUartPs_Config::BaseAddress, XUartPs_ReadReg, XUARTPS_RXWM_MASK, and XUARTPS_RXWM_OFFSET.

u8 XUartPs_GetFlowDelay ( XUartPs * InstancePtr )

This function sets the Flow Delay.

0 - 3: Flow delay inactive 4 - 32: If Flow Control mode is enabled, UART_rtsN is deactivated when the receive FIFO fills to this level.

Parameters

InstancePtr is a pointer to the XUartPs instance.

Returns

The Flow Delay is specified by constants defined in xuartps_hw.h. The constants are named XUARTPS_FLOWDEL*

Note: None.

References XUartPs_Config::BaseAddress, XUARTPS_FLOWDEL_MASK, XUARTPS_FLOWDEL_OFFSET, and XUartPs_ReadReg.

u32 XUartPs_GetInterruptMask ( XUartPs * InstancePtr )

This function gets the interrupt mask.

Parameters

InstancePtr is a pointer to the XUartPs instance.

Returns: The current interrupt mask. The mask indicates which interrupts are enabled.

Note: None.

References XUartPs_Config::BaseAddress, XUARTPS_IMR_OFFSET, and XUartPs_ReadReg.

u16 XUartPs_GetModemStatus ( XUartPs * InstancePtr )

This function gets the modem status from the specified UART.

The modem status indicates any changes of the modem signals. This function allows the modem status to be read in a polled mode. The modem status is updated whenever it is read such that reading it twice may not yield the same results.

Parameters

InstancePtr is a pointer to the XUartPs instance.

Returns

The modem status which are bit masks that are contained in the file xuartps.h and named XUARTPS_MODEM_*.

Note

The bit masks used for the modem status are the exact bits of the modem status register with no abstraction.

References XUartPs_Config::BaseAddress, XUARTPS_MODEMSR_OFFSET, and XUartPs_ReadReg.

u8 XUartPs_GetOperMode ( XUartPs * InstancePtr )

This function gets the operational mode of the UART.

The UART can operate in one of four modes: Normal, Local Loopback, Remote Loopback, or automatic echo.

Parameters

InstancePtr is a pointer to the XUartPs instance.

Returns

The operational mode is specified by constants defined in xuartps.h. The constants are named XUARTPS_OPER_MODE_*

Note: None.

References XUartPs_Config::BaseAddress, XUARTPS_MR_CHMODE_ECHO, XUARTPS_MR_CHMODE_L_LOOP, XUARTPS_MR_CHMODE_MASK, XUARTPS_MR_CHMODE_NORM, XUARTPS_MR_CHMODE_R_LOOP, XUARTPS_MR_CHMODE_SHIFT, XUARTPS_MR_OFFSET, XUARTPS_OPER_MODE_AUTO_ECHO, XUARTPS_OPER_MODE_LOCAL_LOOP, XUARTPS_OPER_MODE_NORMAL, XUARTPS_OPER_MODE_REMOTE_LOOP, and XUartPs_ReadReg.

u16 XUartPs_GetOptions ( XUartPs * InstancePtr )

Gets the options for the specified driver instance.

The options are implemented as bit masks such that multiple options may be enabled or disabled simultaneously.

Parameters

InstancePtr is a pointer to the XUartPs instance.

Returns

The current options for the UART. The options are bit masks that are contained in the file xuartps.h and named XUARTPS_OPTION_*.

Note: None.

References XUartPs_Config::BaseAddress, and XUartPs_ReadReg.

u8 XUartPs_GetRecvTimeout ( XUartPs * InstancePtr )

This function gets the Receive Timeout of the UART.

Parameters

InstancePtr is a pointer to the XUartPs instance.

Returns: The current setting for receive time out.

Note: None.

References XUartPs_Config::BaseAddress, XUartPs_ReadReg, XUARTPS_RXTOUT_MASK, and XUARTPS_RXTOUT_OFFSET.

void XUartPs_InterruptHandler ( XUartPs * InstancePtr )

This function is the interrupt handler for the driver.

It must be connected to an interrupt system by the application such that it can be called when an interrupt occurs.

Parameters

InstancePtr contains a pointer to the driver instance

Returns: None.

Note: None.

References XUartPs_Config::BaseAddress, XUARTPS_IMR_OFFSET, XUARTPS_ISR_OFFSET, XUARTPS_IXR_DMS, XUARTPS_IXR_FRAMING, XUARTPS_IXR_OVER, XUARTPS_IXR_PARITY, XUARTPS_IXR_RBRK, XUARTPS_IXR_RXEMPTY, XUARTPS_IXR_RXFULL, XUARTPS_IXR_RXOVR, XUARTPS_IXR_TOUT, XUARTPS_IXR_TXEMPTY, XUARTPS_IXR_TXFULL, XUartPs_ReadReg, and XUartPs_WriteReg.

Referenced by UartPsIntrExample().

u32 XUartPs_IsSending ( XUartPs * InstancePtr )

This function determines if the specified UART is sending data.

Parameters

InstancePtr is a pointer to the XUartPs instance.

Returns

TRUE if the UART is sending data
FALSE if UART is not sending data

Note: None.

References XUartPs_Config::BaseAddress, XUartPs_ReadReg, XUARTPS_SR_OFFSET, XUARTPS_SR_TACTIVE, and XUARTPS_SR_TXEMPTY.

Referenced by UartPsPolledExample().

XUartPs_Config * XUartPs_LookupConfig ( u16 DeviceId )

Looks up the device configuration based on the unique device ID.

The table contains the configuration info for each device in the system.

Parameters

DeviceId contains the ID of the device

Returns: A pointer to the configuration structure or NULL if the specified device is not in the system.

Note: None.

Referenced by UartPsHelloWorldExample(), UartPsIntrExample(), UartPsPolledExample(), and UartPsSelfTestExample().

u32 XUartPs_Recv	(	XUartPs *	InstancePtr,
		u8 *	BufferPtr,
		u32	NumBytes
	)

This function attempts to receive a specified number of bytes of data from the device and store it into the specified buffer.

This function works for both polled or interrupt driven modes. It is non-blocking.

In a polled mode, this function will only receive the data already in the RX FIFO. The application may need to call it repeatedly to receive the entire buffer. Polled mode is the default mode of operation for the device.

In interrupt mode, this function will start the receiving, if not the entire buffer has been received, the interrupt handler will continue receiving data until the entire buffer has been received. A callback function, as specified by the application, will be called to indicate the completion of the receiving or error conditions.

Parameters

InstancePtr	is a pointer to the XUartPs instance
BufferPtr	is pointer to buffer for data to be received into
NumBytes	is the number of bytes to be received. A value of zero will stop a previous receive operation that is in progress in interrupt mode.

Returns: The number of bytes received.

Note

The number of bytes is not asserted so that this function may be called with a value of zero to stop an operation that is already in progress.

References XUartPs_Config::BaseAddress, XUARTPS_IDR_OFFSET, XUARTPS_IER_OFFSET, XUARTPS_IMR_OFFSET, XUARTPS_IXR_MASK, XUartPs_ReadReg, and XUartPs_WriteReg.

Referenced by UartPsIntrExample(), UartPsPolledExample(), and XUartPs_SelfTest().

u8 XUartPs_RecvByte ( u32 BaseAddress )

This function receives a byte from the device.

It operates in polled mode and blocks until a byte has received.

Parameters

BaseAddress contains the base address of the device.

Returns: The data byte received.

Note: None.

References XUARTPS_FIFO_OFFSET, XUartPs_IsReceiveData, and XUartPs_ReadReg.

void XUartPs_ResetHw ( u32 BaseAddress )

This function resets UART.

Parameters

BaseAddress contains the base address of the device.

Returns: None

Note: None.

References XUARTPS_BAUDDIV_OFFSET, XUARTPS_BAUDDIV_RESET_VAL, XUARTPS_BAUDGEN_OFFSET, XUARTPS_BAUDGEN_RESET_VAL, XUARTPS_CR_OFFSET, XUARTPS_CR_RX_DIS, XUARTPS_CR_RXRST, XUARTPS_CR_STOPBRK, XUARTPS_CR_TX_DIS, XUARTPS_CR_TXRST, XUARTPS_IDR_OFFSET, XUARTPS_ISR_OFFSET, XUARTPS_IXR_MASK, XUARTPS_MR_CHMODE_NORM, XUARTPS_MR_OFFSET, XUARTPS_RXTOUT_DISABLE, XUARTPS_RXTOUT_OFFSET, XUARTPS_RXWM_OFFSET, XUARTPS_RXWM_RESET_VAL, XUARTPS_TXWM_OFFSET, XUARTPS_TXWM_RESET_VAL, and XUartPs_WriteReg.

s32 XUartPs_SelfTest ( XUartPs * InstancePtr )

This function runs a self-test on the driver and hardware device.

This self test performs a local loopback and verifies data can be sent and received.

The time for this test is proportional to the baud rate that has been set prior to calling this function.

The mode and control registers are restored before return.

Parameters

InstancePtr is a pointer to the XUartPs instance

Returns

XST_SUCCESS if the test was successful

XST_UART_TEST_FAIL if the test failed looping back the data

Note

This function can hang if the hardware is not functioning properly.

References XUartPs_Config::BaseAddress, TIMEOUT_VAL, XUARTPS_IDR_OFFSET, XUARTPS_IER_OFFSET, XUARTPS_IMR_OFFSET, XUARTPS_IXR_MASK, XUARTPS_MR_CHMODE_L_LOOP, XUARTPS_MR_CHMODE_MASK, XUARTPS_MR_OFFSET, XUartPs_ReadReg, XUartPs_Recv(), XUartPs_Send(), XUARTPS_SR_OFFSET, XUARTPS_SR_RXEMPTY, and XUartPs_WriteReg.

Referenced by UartPsIntrExample(), UartPsPolledExample(), and UartPsSelfTestExample().

u32 XUartPs_Send	(	XUartPs *	InstancePtr,
		u8 *	BufferPtr,
		u32	NumBytes
	)

This functions sends the specified buffer using the device in either polled or interrupt driven mode.

This function is non-blocking, if the device is busy sending data, it will return and indicate zero bytes were sent. Otherwise, it fills the TX FIFO as much as it can, and return the number of bytes sent.

In a polled mode, this function will only send as much data as TX FIFO can buffer. The application may need to call it repeatedly to send the entire buffer.

In interrupt mode, this function will start sending the specified buffer, then the interrupt handler will continue sending data until the entire buffer has been sent. A callback function, as specified by the application, will be called to indicate the completion of sending.

Parameters

InstancePtr	is a pointer to the XUartPs instance.
BufferPtr	is pointer to a buffer of data to be sent.
NumBytes	contains the number of bytes to be sent. A value of zero will stop a previous send operation that is in progress in interrupt mode. Any data that was already put into the transmit FIFO will be sent.

Returns: The number of bytes actually sent.

Note

The number of bytes is not asserted so that this function may be called with a value of zero to stop an operation that is already in progress.

References XUartPs_Config::BaseAddress, XUARTPS_IDR_OFFSET, XUARTPS_IXR_TXEMPTY, XUARTPS_IXR_TXFULL, and XUartPs_WriteReg.

Referenced by UartPsHelloWorldExample(), UartPsIntrExample(), UartPsPolledExample(), and XUartPs_SelfTest().

void XUartPs_SendByte	(	u32	BaseAddress,
		u8	Data
	)

This function sends one byte using the device.

This function operates in polled mode and blocks until the data has been put into the TX FIFO register.

Parameters

BaseAddress	contains the base address of the device.
Data	contains the byte to be sent.

Returns: None.

Note: None.

References XUARTPS_FIFO_OFFSET, XUartPs_IsTransmitFull, and XUartPs_WriteReg.

s32 XUartPs_SetBaudRate	(	XUartPs *	InstancePtr,
		u32	BaudRate
	)

Sets the baud rate for the device.

Checks the input value for validity and also verifies that the requested rate can be configured to within the maximum error range specified by XUARTPS_MAX_BAUD_ERROR_RATE. If the provided rate is not possible, the current setting is unchanged.

Parameters

InstancePtr	is a pointer to the XUartPs instance
BaudRate	to be set

Returns

XST_SUCCESS if everything configured as expected
XST_UART_BAUD_ERROR if the requested rate is not available because there was too much error

Note: None.

References XUartPs_Config::BaseAddress, XUartPs_Config::InputClockHz, XUARTPS_BAUDDIV_OFFSET, XUARTPS_BAUDGEN_OFFSET, XUARTPS_CR_OFFSET, XUARTPS_CR_RXRST, XUARTPS_CR_TXRST, XUartPs_DisableUart, XUartPs_EnableUart, XUARTPS_MR_CLKSEL, XUARTPS_MR_OFFSET, XUartPs_ReadReg, and XUartPs_WriteReg.

Referenced by UartPsHelloWorldExample(), XUartPs_CfgInitialize(), and XUartPs_SetDataFormat().

s32 XUartPs_SetDataFormat	(	XUartPs *	InstancePtr,
		XUartPsFormat *	FormatPtr
	)

Sets the data format for the device.

The data format includes the baud rate, number of data bits, number of stop bits, and parity. It is the caller's responsibility to ensure that the UART is not sending or receiving data when this function is called.

Parameters

InstancePtr	is a pointer to the XUartPs instance.
FormatPtr	is a pointer to a format structure containing the data format to be set.

Returns

XST_SUCCESS if the data format was successfully set.
XST_UART_BAUD_ERROR indicates the baud rate could not be set because of the amount of error with the baud rate and the input clock frequency.
XST_INVALID_PARAM if one of the parameters was not valid.

Note

The data types in the format type, data bits and parity, are 32 bit fields to prevent a compiler warning. The asserts in this function will cause a warning if these fields are bytes.

References XUartPs_Config::BaseAddress, XUartPsFormat::BaudRate, XUartPsFormat::DataBits, XUartPsFormat::Parity, XUartPsFormat::StopBits, XUARTPS_FORMAT_2_STOP_BIT, XUARTPS_FORMAT_6_BITS, XUARTPS_FORMAT_NO_PARITY, XUARTPS_MR_CHARLEN_MASK, XUARTPS_MR_CHARLEN_SHIFT, XUARTPS_MR_OFFSET, XUARTPS_MR_PARITY_MASK, XUARTPS_MR_PARITY_SHIFT, XUARTPS_MR_STOPMODE_MASK, XUARTPS_MR_STOPMODE_SHIFT, XUartPs_ReadReg, XUartPs_SetBaudRate(), and XUartPs_WriteReg.

void XUartPs_SetFifoThreshold	(	XUartPs *	InstancePtr,
		u8	TriggerLevel
	)

This functions sets the receive FIFO trigger level.

The receive trigger level specifies the number of bytes in the receive FIFO that cause a receive data event (interrupt) to be generated.

Parameters

InstancePtr	is a pointer to the XUartPs instance.
TriggerLevel	contains the trigger level to set.

Returns: None

Note: None.

References XUartPs_Config::BaseAddress, XUARTPS_RXWM_MASK, XUARTPS_RXWM_OFFSET, and XUartPs_WriteReg.

void XUartPs_SetFlowDelay	(	XUartPs *	InstancePtr,
		u8	FlowDelayValue
	)

This function sets the Flow Delay.

0 - 3: Flow delay inactive 4 - 63: If Flow Control mode is enabled, UART_rtsN is deactivated when the receive FIFO fills to this level.

Parameters

InstancePtr	is a pointer to the XUartPs instance.
FlowDelayValue	is the Setting for the flow delay.

Returns: None.

Note: None.

References XUartPs_Config::BaseAddress, XUARTPS_FLOWDEL_MASK, XUARTPS_FLOWDEL_OFFSET, and XUartPs_WriteReg.

void XUartPs_SetHandler	(	XUartPs *	InstancePtr,
		XUartPs_Handler	FuncPtr,
		void *	CallBackRef
	)

This function sets the handler that will be called when an event (interrupt) occurs that needs application's attention.

Parameters

InstancePtr	is a pointer to the XUartPs instance
FuncPtr	is the pointer to the callback function.
CallBackRef	is the upper layer callback reference passed back when the callback function is invoked.

Returns: None.

Note

There is no assert on the CallBackRef since the driver doesn't know what it is (nor should it)

Referenced by UartPsIntrExample().

void XUartPs_SetInterruptMask	(	XUartPs *	InstancePtr,
		u32	Mask
	)

This function sets the interrupt mask.

Parameters

InstancePtr	is a pointer to the XUartPs instance
Mask	contains the interrupts to be enabled or disabled. A '1' enables an interrupt, and a '0' disables.

Returns: None.

Note: None.

References XUartPs_Config::BaseAddress, XUARTPS_IDR_OFFSET, XUARTPS_IER_OFFSET, XUARTPS_IXR_MASK, and XUartPs_WriteReg.

Referenced by UartPsIntrExample().

void XUartPs_SetOperMode	(	XUartPs *	InstancePtr,
		u8	OperationMode
	)

This function sets the operational mode of the UART.

The UART can operate in one of four modes: Normal, Local Loopback, Remote Loopback, or automatic echo.

Parameters

InstancePtr	is a pointer to the XUartPs instance.
OperationMode	is the mode of the UART.

Returns: None.

Note: None.

References XUartPs_Config::BaseAddress, XUARTPS_MR_CHMODE_ECHO, XUARTPS_MR_CHMODE_L_LOOP, XUARTPS_MR_CHMODE_MASK, XUARTPS_MR_CHMODE_NORM, XUARTPS_MR_CHMODE_R_LOOP, XUARTPS_MR_OFFSET, XUARTPS_OPER_MODE_AUTO_ECHO, XUARTPS_OPER_MODE_LOCAL_LOOP, XUARTPS_OPER_MODE_NORMAL, XUARTPS_OPER_MODE_REMOTE_LOOP, XUartPs_ReadReg, and XUartPs_WriteReg.

Referenced by UartPsIntrExample(), and UartPsPolledExample().

void XUartPs_SetOptions	(	XUartPs *	InstancePtr,
		u16	Options
	)

Sets the options for the specified driver instance.

The options are implemented as bit masks such that multiple options may be enabled or disabled simultaneously.

The GetOptions function may be called to retrieve the currently enabled options. The result is ORed in the desired new settings to be enabled and ANDed with the inverse to clear the settings to be disabled. The resulting value is then used as the options for the SetOption function call.

Parameters

InstancePtr	is a pointer to the XUartPs instance.
Options	contains the options to be set which are bit masks contained in the file xuartps.h and named XUARTPS_OPTION_*.

Returns: None.

Note: None.

References XUartPs_Config::BaseAddress, XUARTPS_CR_STOPBRK, XUARTPS_OPTION_SET_BREAK, XUartPs_ReadReg, and XUartPs_WriteReg.

void XUartPs_SetRecvTimeout	(	XUartPs *	InstancePtr,
		u8	RecvTimeout
	)

This function sets the Receive Timeout of the UART.

Parameters

InstancePtr	is a pointer to the XUartPs instance.
RecvTimeout	setting allows the UART to detect an idle connection on the receiver data line. Timeout duration = RecvTimeout x 4 x Bit Period. 0 disables the timeout function.

Returns: None.

Note: None.

References XUartPs_Config::BaseAddress, XUARTPS_CR_OFFSET, XUARTPS_CR_TORST, XUartPs_ReadReg, XUARTPS_RXTOUT_MASK, XUARTPS_RXTOUT_OFFSET, and XUartPs_WriteReg.

Referenced by UartPsIntrExample().

Variable Documentation

XUartPs_Config XUartPs_ConfigTable[XPAR_XUARTPS_NUM_INSTANCES]

Each XUartPs device in the system has an entry in this table.

XUartPs_Config XUartPs_ConfigTable[XPAR_XUARTPS_NUM_INSTANCES]

Initial value:

= {
        {
                (u16)XPAR_XUARTPS_0_DEVICE_ID,
                (u32)XPAR_XUARTPS_0_BASEADDR,
                (u32)XPAR_XUARTPS_0_UART_CLK_FREQ_HZ,
                (s32)0
        },
}

Each XUartPs device in the system has an entry in this table.

Data Structures

Macros

Typedefs

Functions

Variables

Configuration options

Channel Operational Mode

Data format values

Callback events

Register Map

Control Register

Mode Register

Interrupt Registers

Baud Rate Generator Register

Baud Divisor Rate register

Receiver Timeout Register

Receiver FIFO Trigger Level Register

Transmit FIFO Trigger Level Register

Modem Control Register

Modem Status Register

Channel Status Register

Flow Delay Register

Receiver FIFO Byte Status Register

Macro Definition Documentation

Typedef Documentation

Function Documentation

Variable Documentation