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uartpsv
Vitis Drivers API Documentation
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uartpsv
Vitis Drivers API Documentation
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Data Structures | |
| struct | XUartPsv_Config |
| This typedef contains configuration information for the device. More... | |
| struct | XUartPsvBuffer |
| Keep track of state information about a data buffer in the interrupt mode. More... | |
| struct | XUartPsvFormat |
| Keep track of data format setting of a device. More... | |
| struct | XUartPsv |
| The XUartPsv driver instance data structure. More... | |
Macros | |
| #define | XUARTPSV_MAX_BAUD_ERROR_RATE 3U |
| max % error allowed More... | |
| #define | XUARTPSV_H |
| by using protection macros More... | |
| #define | XUARTPSV_MAX_RATE 921600U |
| Maximum baud rate. More... | |
| #define | XUARTPSV_MIN_RATE 110U |
| Minimum baud rate. More... | |
| #define | XUARTPSV_DFT_BAUDRATE 115200U |
| Default baud rate. More... | |
| #define | XUartPsv_GetChannelStatus(InstancePtr) |
| Get the UART Channel Status Register. More... | |
| #define | XUartPsv_GetModeControl(InstancePtr) |
| Get the UART Mode Control Register. More... | |
| #define | XUartPsv_SetModeControl(InstancePtr, RegisterValue) |
| Set the UART Mode Control Register. More... | |
| #define | XUartPsv_EnableUart(InstancePtr) |
| Enable the transmitter and receiver of the UART. More... | |
| #define | XUartPsv_DisableUart(InstancePtr) |
| Disable the transmitter and receiver of the UART. More... | |
| #define | XUartPsv_IsTransmitEmpty(InstancePtr) |
| Determine if the transmitter FIFO is empty. More... | |
| #define | XUARTPSV_HW_H |
| by using protection macros More... | |
| #define | XUartPsv_ReadReg(BaseAddress, RegOffset) Xil_In32((BaseAddress) + (u32)(RegOffset)) |
| Read a UART register. More... | |
| #define | XUartPsv_WriteReg(BaseAddress, RegOffset, RegisterValue) |
| Write a UART register. More... | |
| #define | XUartPsv_IsReceiveData(BaseAddress) |
| Determine if there is receive data in the receiver and/or FIFO. More... | |
| #define | XUartPsv_IsTransmitFull(BaseAddress) |
| Determine if a byte of data can be sent with the transmitter. More... | |
| #define | XUartPsv_IsTransmitbusy(BaseAddress) |
| Determine if a byte of data can be sent with the transmitter. More... | |
| #define | XUARTPSV_NUM_OPTIONS (sizeof(XUartPsv_OptionsTable) / sizeof(Mapping)) |
| No. More... | |
| #define | XUARTPSV_TOTAL_BYTES (u8)32 |
| No. More... | |
Typedefs | |
| typedef void(* | XUartPsv_Handler )(void *CallBackRef, u32 Event, u32 EventData) |
| This data type defines a handler that an application defines to communicate with interrupt system to retrieve state information about an application. More... | |
Functions | |
| s32 | XUartPsv_CfgInitialize (XUartPsv *InstancePtr, XUartPsv_Config *Config, UINTPTR EffectiveAddr) |
| Initializes a specific XUartPsv instance such that it is ready to be used. More... | |
| u32 | XUartPsv_Send (XUartPsv *InstancePtr, u8 *BufferPtr, u32 NumBytes) |
| This functions sends the specified buffer using the device in either polled or interrupt driven mode. More... | |
| u32 | XUartPsv_Send_NoWait (XUartPsv *InstancePtr, u8 *BufferPtr, u32 NumBytes) |
| u32 | XUartPsv_Recv (XUartPsv *InstancePtr, u8 *BufferPtr, u32 NumBytes) |
| This function attempts to receive a specified number of bytes of data from the device and store it into the specified buffer. More... | |
| u32 | XUartPsv_SendBuffer (XUartPsv *InstancePtr) |
| This function sends a buffer that has been previously specified by setting up the instance variables of the instance. More... | |
| u32 | XUartPsv_ReceiveBuffer (XUartPsv *InstancePtr) |
| This function receives a buffer that has been previously specified by setting up the instance variables of the instance. More... | |
| s32 | XUartPsv_SetBaudRate (XUartPsv *InstancePtr, u32 BaudRate) |
| Sets the baud rate for the device. More... | |
| void | XUartPsv_ProgramCtrlReg (XUartPsv *InstancePtr, u32 CtrlRegister) |
| This function reprograms the control register according to the following sequence mentioned in the TRM. More... | |
| void | XUartPsv_CleanupRx (XUartPsv *InstancePtr) |
| This function is a cleanup function to allow reseting Rx NextBytePtr, RemainingBytes and RequestedBytes. More... | |
| void | XUartPsv_CleanupTx (XUartPsv *InstancePtr) |
| This function is a cleanup function to allow reseting Tx NextBytePtr, RemainingBytes and RequestedBytes. More... | |
| XUartPsv_Config * | XUartPsv_LookupConfig (u16 DeviceId) |
| Looks up the device configuration based on the unique device ID. More... | |
| void | XUartPsv_SetOptions (XUartPsv *InstancePtr, u16 Options) |
| Sets the options for the specified driver instance. More... | |
| u16 | XUartPsv_GetOptions (XUartPsv *InstancePtr) |
| Gets the options for the specified driver instance. More... | |
| void | XUartPsv_SetFifoThreshold (XUartPsv *InstancePtr, u8 TriggerLevel) |
| This functions sets the Tx and Rx FIFO trigger level to the 'TriggerLevel' argument. More... | |
| void | XUartPsv_SetTxFifoThreshold (XUartPsv *InstancePtr, u8 TriggerLevel) |
| This functions sets the Tx FIFO trigger level to the 'TriggerLevel' argument. More... | |
| void | XUartPsv_SetRxFifoThreshold (XUartPsv *InstancePtr, u8 TriggerLevel) |
| This functions sets the Rx FIFO trigger level to the 'TriggerLevel' argument. More... | |
| u8 | XUartPsv_GetFifoThreshold (XUartPsv *InstancePtr) |
| This function gets the Tx and Rx FIFO trigger level. More... | |
| u16 | XUartPsv_GetModemStatus (XUartPsv *InstancePtr) |
| This function gets the modem status from the specified UART. More... | |
| u32 | XUartPsv_IsSending (XUartPsv *InstancePtr) |
| This function determines if the specified UART is sending data. More... | |
| u8 | XUartPsv_GetOperMode (XUartPsv *InstancePtr) |
| This function gets the operational mode of the UART. More... | |
| void | XUartPsv_SetOperMode (XUartPsv *InstancePtr, u8 OperationMode) |
| This function sets the operational mode of the UART. More... | |
| s32 | XUartPsv_SetDataFormat (XUartPsv *InstancePtr, XUartPsvFormat *FormatPtr) |
| Sets the data format for the device. More... | |
| void | XUartPsv_GetDataFormat (XUartPsv *InstancePtr, XUartPsvFormat *FormatPtr) |
| Gets the data format for the specified UART. More... | |
| u32 | XUartPsv_GetInterruptMask (XUartPsv *InstancePtr) |
| This function gets the interrupt mask. More... | |
| void | XUartPsv_SetInterruptMask (XUartPsv *InstancePtr, u32 Mask) |
| This function sets the interrupt mask. More... | |
| void | XUartPsv_InterruptHandler (XUartPsv *InstancePtr) |
| This function is the interrupt handler for the driver. More... | |
| void | XUartPsv_SetHandler (XUartPsv *InstancePtr, XUartPsv_Handler FuncPtr, void *CallBackRef) |
| This function sets the handler that will be called when an event (interrupt) occurs that needs application's attention. More... | |
| s32 | XUartPsv_SelfTest (XUartPsv *InstancePtr) |
| This function runs a self-test on the driver and hardware device. More... | |
| void | XUartPsv_SendByte (UINTPTR BaseAddress, u8 Data) |
| This function sends one byte using the device. More... | |
| u8 | XUartPsv_RecvByte (UINTPTR BaseAddress) |
| This function receives a byte from the device. More... | |
| void | XUartPsv_ResetHw (UINTPTR BaseAddress) |
| This function resets UART. More... | |
Variables | |
| XUartPsv_Config | XUartPsv_ConfigTable [] |
| Config structure. More... | |
Configuration options | |
| #define | XUARTPSV_OPTION_SET_BREAK 0x0080U |
| These constants specify the options that may be set or retrieved with the driver, each is a unique bit mask such that multiple options may be specified. More... | |
| #define | XUARTPSV_OPTION_STOP_BREAK 0x0040U |
| Stops break transmission. More... | |
| #define | XUARTPSV_OPTION_RESET_TMOUT 0x0020U |
| Reset the receive timeout. More... | |
| #define | XUARTPSV_OPTION_RESET_TX 0x0010U |
| Reset the transmitter. More... | |
| #define | XUARTPSV_OPTION_RESET_RX 0x0008U |
| Reset the receiver. More... | |
| #define | XUARTPSV_OPTION_ASSERT_RTS 0x0004U |
| Assert the RTS bit. More... | |
| #define | XUARTPSV_OPTION_ASSERT_DTR 0x0002U |
| Assert the DTR bit. More... | |
| #define | XUARTPSV_OPTION_SET_FCM 0x0001U |
| Turn on flow control mode. More... | |
Channel Operational Mode | |
The UART can operate in one of four modes: Normal, Local Loopback, Remote Loopback, or automatic echo. | |
| #define | XUARTPSV_OPER_MODE_NORMAL (u8)0x00U |
| Normal Mode. More... | |
| #define | XUARTPSV_OPER_MODE_LOCAL_LOOP (u8)0x02U |
| Local Loop back Mode. More... | |
Data format values | |
These constants specify the data format that the driver supports. The data format includes the number of data bits, the number of stop bits and parity. | |
| #define | XUARTPSV_FORMAT_8_BITS 3U |
| 8 data bits More... | |
| #define | XUARTPSV_FORMAT_7_BITS 2U |
| 7 data bits More... | |
| #define | XUARTPSV_FORMAT_6_BITS 1U |
| 6 data bits More... | |
| #define | XUARTPSV_FORMAT_5_BITS 0U |
| 5 data bits More... | |
| #define | XUARTPSV_FORMAT_NO_PARITY 0U |
| No parity. More... | |
| #define | XUARTPSV_FORMAT_EN_PARITY 1U |
| Enable parity. More... | |
| #define | XUARTPSV_FORMAT_EVEN_PARITY 2U |
| Even parity. More... | |
| #define | XUARTPSV_FORMAT_ODD_PARITY 0U |
| Odd parity. More... | |
| #define | XUARTPSV_FORMAT_EN_STICK_PARITY 4U |
| Stick parity. More... | |
| #define | XUARTPSV_FORMAT_NO_STICK_PARITY 0U |
| Stick parity. More... | |
| #define | XUARTPSV_FORMAT_PARITY_MASK 7U |
| Format parity mask. More... | |
| #define | XUARTPSV_FORMAT_EVEN_PARITY_SHIFT 1U |
| Even parity shift. More... | |
| #define | XUARTPSV_FORMAT_EN_STICK_PARITY_SHIFT 5U |
| Stick parity shift. More... | |
| #define | XUARTPSV_FORMAT_2_STOP_BIT 1U |
| 2 stop bits More... | |
| #define | XUARTPSV_FORMAT_1_STOP_BIT 0U |
| 1 stop bit More... | |
Callback events | |
These constants specify the handler events that an application can handle using its specific handler function. Note that these constants are not bit mask, so only one event can be passed to an application at a time. | |
| #define | XUARTPSV_EVENT_RECV_DATA 1U |
| Data receiving done. More... | |
| #define | XUARTPSV_EVENT_RECV_TOUT 2U |
| A receive timeout occurred. More... | |
| #define | XUARTPSV_EVENT_SENT_DATA 3U |
| Data transmission done. More... | |
| #define | XUARTPSV_EVENT_RECV_ERROR 4U |
| A receive error detected. More... | |
| #define | XUARTPSV_EVENT_MODEM 5U |
| Modem status changed. More... | |
| #define | XUARTPSV_EVENT_PARE_FRAME_BRKE 6U |
| A receive parity, frame,break error detected. More... | |
| #define | XUARTPSV_EVENT_RECV_ORERR 7U |
| A receive overrun error detected. More... | |
Register Map | |
| #define | XUARTPSV_UARTDR_OFFSET 0x0000U |
| Data. More... | |
| #define | XUARTPSV_UARTRSR_OFFSET 0x0004U |
| Receive Status Register/Error Clear. More... | |
| #define | XUARTPSV_UARTFR_OFFSET 0x0018U |
| Flag Register. More... | |
| #define | XUARTPSV_UARTILPR_OFFSET 0x0020U |
| IrDA Low-Power Counter. More... | |
| #define | XUARTPSV_UARTIBRD_OFFSET 0x0024U |
| Integer Baud Rate. More... | |
| #define | XUARTPSV_UARTFBRD_OFFSET 0x0028U |
| Fractional Baud Rate. More... | |
| #define | XUARTPSV_UARTLCR_OFFSET 0x002CU |
| Line Control. More... | |
| #define | XUARTPSV_UARTCR_OFFSET 0x0030U |
| Control. More... | |
| #define | XUARTPSV_UARTIFLS_OFFSET 0x0034U |
| Interrupt FIFO Level Select. More... | |
| #define | XUARTPSV_UARTIMSC_OFFSET 0x0038U |
| Interrupt Mask Set/Clear. More... | |
| #define | XUARTPSV_UARTRIS_OFFSET 0x003CU |
| Raw interrupt Status. More... | |
| #define | XUARTPSV_UARTMIS_OFFSET 0x0040U |
| Mask interrupt Status. More... | |
| #define | XUARTPSV_UARTICR_OFFSET 0x0044U |
| Interrupt Clear. More... | |
| #define | XUARTPSV_UARTDMACR_OFFSET 0x0048U |
| DMA Control. More... | |
Receive status register/error clear register | |
The Receive status register/error clear register (UARTRSR) gives the status of break, frame, parity and overrun. Receive status register/error clear register Bit Definition | |
| #define | XUARTPSV_UARTRSR_OE 0x00000008U |
| Overrun error. More... | |
Flag Register | |
|
Flag Register Bit Definition | |
| #define | XUARTPSV_UARTFR_RI 0x00000100U |
| Ring indicator. More... | |
| #define | XUARTPSV_UARTFR_TXFE 0x00000080U |
| Transmit FIFO empty. More... | |
| #define | XUARTPSV_UARTFR_RXFF 0x00000040U |
| Receive FIFO full. More... | |
| #define | XUARTPSV_UARTFR_TXFF 0x00000020U |
| Transmit FIFO full. More... | |
| #define | XUARTPSV_UARTFR_RXFE 0x00000010U |
| Receive FIFO empty. More... | |
| #define | XUARTPSV_UARTFR_BUSY 0x00000008U |
| UART Busy. More... | |
| #define | XUARTPSV_UARTFR_DCD 0x00000004U |
| Data carrier detect. More... | |
| #define | XUARTPSV_UARTFR_DSR 0x00000002U |
| Data set ready. More... | |
| #define | XUARTPSV_UARTFR_CTS 0x00000001U |
| Clear to send. More... | |
Line Control Register | |
The Line Control register (UARTLCR) controls the functions of the device. Line Control Register Bit Definition | |
| #define | XUARTPSV_UARTLCR_SPS 0x00000080U |
| Stick parity select. More... | |
| #define | XUARTPSV_UARTLCR_FEN 0x00000010U |
| Enable FIFOs. More... | |
| #define | XUARTPSV_UARTLCR_STP2 0x00000008U |
| Two stop bits selected. More... | |
| #define | XUARTPSV_UARTLCR_EPS 0x00000004U |
| Even parity select. More... | |
| #define | XUARTPSV_UARTLCR_PEN 0x00000002U |
| Parity enable. More... | |
| #define | XUARTPSV_UARTLCR_BRK 0x00000001U |
| Send break. More... | |
| #define | XUARTPSV_UARTLCR_WLEN_MASK 0x00000060U |
| Word length mask. More... | |
| #define | XUARTPSV_UARTLCR_WLEN_SHIFT 0x00000005U |
| Word length shift. More... | |
| #define | XUARTPSV_UARTLCR_WLEN_5_BIT 0x00000000U |
| 5 bits data More... | |
| #define | XUARTPSV_UARTLCR_WLEN_6_BIT 0x00000020U |
| 6 bits data More... | |
| #define | XUARTPSV_UARTLCR_WLEN_7_BIT 0x00000040U |
| 7 bits data More... | |
| #define | XUARTPSV_UARTLCR_WLEN_8_BIT 0x00000060U |
| 8 bits data More... | |
| #define | XUARTPSV_UARTLCR_STP_1_BIT 0x00000000U |
| One stop bits selected. More... | |
| #define | XUARTPSV_UARTLCR_STP_MASK 0x00000008U |
| Stop bits mask. More... | |
| #define | XUARTPSV_UARTLCR_STP_SHIFT 0x00000003U |
| Stop bits shift. More... | |
| #define | XUARTPSV_UARTLCR_PARITY_EVEN 0x00000004U |
| Even parity mode. More... | |
| #define | XUARTPSV_UARTLCR_PARITY_MASK 0x00000002U |
| Parity mask. More... | |
| #define | XUARTPSV_UARTLCR_PARITY_SHIFT 0x00000001U |
| Parity shift. More... | |
| #define | XUARTPSV_UARTLCR_PARITY_NONE 0x00000000U |
| No parity mode. More... | |
| #define | XUARTPSV_UARTLCR_PARITY_ODD 0x00000000U |
| Odd parity mode. More... | |
Control Register | |
The Control register (UARTCR) controls the major functions of the device. Control Register Bit Definition | |
| #define | XUARTPSV_UARTCR_CTSEN 0x00008000U |
| CTS hardware flow control enable. More... | |
| #define | XUARTPSV_UARTCR_RTSEN 0x00004000U |
| RTS hardware flow control enable. More... | |
| #define | XUARTPSV_UARTCR_OUT2 0x00002000U |
| UART Out2 modem status output. More... | |
| #define | XUARTPSV_UARTCR_OUT1 0x00001000U |
| UART Out1 modem status output. More... | |
| #define | XUARTPSV_UARTCR_RTS 0x00000800U |
| Request to send. More... | |
| #define | XUARTPSV_UARTCR_DTR 0x00000400U |
| Data transmit ready. More... | |
| #define | XUARTPSV_UARTCR_RXE 0x00000200U |
| Receive enable. More... | |
| #define | XUARTPSV_UARTCR_TXE 0x00000100U |
| Transmit enable. More... | |
| #define | XUARTPSV_UARTCR_LBE 0x00000080U |
| Loop back enable. More... | |
| #define | XUARTPSV_UARTCR_SIRLP 0x00000004U |
| SIR low-power IrDA mode. More... | |
| #define | XUARTPSV_UARTCR_SIREN 0x00000002U |
| SIR enable. More... | |
| #define | XUARTPSV_UARTCR_UARTEN 0x00000001U |
| UART enable. More... | |
| #define | XUARTPSV_UARTCR_MODE_MASK 0x00000080U |
| Mode mask. More... | |
| #define | XUARTPSV_UARTCR_MODE_SHIFT 0x00000007U |
| Mode shift. More... | |
| #define | XUARTPSV_UARTCR_MODE_NORMAL 0x00000000U |
| Normal Mode. More... | |
Interrupt FIFO Level Select Register | |
The UARTIFLS Register is the interrupt FIFO level select register. You can use this register to define the FIFO level that triggers the assertion of UARTTXINTR and UARTRXINTR. Interrupt FIFO Level Select Register Register Bit Definition | |
| #define | XUARTPSV_UARTIFLS_RXIFLSEL_MASK 0x00000038U |
| Receive interrupt FIFO level select mask. More... | |
| #define | XUARTPSV_UARTIFLS_RXIFLSEL_SHIFT 0x00000003U |
| Transmit interrupt FIFO level select shift. More... | |
| #define | XUARTPSV_UARTIFLS_TXIFLSEL_MASK 0x00000007U |
| Receive interrupt FIFO level select mask. More... | |
| #define | XUARTPSV_UARTIFLS_TXIFLSEL_SHIFT 0x00000000U |
| Transmit interrupt FIFO level select shift. More... | |
| #define | XUARTPSV_UARTIFLS_RXIFLSEL_1_8 0x00000000U |
| Receive FIFO becomes . More... | |
| #define | XUARTPSV_UARTIFLS_RXIFLSEL_1_4 0x00000008U |
| Receive FIFO becomes . More... | |
| #define | XUARTPSV_UARTIFLS_RXIFLSEL_1_2 0x00000010U |
| Receive FIFO becomes * . More... | |
| #define | XUARTPSV_UARTIFLS_RXIFLSEL_3_4 0x00000018U |
| Receive FIFO becomes * . More... | |
| #define | XUARTPSV_UARTIFLS_RXIFLSEL_7_8 0x00000020U |
| Receive FIFO becomes * . More... | |
| #define | XUARTPSV_UARTIFLS_TXIFLSEL_1_8 0x00000000U |
| Transmit FIFO becomes * . More... | |
| #define | XUARTPSV_UARTIFLS_TXIFLSEL_1_4 0x00000001U |
| Transmit FIFO becomes * . More... | |
| #define | XUARTPSV_UARTIFLS_TXIFLSEL_1_2 0x00000002U |
| Transmit FIFO becomes * . More... | |
| #define | XUARTPSV_UARTIFLS_TXIFLSEL_3_4 0x00000003U |
| Transmit FIFO becomes * . More... | |
| #define | XUARTPSV_UARTIFLS_TXIFLSEL_7_8 0x00000004U |
| Transmit FIFO becomes * . More... | |
Interrupt Mask Set/Clear Register | |
The UARTIMSC Register is the interrupt mask set/clear register. It is a read/write register. On a read this register returns the current value of the mask on the relevant interrupt. On a write of 1 to the particular bit, it sets the corresponding mask of that interrupt. A write of 0 clears the corresponding mask. Interrupt Mask Set/Clear Register Bit Definition | |
| #define | XUARTPSV_UARTIMSC_OEIM 0x00000400U |
| Overrun Error Interrupt. More... | |
| #define | XUARTPSV_UARTIMSC_BEIM 0x00000200U |
| Break Error Interrupt. More... | |
| #define | XUARTPSV_UARTIMSC_PEIM 0x00000100U |
| Parity Error Interrupt. More... | |
| #define | XUARTPSV_UARTIMSC_FEIM 0x00000080U |
| Framing Error Interrupt. More... | |
| #define | XUARTPSV_UARTIMSC_RTIM 0x00000040U |
| Receive Timeout Interrupt. More... | |
| #define | XUARTPSV_UARTIMSC_TXIM 0x00000020U |
| Transmit Interrupt. More... | |
| #define | XUARTPSV_UARTIMSC_RXIM 0x00000010U |
| Receive Interrupt. More... | |
| #define | XUARTPSV_UARTIMSC_DSRMIM 0x00000008U |
| nUARTDSR modem interrupt More... | |
| #define | XUARTPSV_UARTIMSC_DCDMIM 0x00000004U |
| nUARTDCD modem interrupt More... | |
| #define | XUARTPSV_UARTIMSC_CTSMIM 0x00000002U |
| nUARTCTS modem interrupt More... | |
| #define | XUARTPSV_UARTIMSC_RIMIM 0x00000001U |
| nUARTRI modem interrupt More... | |
| #define | XUARTPSV_UARTIMSC_MASK 0x000007FFU |
| Valid bit mask. More... | |
Raw Interrupt Status Register | |
The raw interrupt status register (UARTRIS) is a read-only register. This register returns the current raw status value, prior to masking, of the corresponding interrupt. A write has no effect. Raw Interrupt Status Register Bit Definition | |
| #define | XUARTPSV_UARTRIS_OERIS 0x00000400U |
| Overrun Error Interrupt. More... | |
| #define | XUARTPSV_UARTRIS_BERIS 0x00000200U |
| Break Error Interrupt. More... | |
| #define | XUARTPSV_UARTRIS_PERIS 0x00000100U |
| Parity Error Interrupt. More... | |
| #define | XUARTPSV_UARTRIS_FERIS 0x00000080U |
| Framing Error Interrupt. More... | |
| #define | XUARTPSV_UARTRIS_RTRIS 0x00000040U |
| Receive Timeout Interrupt. More... | |
| #define | XUARTPSV_UARTRIS_TXRIS 0x00000020U |
| Transmit Interrupt. More... | |
| #define | XUARTPSV_UARTRIS_RXRIS 0x00000010U |
| Receive Interrupt. More... | |
| #define | XUARTPSV_UARTRIS_DSRRMIS 0x00000008U |
| nUARTDSR modem interrupt More... | |
| #define | XUARTPSV_UARTRIS_DCDRMIS 0x00000004U |
| nUARTDCD modem interrupt More... | |
| #define | XUARTPSV_UARTRIS_CTSRMIS 0x00000002U |
| nUARTCTS modem interrupt More... | |
| #define | XUARTPSV_UARTRIS_RIRMIS 0x00000001U |
| nUARTRI modem interrupt More... | |
Masked Interrupt Status Register | |
The UARTMIS Register is the masked interrupt status register. It is a read-only register. This register returns the current masked status value of the corresponding interrupt. A write has no effect. Masked Interrupt Status Register Bit Definition | |
| #define | XUARTPSV_UARTMIS_OEMIS 0x00000400U |
| Overrun Error Interrupt. More... | |
| #define | XUARTPSV_UARTMIS_BEMIS 0x00000200U |
| Break Error Interrupt. More... | |
| #define | XUARTPSV_UARTMIS_PEMIS 0x00000100U |
| Parity Error Interrupt. More... | |
| #define | XUARTPSV_UARTMIS_FEMIS 0x00000080U |
| Framing Error Interrupt. More... | |
| #define | XUARTPSV_UARTMIS_RTMIS 0x00000040U |
| Receive Timeout Interrupt. More... | |
| #define | XUARTPSV_UARTMIS_TXMIS 0x00000020U |
| Transmit Interrupt. More... | |
| #define | XUARTPSV_UARTMIS_RXMIS 0x00000010U |
| Receive Interrupt. More... | |
| #define | XUARTPSV_UARTMIS_DSRMMIS 0x00000008U |
| nUARTDSR modem interrupt More... | |
| #define | XUARTPSV_UARTMIS_DCDMMIS 0x00000004U |
| nUARTDCD modem interrupt More... | |
| #define | XUARTPSV_UARTMIS_CTSMMIS 0x00000002U |
| nUARTCTS modem interrupt More... | |
| #define | XUARTPSV_UARTMIS_RIRMMIS 0x00000001U |
| nUARTRI modem interrupt More... | |
Interrupt Clear Register | |
The UARTICR Register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect. Interrupt Clear Register Bit Definition | |
| #define | XUARTPSV_UARTICR_OEIC 0x00000400U |
| Overrun Error Interrupt. More... | |
| #define | XUARTPSV_UARTICR_BEIC 0x00000200U |
| Break Error Interrupt. More... | |
| #define | XUARTPSV_UARTICR_PEIC 0x00000100U |
| Parity Error Interrupt. More... | |
| #define | XUARTPSV_UARTICR_FEIC 0x00000080U |
| Framing Error Interrupt. More... | |
| #define | XUARTPSV_UARTICR_RTIC 0x00000040U |
| Receive Timeout Interrupt. More... | |
| #define | XUARTPSV_UARTICR_TXIC 0x00000020U |
| Transmit Interrupt. More... | |
| #define | XUARTPSV_UARTICR_RXIC 0x00000010U |
| Receive Interrupt. More... | |
| #define | XUARTPSV_UARTICR_DSRMIC 0x00000008U |
| nUARTDSR modem interrupt More... | |
| #define | XUARTPSV_UARTICR_DCDMIC 0x00000004U |
| nUARTDCD modem interrupt More... | |
| #define | XUARTPSV_UARTICR_CTSMIC 0x00000002U |
| nUARTCTS modem interrupt More... | |
| #define | XUARTPSV_UARTICR_RIMIC 0x00000001U |
| nUARTRI modem interrupt More... | |
DMA Control Register | |
The UARTDMACR Register is the DMA control register. It is a read/write register. All the bits are cleared to 0 on reset. DMA Control Register Bit Definition | |
| #define | XUARTPSV_UARTDMACR_DMAONERR 0x00000004U |
| DMA on error. More... | |
| #define | XUARTPSV_UARTDMACR_TXDMAE 0x00000002U |
| Transmit DMA enable. More... | |
| #define | XUARTPSV_UARTDMACR_RXDMAE 0x00000001U |
| Receive DMA enable. More... | |
Integer Baud Rate Register | |
The UARTIBRD Register is the integer part of the baud rate divisor value | |
| #define | XUARTPSV_UARTIBRD_BAUD_DIVINT_MASK 0x0000FFFFU |
| 16 UARTIBRD bit mask More... | |
| #define | XUARTPSV_UARTIBRD_BAUD_DIVINT_RESET_VAL 0x00000000U |
| Reset value. More... | |
Fractional Baud Rate Register | |
The UARTFBRD Register is the fractional part of the baud rate divisor value Baud rate divisor BAUDDIV = (FUARTCLK/(16xBaud rate)) where FUARTCLK is the UART reference clock frequency The BAUDDIV is comprised of the integer value (BAUD DIVINT) and the fractional value (BAUD DIVFRAC) | |
| #define | XUARTPSV_UARTFBRD_BAUD_DIVFRAC_MASK 0x0000003FU |
| 6 UARTFBRD bit mask More... | |
| #define | XUARTPSV_UARTFBRD_BAUD_DIVFRAC_RESET_VAL 0x00000000U |
| Reset value. More... | |
Receiver Timeout Register | |
Use the receiver timeout register (RTR) to detect an idle condition on the receiver data line. | |
| #define | XUARTPSV_RXTOUT_DISABLE 0x00000000U |
| Disable time out. More... | |
| #define | XUARTPSV_RXTOUT_MASK 0x000000FFU |
| Valid bits mask. More... | |
Receiver FIFO Trigger Level Register | |
Use the Receiver FIFO Trigger Level Register (RTRIG) to set the value at which the RX FIFO triggers an interrupt event. | |
| #define | XUARTPSV_RXWM_DISABLE 0x00000000U |
| Disable RX trigger interrupt. More... | |
| #define | XUARTPSV_RXWM_MASK 0x0000003FU |
| Valid bits mask. More... | |
| #define | XUARTPSV_RXWM_RESET_VAL 0x00000020U |
| Reset value. More... | |
Transmit FIFO Trigger Level Register | |
Use the Transmit FIFO Trigger Level Register (TTRIG) to set the value at which the TX FIFO triggers an interrupt event. | |
| #define | XUARTPSV_TXWM_MASK 0x0000003FU |
| Valid bits mask. More... | |
| #define | XUARTPSV_TXWM_RESET_VAL 0x00000020U |
| Reset value. More... | |
Modem Control Register | |
This register (MODEMCR) controls the interface with the modem or data set, or a peripheral device emulating a modem. | |
| #define | XUARTPSV_MODEMCR_FCM 0x00000010U |
| Flow control mode. More... | |
| #define | XUARTPSV_MODEMCR_RTS 0x00000002U |
| Request to send. More... | |
| #define | XUARTPSV_MODEMCR_DTR 0x00000001U |
| Data terminal ready. More... | |
Modem Status Register | |
This register (MODEMSR) indicates the current state of the control lines from a modem, or another peripheral device, to the CPU. In addition, four bits of the modem status register provide change information. These bits are set to a logic 1 whenever a control input from the modem changes state. Note: Whenever the DCTS, DDSR, TERI, or DDCD bit is set to logic 1, a modem status interrupt is generated and this is reflected in the modem status register. | |
| #define | XUARTPSV_MODEMSR_FCMS 0x00000100U |
| Flow control mode (FCMS) More... | |
| #define | XUARTPSV_MODEMSR_DCD 0x00000080U |
| Complement of DCD input. More... | |
| #define | XUARTPSV_MODEMSR_RI 0x00000040U |
| Complement of RI input. More... | |
| #define | XUARTPSV_MODEMSR_DSR 0x00000020U |
| Complement of DSR input. More... | |
| #define | XUARTPSV_MODEMSR_CTS 0x00000010U |
| Complement of CTS input. More... | |
| #define | XUARTPSV_MODEMSR_DDCD 0x00000008U |
| Delta DCD indicator. More... | |
| #define | XUARTPSV_MODEMSR_TERI 0x00000004U |
| Trailing Edge Ring Indicator. More... | |
| #define | XUARTPSV_MODEMSR_DDSR 0x00000002U |
| Change of DSR. More... | |
| #define | XUARTPSV_MODEMSR_DCTS 0x00000001U |
| Change of CTS. More... | |
Flow Delay Register | |
Operation of the flow delay register (FLOWDEL) is very similar to the receive FIFO trigger register. An internal trigger signal activates when the FIFO is filled to the level set by this register. This trigger will not cause an interrupt, although it can be read through the channel status register. In hardware flow control mode, RTS is deactivated when the trigger becomes active. RTS only resets when the FIFO level is four less than the level of the flow delay trigger and the flow delay trigger is not activated. A value less than 4 disables the flow delay. | |
| #define | XUARTPSV_FLOWDEL_MASK XUARTPSV_RXWM_MASK |
| Valid bit mask. More... | |
Receiver FIFO Byte Status Register | |
The Receiver FIFO Status register is used to have a continuous monitoring of the raw unmasked byte status information. The register contains frame, parity and break status information for the top four bytes in the RX FIFO. Receiver FIFO Byte Status Register Bit Definition | |
| #define | XUARTPSV_RXBS_BYTE3_BRKE 0x00000800U |
| Byte3 Break Error. More... | |
| #define | XUARTPSV_RXBS_BYTE3_FRME 0x00000400U |
| Byte3 Frame Error. More... | |
| #define | XUARTPSV_RXBS_BYTE3_PARE 0x00000200U |
| Byte3 Parity Error. More... | |
| #define | XUARTPSV_RXBS_BYTE2_BRKE 0x00000100U |
| Byte2 Break Error. More... | |
| #define | XUARTPSV_RXBS_BYTE2_FRME 0x00000080U |
| Byte2 Frame Error. More... | |
| #define | XUARTPSV_RXBS_BYTE2_PARE 0x00000040U |
| Byte2 Parity Error. More... | |
| #define | XUARTPSV_RXBS_BYTE1_BRKE 0x00000020U |
| Byte1 Break Error. More... | |
| #define | XUARTPSV_RXBS_BYTE1_FRME 0x00000010U |
| Byte1 Frame Error. More... | |
| #define | XUARTPSV_RXBS_BYTE1_PARE 0x00000008U |
| Byte1 Parity Error. More... | |
| #define | XUARTPSV_RXBS_BYTE0_BRKE 0x00000004U |
| Byte0 Break Error. More... | |
| #define | XUARTPSV_RXBS_BYTE0_FRME 0x00000002U |
| Byte0 Frame Error. More... | |
| #define | XUARTPSV_RXBS_BYTE0_PARE 0x00000001U |
| Byte0 Parity Error. More... | |
| #define | XUARTPSV_RXBS_MASK 0x0000000FU |
| 3 bit RX byte status mask More... | |
| #define XUARTPSV_DFT_BAUDRATE 115200U |
Default baud rate.
Referenced by XUartPsv_CfgInitialize().
| #define XUartPsv_DisableUart | ( | InstancePtr | ) |
Disable the transmitter and receiver of the UART.
| InstancePtr | is a pointer to the XUartPsv instance. |
Referenced by XUartPsv_SetBaudRate().
| #define XUartPsv_EnableUart | ( | InstancePtr | ) |
Enable the transmitter and receiver of the UART.
| InstancePtr | is a pointer to the XUartPsv instance. |
Referenced by XUartPsv_SetBaudRate().
| #define XUARTPSV_EVENT_MODEM 5U |
Modem status changed.
| #define XUARTPSV_EVENT_PARE_FRAME_BRKE 6U |
A receive parity, frame,break error detected.
Referenced by Handler(), and XUartPsv_InterruptHandler().
| #define XUARTPSV_EVENT_RECV_DATA 1U |
Data receiving done.
Referenced by Handler().
| #define XUARTPSV_EVENT_RECV_ERROR 4U |
A receive error detected.
Referenced by Handler().
| #define XUARTPSV_EVENT_RECV_ORERR 7U |
A receive overrun error detected.
Referenced by Handler().
| #define XUARTPSV_EVENT_RECV_TOUT 2U |
A receive timeout occurred.
Referenced by Handler().
| #define XUARTPSV_EVENT_SENT_DATA 3U |
Data transmission done.
Referenced by Handler().
| #define XUARTPSV_FLOWDEL_MASK XUARTPSV_RXWM_MASK |
Valid bit mask.
| #define XUARTPSV_FORMAT_1_STOP_BIT 0U |
1 stop bit
| #define XUARTPSV_FORMAT_2_STOP_BIT 1U |
2 stop bits
Referenced by XUartPsv_SetDataFormat().
| #define XUARTPSV_FORMAT_5_BITS 0U |
5 data bits
| #define XUARTPSV_FORMAT_6_BITS 1U |
6 data bits
| #define XUARTPSV_FORMAT_7_BITS 2U |
7 data bits
| #define XUARTPSV_FORMAT_8_BITS 3U |
8 data bits
Referenced by XUartPsv_SetDataFormat().
| #define XUARTPSV_FORMAT_EN_PARITY 1U |
Enable parity.
Referenced by XUartPsv_SetDataFormat().
| #define XUARTPSV_FORMAT_EN_STICK_PARITY 4U |
Stick parity.
Referenced by XUartPsv_SetDataFormat().
| #define XUARTPSV_FORMAT_EN_STICK_PARITY_SHIFT 5U |
Stick parity shift.
Referenced by XUartPsv_SetDataFormat().
| #define XUARTPSV_FORMAT_EVEN_PARITY 2U |
Even parity.
Referenced by XUartPsv_SetDataFormat().
| #define XUARTPSV_FORMAT_EVEN_PARITY_SHIFT 1U |
Even parity shift.
Referenced by XUartPsv_SetDataFormat().
| #define XUARTPSV_FORMAT_NO_PARITY 0U |
No parity.
| #define XUARTPSV_FORMAT_NO_STICK_PARITY 0U |
Stick parity.
| #define XUARTPSV_FORMAT_ODD_PARITY 0U |
Odd parity.
| #define XUARTPSV_FORMAT_PARITY_MASK 7U |
Format parity mask.
Referenced by XUartPsv_SetDataFormat().
| #define XUartPsv_GetChannelStatus | ( | InstancePtr | ) |
Get the UART Channel Status Register.
| InstancePtr | is a pointer to the XUartPsv instance. |
| #define XUartPsv_GetModeControl | ( | InstancePtr | ) |
Get the UART Mode Control Register.
| InstancePtr | is a pointer to the XUartPsv instance. |
| #define XUARTPSV_H |
by using protection macros
| #define XUARTPSV_HW_H |
by using protection macros
| #define XUartPsv_IsReceiveData | ( | BaseAddress | ) |
Determine if there is receive data in the receiver and/or FIFO.
| BaseAddress | contains the base address of the device. |
Referenced by XUartPsv_RecvByte().
| #define XUartPsv_IsTransmitbusy | ( | BaseAddress | ) |
Determine if a byte of data can be sent with the transmitter.
| BaseAddress | contains the base address of the device. |
Referenced by UartPsvPolledExample(), XUartPsv_ProgramCtrlReg(), and XUartPsv_Send_NoWait().
| #define XUartPsv_IsTransmitEmpty | ( | InstancePtr | ) |
Determine if the transmitter FIFO is empty.
| InstancePtr | is a pointer to the XUartPsv instance. |
| #define XUartPsv_IsTransmitFull | ( | BaseAddress | ) |
Determine if a byte of data can be sent with the transmitter.
| BaseAddress | contains the base address of the device. |
Referenced by XUartPsv_SendBuffer(), and XUartPsv_SendByte().
| #define XUARTPSV_MAX_BAUD_ERROR_RATE 3U |
max % error allowed
Referenced by XUartPsv_SetBaudRate().
| #define XUARTPSV_MAX_RATE 921600U |
Maximum baud rate.
Referenced by XUartPsv_SetBaudRate().
| #define XUARTPSV_MIN_RATE 110U |
Minimum baud rate.
Referenced by XUartPsv_SetBaudRate().
| #define XUARTPSV_MODEMCR_DTR 0x00000001U |
Data terminal ready.
| #define XUARTPSV_MODEMCR_FCM 0x00000010U |
Flow control mode.
| #define XUARTPSV_MODEMCR_RTS 0x00000002U |
Request to send.
| #define XUARTPSV_MODEMSR_CTS 0x00000010U |
Complement of CTS input.
| #define XUARTPSV_MODEMSR_DCD 0x00000080U |
Complement of DCD input.
| #define XUARTPSV_MODEMSR_DCTS 0x00000001U |
Change of CTS.
| #define XUARTPSV_MODEMSR_DDCD 0x00000008U |
Delta DCD indicator.
| #define XUARTPSV_MODEMSR_DDSR 0x00000002U |
Change of DSR.
| #define XUARTPSV_MODEMSR_DSR 0x00000020U |
Complement of DSR input.
| #define XUARTPSV_MODEMSR_FCMS 0x00000100U |
Flow control mode (FCMS)
| #define XUARTPSV_MODEMSR_RI 0x00000040U |
Complement of RI input.
| #define XUARTPSV_MODEMSR_TERI 0x00000004U |
Trailing Edge Ring Indicator.
| #define XUARTPSV_NUM_OPTIONS (sizeof(XUartPsv_OptionsTable) / sizeof(Mapping)) |
| #define XUARTPSV_OPER_MODE_LOCAL_LOOP (u8)0x02U |
Local Loop back Mode.
Referenced by UartPsvIntrExample(), UartPsvPolledExample(), XUartPsv_GetOperMode(), XUartPsv_SelfTest(), and XUartPsv_SetOperMode().
| #define XUARTPSV_OPER_MODE_NORMAL (u8)0x00U |
Normal Mode.
Referenced by UartPsvIntrExample(), UartPsvPolledExample(), XUartPsv_GetOperMode(), and XUartPsv_SetOperMode().
| #define XUARTPSV_OPTION_ASSERT_DTR 0x0002U |
Assert the DTR bit.
| #define XUARTPSV_OPTION_ASSERT_RTS 0x0004U |
Assert the RTS bit.
| #define XUARTPSV_OPTION_RESET_RX 0x0008U |
Reset the receiver.
| #define XUARTPSV_OPTION_RESET_TMOUT 0x0020U |
Reset the receive timeout.
| #define XUARTPSV_OPTION_RESET_TX 0x0010U |
Reset the transmitter.
| #define XUARTPSV_OPTION_SET_BREAK 0x0080U |
These constants specify the options that may be set or retrieved with the driver, each is a unique bit mask such that multiple options may be specified.
These constants indicate the available options in active state.Starts break transmission
| #define XUARTPSV_OPTION_SET_FCM 0x0001U |
Turn on flow control mode.
| #define XUARTPSV_OPTION_STOP_BREAK 0x0040U |
Stops break transmission.
| #define XUartPsv_ReadReg | ( | BaseAddress, | |
| RegOffset | |||
| ) | Xil_In32((BaseAddress) + (u32)(RegOffset)) |
Read a UART register.
| BaseAddress | contains the base address of the device. |
| RegOffset | contains the offset from the base address of the device. |
Referenced by XUartPsv_CfgInitialize(), XUartPsv_GetDataFormat(), XUartPsv_GetFifoThreshold(), XUartPsv_GetInterruptMask(), XUartPsv_GetModemStatus(), XUartPsv_GetOperMode(), XUartPsv_GetOptions(), XUartPsv_InterruptHandler(), XUartPsv_IsSending(), XUartPsv_ProgramCtrlReg(), XUartPsv_ReceiveBuffer(), XUartPsv_RecvByte(), XUartPsv_SelfTest(), XUartPsv_SetBaudRate(), XUartPsv_SetDataFormat(), XUartPsv_SetFifoThreshold(), XUartPsv_SetOperMode(), XUartPsv_SetOptions(), XUartPsv_SetRxFifoThreshold(), and XUartPsv_SetTxFifoThreshold().
| #define XUARTPSV_RXBS_BYTE0_BRKE 0x00000004U |
Byte0 Break Error.
| #define XUARTPSV_RXBS_BYTE0_FRME 0x00000002U |
Byte0 Frame Error.
| #define XUARTPSV_RXBS_BYTE0_PARE 0x00000001U |
Byte0 Parity Error.
| #define XUARTPSV_RXBS_BYTE1_BRKE 0x00000020U |
Byte1 Break Error.
| #define XUARTPSV_RXBS_BYTE1_FRME 0x00000010U |
Byte1 Frame Error.
| #define XUARTPSV_RXBS_BYTE1_PARE 0x00000008U |
Byte1 Parity Error.
| #define XUARTPSV_RXBS_BYTE2_BRKE 0x00000100U |
Byte2 Break Error.
| #define XUARTPSV_RXBS_BYTE2_FRME 0x00000080U |
Byte2 Frame Error.
| #define XUARTPSV_RXBS_BYTE2_PARE 0x00000040U |
Byte2 Parity Error.
| #define XUARTPSV_RXBS_BYTE3_BRKE 0x00000800U |
Byte3 Break Error.
| #define XUARTPSV_RXBS_BYTE3_FRME 0x00000400U |
Byte3 Frame Error.
| #define XUARTPSV_RXBS_BYTE3_PARE 0x00000200U |
Byte3 Parity Error.
| #define XUARTPSV_RXBS_MASK 0x0000000FU |
3 bit RX byte status mask
| #define XUARTPSV_RXTOUT_DISABLE 0x00000000U |
Disable time out.
| #define XUARTPSV_RXTOUT_MASK 0x000000FFU |
Valid bits mask.
| #define XUARTPSV_RXWM_DISABLE 0x00000000U |
Disable RX trigger interrupt.
| #define XUARTPSV_RXWM_MASK 0x0000003FU |
Valid bits mask.
| #define XUARTPSV_RXWM_RESET_VAL 0x00000020U |
Reset value.
| #define XUartPsv_SetModeControl | ( | InstancePtr, | |
| RegisterValue | |||
| ) |
Set the UART Mode Control Register.
| InstancePtr | is a pointer to the XUartPsv instance. |
| RegisterValue | is the value to be written to the register. |
| #define XUARTPSV_TOTAL_BYTES (u8)32 |
| #define XUARTPSV_TXWM_MASK 0x0000003FU |
Valid bits mask.
| #define XUARTPSV_TXWM_RESET_VAL 0x00000020U |
Reset value.
| #define XUARTPSV_UARTCR_CTSEN 0x00008000U |
CTS hardware flow control enable.
| #define XUARTPSV_UARTCR_DTR 0x00000400U |
Data transmit ready.
| #define XUARTPSV_UARTCR_LBE 0x00000080U |
Loop back enable.
Referenced by XUartPsv_GetOperMode(), and XUartPsv_SetOperMode().
| #define XUARTPSV_UARTCR_MODE_MASK 0x00000080U |
Mode mask.
Referenced by XUartPsv_GetOperMode(), and XUartPsv_SetOperMode().
| #define XUARTPSV_UARTCR_MODE_NORMAL 0x00000000U |
Normal Mode.
Referenced by XUartPsv_GetOperMode(), and XUartPsv_SetOperMode().
| #define XUARTPSV_UARTCR_MODE_SHIFT 0x00000007U |
Mode shift.
Referenced by XUartPsv_GetOperMode().
| #define XUARTPSV_UARTCR_OFFSET 0x0030U |
Control.
Referenced by XUartPsv_GetOperMode(), XUartPsv_ProgramCtrlReg(), XUartPsv_SelfTest(), and XUartPsv_SetOperMode().
| #define XUARTPSV_UARTCR_OUT1 0x00001000U |
UART Out1 modem status output.
| #define XUARTPSV_UARTCR_OUT2 0x00002000U |
UART Out2 modem status output.
| #define XUARTPSV_UARTCR_RTS 0x00000800U |
Request to send.
| #define XUARTPSV_UARTCR_RTSEN 0x00004000U |
RTS hardware flow control enable.
| #define XUARTPSV_UARTCR_RXE 0x00000200U |
Receive enable.
| #define XUARTPSV_UARTCR_SIREN 0x00000002U |
SIR enable.
| #define XUARTPSV_UARTCR_SIRLP 0x00000004U |
SIR low-power IrDA mode.
| #define XUARTPSV_UARTCR_TXE 0x00000100U |
Transmit enable.
| #define XUARTPSV_UARTCR_UARTEN 0x00000001U |
UART enable.
Referenced by XUartPsv_ProgramCtrlReg().
| #define XUARTPSV_UARTDMACR_DMAONERR 0x00000004U |
DMA on error.
| #define XUARTPSV_UARTDMACR_OFFSET 0x0048U |
DMA Control.
| #define XUARTPSV_UARTDMACR_RXDMAE 0x00000001U |
Receive DMA enable.
| #define XUARTPSV_UARTDMACR_TXDMAE 0x00000002U |
Transmit DMA enable.
| #define XUARTPSV_UARTDR_OFFSET 0x0000U |
Data.
Referenced by XUartPsv_ReceiveBuffer(), XUartPsv_RecvByte(), XUartPsv_SendBuffer(), and XUartPsv_SendByte().
| #define XUARTPSV_UARTFBRD_BAUD_DIVFRAC_MASK 0x0000003FU |
6 UARTFBRD bit mask
| #define XUARTPSV_UARTFBRD_BAUD_DIVFRAC_RESET_VAL 0x00000000U |
Reset value.
| #define XUARTPSV_UARTFBRD_OFFSET 0x0028U |
Fractional Baud Rate.
Referenced by XUartPsv_SetBaudRate().
| #define XUARTPSV_UARTFR_BUSY 0x00000008U |
UART Busy.
Referenced by XUartPsv_IsSending(), and XUartPsv_SendBuffer().
| #define XUARTPSV_UARTFR_CTS 0x00000001U |
Clear to send.
| #define XUARTPSV_UARTFR_DCD 0x00000004U |
Data carrier detect.
| #define XUARTPSV_UARTFR_DSR 0x00000002U |
Data set ready.
| #define XUARTPSV_UARTFR_OFFSET 0x0018U |
Flag Register.
Referenced by XUartPsv_IsSending(), XUartPsv_ReceiveBuffer(), XUartPsv_SelfTest(), and XUartPsv_SendBuffer().
| #define XUARTPSV_UARTFR_RI 0x00000100U |
Ring indicator.
| #define XUARTPSV_UARTFR_RXFE 0x00000010U |
Receive FIFO empty.
Referenced by XUartPsv_ReceiveBuffer(), and XUartPsv_SelfTest().
| #define XUARTPSV_UARTFR_RXFF 0x00000040U |
Receive FIFO full.
| #define XUARTPSV_UARTFR_TXFE 0x00000080U |
Transmit FIFO empty.
Referenced by XUartPsv_IsSending().
| #define XUARTPSV_UARTFR_TXFF 0x00000020U |
Transmit FIFO full.
| #define XUARTPSV_UARTIBRD_BAUD_DIVINT_MASK 0x0000FFFFU |
16 UARTIBRD bit mask
| #define XUARTPSV_UARTIBRD_BAUD_DIVINT_RESET_VAL 0x00000000U |
Reset value.
| #define XUARTPSV_UARTIBRD_OFFSET 0x0024U |
Integer Baud Rate.
Referenced by XUartPsv_SetBaudRate().
| #define XUARTPSV_UARTICR_BEIC 0x00000200U |
Break Error Interrupt.
| #define XUARTPSV_UARTICR_CTSMIC 0x00000002U |
nUARTCTS modem interrupt
| #define XUARTPSV_UARTICR_DCDMIC 0x00000004U |
nUARTDCD modem interrupt
| #define XUARTPSV_UARTICR_DSRMIC 0x00000008U |
nUARTDSR modem interrupt
| #define XUARTPSV_UARTICR_FEIC 0x00000080U |
Framing Error Interrupt.
| #define XUARTPSV_UARTICR_OEIC 0x00000400U |
Overrun Error Interrupt.
| #define XUARTPSV_UARTICR_OFFSET 0x0044U |
Interrupt Clear.
Referenced by XUartPsv_CfgInitialize(), and XUartPsv_InterruptHandler().
| #define XUARTPSV_UARTICR_PEIC 0x00000100U |
Parity Error Interrupt.
| #define XUARTPSV_UARTICR_RIMIC 0x00000001U |
nUARTRI modem interrupt
| #define XUARTPSV_UARTICR_RTIC 0x00000040U |
Receive Timeout Interrupt.
| #define XUARTPSV_UARTICR_RXIC 0x00000010U |
Receive Interrupt.
| #define XUARTPSV_UARTICR_TXIC 0x00000020U |
Transmit Interrupt.
| #define XUARTPSV_UARTIFLS_OFFSET 0x0034U |
Interrupt FIFO Level Select.
Referenced by XUartPsv_CfgInitialize(), XUartPsv_GetFifoThreshold(), XUartPsv_SetFifoThreshold(), XUartPsv_SetRxFifoThreshold(), and XUartPsv_SetTxFifoThreshold().
| #define XUARTPSV_UARTIFLS_RXIFLSEL_1_2 0x00000010U |
| #define XUARTPSV_UARTIFLS_RXIFLSEL_1_4 0x00000008U |
| #define XUARTPSV_UARTIFLS_RXIFLSEL_1_8 0x00000000U |
Receive FIFO becomes .
1/8 full
| #define XUARTPSV_UARTIFLS_RXIFLSEL_3_4 0x00000018U |
Receive FIFO becomes * .
3/4 full
| #define XUARTPSV_UARTIFLS_RXIFLSEL_7_8 0x00000020U |
Receive FIFO becomes * .
7/8 full
| #define XUARTPSV_UARTIFLS_RXIFLSEL_MASK 0x00000038U |
Receive interrupt FIFO level select mask.
Referenced by XUartPsv_GetFifoThreshold(), XUartPsv_SetFifoThreshold(), and XUartPsv_SetRxFifoThreshold().
| #define XUARTPSV_UARTIFLS_RXIFLSEL_SHIFT 0x00000003U |
Transmit interrupt FIFO level select shift.
Referenced by XUartPsv_SetFifoThreshold().
| #define XUARTPSV_UARTIFLS_TXIFLSEL_1_2 0x00000002U |
Transmit FIFO becomes * .
1/2 full
Referenced by UartPsvIntrExample(), and XUartPsv_CfgInitialize().
| #define XUARTPSV_UARTIFLS_TXIFLSEL_1_4 0x00000001U |
Transmit FIFO becomes * .
1/4 full
| #define XUARTPSV_UARTIFLS_TXIFLSEL_1_8 0x00000000U |
Transmit FIFO becomes * .
1/8 full
| #define XUARTPSV_UARTIFLS_TXIFLSEL_3_4 0x00000003U |
Transmit FIFO becomes * .
3/4 full
| #define XUARTPSV_UARTIFLS_TXIFLSEL_7_8 0x00000004U |
Transmit FIFO becomes * .
7/8 full
| #define XUARTPSV_UARTIFLS_TXIFLSEL_MASK 0x00000007U |
Receive interrupt FIFO level select mask.
Referenced by XUartPsv_GetFifoThreshold(), XUartPsv_SetFifoThreshold(), and XUartPsv_SetTxFifoThreshold().
| #define XUARTPSV_UARTIFLS_TXIFLSEL_SHIFT 0x00000000U |
Transmit interrupt FIFO level select shift.
Referenced by XUartPsv_SetFifoThreshold(), and XUartPsv_SetTxFifoThreshold().
| #define XUARTPSV_UARTILPR_OFFSET 0x0020U |
IrDA Low-Power Counter.
| #define XUARTPSV_UARTIMSC_BEIM 0x00000200U |
Break Error Interrupt.
Referenced by UartPsvIntrExample().
| #define XUARTPSV_UARTIMSC_CTSMIM 0x00000002U |
nUARTCTS modem interrupt
| #define XUARTPSV_UARTIMSC_DCDMIM 0x00000004U |
nUARTDCD modem interrupt
| #define XUARTPSV_UARTIMSC_DSRMIM 0x00000008U |
nUARTDSR modem interrupt
| #define XUARTPSV_UARTIMSC_FEIM 0x00000080U |
Framing Error Interrupt.
Referenced by UartPsvIntrExample().
| #define XUARTPSV_UARTIMSC_MASK 0x000007FFU |
Valid bit mask.
Referenced by XUartPsv_CfgInitialize(), and XUartPsv_SetInterruptMask().
| #define XUARTPSV_UARTIMSC_OEIM 0x00000400U |
Overrun Error Interrupt.
Referenced by UartPsvIntrExample().
| #define XUARTPSV_UARTIMSC_OFFSET 0x0038U |
Interrupt Mask Set/Clear.
Referenced by XUartPsv_CfgInitialize(), XUartPsv_GetInterruptMask(), XUartPsv_InterruptHandler(), and XUartPsv_SetInterruptMask().
| #define XUARTPSV_UARTIMSC_PEIM 0x00000100U |
Parity Error Interrupt.
Referenced by UartPsvIntrExample().
| #define XUARTPSV_UARTIMSC_RIMIM 0x00000001U |
nUARTRI modem interrupt
| #define XUARTPSV_UARTIMSC_RTIM 0x00000040U |
Receive Timeout Interrupt.
Referenced by UartPsvIntrExample().
| #define XUARTPSV_UARTIMSC_RXIM 0x00000010U |
Receive Interrupt.
Referenced by UartPsvIntrExample().
| #define XUARTPSV_UARTIMSC_TXIM 0x00000020U |
Transmit Interrupt.
Referenced by UartPsvIntrExample().
| #define XUARTPSV_UARTLCR_BRK 0x00000001U |
Send break.
| #define XUARTPSV_UARTLCR_EPS 0x00000004U |
Even parity select.
| #define XUARTPSV_UARTLCR_FEN 0x00000010U |
Enable FIFOs.
Referenced by XUartPsv_CfgInitialize(), and XUartPsv_ProgramCtrlReg().
| #define XUARTPSV_UARTLCR_OFFSET 0x002CU |
Line Control.
Referenced by XUartPsv_CfgInitialize(), XUartPsv_GetDataFormat(), XUartPsv_ProgramCtrlReg(), XUartPsv_SetBaudRate(), and XUartPsv_SetDataFormat().
| #define XUARTPSV_UARTLCR_PARITY_EVEN 0x00000004U |
Even parity mode.
| #define XUARTPSV_UARTLCR_PARITY_MASK 0x00000002U |
Parity mask.
Referenced by XUartPsv_CfgInitialize(), XUartPsv_GetDataFormat(), and XUartPsv_SetDataFormat().
| #define XUARTPSV_UARTLCR_PARITY_NONE 0x00000000U |
No parity mode.
Referenced by XUartPsv_CfgInitialize().
| #define XUARTPSV_UARTLCR_PARITY_ODD 0x00000000U |
Odd parity mode.
| #define XUARTPSV_UARTLCR_PARITY_SHIFT 0x00000001U |
Parity shift.
Referenced by XUartPsv_GetDataFormat(), and XUartPsv_SetDataFormat().
| #define XUARTPSV_UARTLCR_PEN 0x00000002U |
Parity enable.
| #define XUARTPSV_UARTLCR_SPS 0x00000080U |
Stick parity select.
| #define XUARTPSV_UARTLCR_STP2 0x00000008U |
Two stop bits selected.
| #define XUARTPSV_UARTLCR_STP_1_BIT 0x00000000U |
One stop bits selected.
Referenced by XUartPsv_CfgInitialize().
| #define XUARTPSV_UARTLCR_STP_MASK 0x00000008U |
Stop bits mask.
Referenced by XUartPsv_CfgInitialize(), XUartPsv_GetDataFormat(), and XUartPsv_SetDataFormat().
| #define XUARTPSV_UARTLCR_STP_SHIFT 0x00000003U |
Stop bits shift.
Referenced by XUartPsv_GetDataFormat(), and XUartPsv_SetDataFormat().
| #define XUARTPSV_UARTLCR_WLEN_5_BIT 0x00000000U |
5 bits data
| #define XUARTPSV_UARTLCR_WLEN_6_BIT 0x00000020U |
6 bits data
| #define XUARTPSV_UARTLCR_WLEN_7_BIT 0x00000040U |
7 bits data
| #define XUARTPSV_UARTLCR_WLEN_8_BIT 0x00000060U |
8 bits data
Referenced by XUartPsv_CfgInitialize().
| #define XUARTPSV_UARTLCR_WLEN_MASK 0x00000060U |
Word length mask.
Referenced by XUartPsv_CfgInitialize(), XUartPsv_GetDataFormat(), and XUartPsv_SetDataFormat().
| #define XUARTPSV_UARTLCR_WLEN_SHIFT 0x00000005U |
Word length shift.
Referenced by XUartPsv_GetDataFormat(), and XUartPsv_SetDataFormat().
| #define XUARTPSV_UARTMIS_BEMIS 0x00000200U |
Break Error Interrupt.
| #define XUARTPSV_UARTMIS_CTSMMIS 0x00000002U |
nUARTCTS modem interrupt
| #define XUARTPSV_UARTMIS_DCDMMIS 0x00000004U |
nUARTDCD modem interrupt
| #define XUARTPSV_UARTMIS_DSRMMIS 0x00000008U |
nUARTDSR modem interrupt
| #define XUARTPSV_UARTMIS_FEMIS 0x00000080U |
Framing Error Interrupt.
| #define XUARTPSV_UARTMIS_OEMIS 0x00000400U |
Overrun Error Interrupt.
| #define XUARTPSV_UARTMIS_OFFSET 0x0040U |
Mask interrupt Status.
| #define XUARTPSV_UARTMIS_PEMIS 0x00000100U |
Parity Error Interrupt.
| #define XUARTPSV_UARTMIS_RIRMMIS 0x00000001U |
nUARTRI modem interrupt
| #define XUARTPSV_UARTMIS_RTMIS 0x00000040U |
Receive Timeout Interrupt.
| #define XUARTPSV_UARTMIS_RXMIS 0x00000010U |
Receive Interrupt.
| #define XUARTPSV_UARTMIS_TXMIS 0x00000020U |
Transmit Interrupt.
| #define XUARTPSV_UARTRIS_BERIS 0x00000200U |
Break Error Interrupt.
Referenced by XUartPsv_InterruptHandler().
| #define XUARTPSV_UARTRIS_CTSRMIS 0x00000002U |
nUARTCTS modem interrupt
Referenced by XUartPsv_InterruptHandler().
| #define XUARTPSV_UARTRIS_DCDRMIS 0x00000004U |
nUARTDCD modem interrupt
Referenced by XUartPsv_InterruptHandler().
| #define XUARTPSV_UARTRIS_DSRRMIS 0x00000008U |
nUARTDSR modem interrupt
Referenced by XUartPsv_InterruptHandler().
| #define XUARTPSV_UARTRIS_FERIS 0x00000080U |
Framing Error Interrupt.
Referenced by XUartPsv_InterruptHandler().
| #define XUARTPSV_UARTRIS_OERIS 0x00000400U |
Overrun Error Interrupt.
Referenced by XUartPsv_InterruptHandler().
| #define XUARTPSV_UARTRIS_OFFSET 0x003CU |
Raw interrupt Status.
Referenced by XUartPsv_GetModemStatus(), and XUartPsv_InterruptHandler().
| #define XUARTPSV_UARTRIS_PERIS 0x00000100U |
Parity Error Interrupt.
Referenced by XUartPsv_InterruptHandler().
| #define XUARTPSV_UARTRIS_RIRMIS 0x00000001U |
nUARTRI modem interrupt
Referenced by XUartPsv_InterruptHandler().
| #define XUARTPSV_UARTRIS_RTRIS 0x00000040U |
Receive Timeout Interrupt.
Referenced by XUartPsv_InterruptHandler().
| #define XUARTPSV_UARTRIS_RXRIS 0x00000010U |
Receive Interrupt.
Referenced by XUartPsv_InterruptHandler().
| #define XUARTPSV_UARTRIS_TXRIS 0x00000020U |
Transmit Interrupt.
Referenced by XUartPsv_InterruptHandler().
| #define XUARTPSV_UARTRSR_OE 0x00000008U |
Overrun error.
| #define XUARTPSV_UARTRSR_OFFSET 0x0004U |
Receive Status Register/Error Clear.
| #define XUartPsv_WriteReg | ( | BaseAddress, | |
| RegOffset, | |||
| RegisterValue | |||
| ) |
Write a UART register.
| BaseAddress | contains the base address of the device. |
| RegOffset | contains the offset from the base address of the device. |
| RegisterValue | is the value to be written to the register. |
Referenced by XUartPsv_CfgInitialize(), XUartPsv_InterruptHandler(), XUartPsv_ProgramCtrlReg(), XUartPsv_SendBuffer(), XUartPsv_SendByte(), XUartPsv_SetBaudRate(), XUartPsv_SetDataFormat(), XUartPsv_SetFifoThreshold(), XUartPsv_SetInterruptMask(), XUartPsv_SetOptions(), XUartPsv_SetRxFifoThreshold(), and XUartPsv_SetTxFifoThreshold().
| typedef void(* XUartPsv_Handler)(void *CallBackRef, u32 Event, u32 EventData) |
This data type defines a handler that an application defines to communicate with interrupt system to retrieve state information about an application.
| CallBackRef | is a callback reference passed in by the upper layer when setting the handler, and is passed back to the upper layer when the handler is called. It is used to find the device driver instance. |
| Event | contains one of the event constants indicating events that have occurred. |
| EventData | contains the number of bytes sent or received at the time of the call for send and receive events and contains the modem status for modem events. |
| s32 XUartPsv_CfgInitialize | ( | XUartPsv * | InstancePtr, |
| XUartPsv_Config * | Config, | ||
| UINTPTR | EffectiveAddr | ||
| ) |
Initializes a specific XUartPsv instance such that it is ready to be used.
The data format of the device is setup for 8 data bits, 1 stop bit, and no parity by default. The baud rate is set to a default value specified by Config->DefaultBaudRate if set, otherwise it is set to 19.2K baud. The receive FIFO threshold is set for 8 bytes. The default operating mode of the driver is polled mode.
| InstancePtr | is a pointer to the XUartPsv instance. |
| Config | is a reference to a structure containing information about a specific XUartPsv driver. |
| EffectiveAddr | is the device base address in the virtual memory address space. The caller is responsible for keeping the address mapping from EffectiveAddr to the device physical base address unchanged once this function is invoked. Unexpected errors may occur if the address mapping changes after this function is called. If address translation is not used, pass in the physical address instead. |
FIFO's are enabled with a threshold of 16 ytes
All interrupts are disabled.
References XUartPsv_Config::BaseAddress, XUartPsv::Config, XUartPsv::Handler, XUartPsv_Config::InputClockHz, XUartPsv::IsReady, XUartPsv_Config::ModemPinsConnected, XUartPsvBuffer::NextBytePtr, XUartPsv::ReceiveBuffer, XUartPsvBuffer::RemainingBytes, XUartPsvBuffer::RequestedBytes, XUartPsv::SendBuffer, XUARTPSV_DFT_BAUDRATE, XUartPsv_ReadReg, XUartPsv_SetBaudRate(), XUARTPSV_UARTICR_OFFSET, XUARTPSV_UARTIFLS_OFFSET, XUARTPSV_UARTIFLS_RXIFLSEL_1_2, XUARTPSV_UARTIFLS_TXIFLSEL_1_2, XUARTPSV_UARTIMSC_MASK, XUARTPSV_UARTIMSC_OFFSET, XUARTPSV_UARTLCR_FEN, XUARTPSV_UARTLCR_OFFSET, XUARTPSV_UARTLCR_PARITY_MASK, XUARTPSV_UARTLCR_PARITY_NONE, XUARTPSV_UARTLCR_STP_1_BIT, XUARTPSV_UARTLCR_STP_MASK, XUARTPSV_UARTLCR_WLEN_8_BIT, XUARTPSV_UARTLCR_WLEN_MASK, and XUartPsv_WriteReg.
Referenced by UartPsvHelloWorldExample(), UartPsvIntrExample(), UartPsvPolledExample(), and UartPsvSelfTestExample().
| void XUartPsv_CleanupRx | ( | XUartPsv * | InstancePtr | ) |
This function is a cleanup function to allow reseting Rx NextBytePtr, RemainingBytes and RequestedBytes.
References XUartPsvBuffer::NextBytePtr, XUartPsv::ReceiveBuffer, XUartPsvBuffer::RemainingBytes, and XUartPsvBuffer::RequestedBytes.
| void XUartPsv_CleanupTx | ( | XUartPsv * | InstancePtr | ) |
This function is a cleanup function to allow reseting Tx NextBytePtr, RemainingBytes and RequestedBytes.
References XUartPsvBuffer::NextBytePtr, XUartPsvBuffer::RemainingBytes, XUartPsvBuffer::RequestedBytes, and XUartPsv::SendBuffer.
| void XUartPsv_GetDataFormat | ( | XUartPsv * | InstancePtr, |
| XUartPsvFormat * | FormatPtr | ||
| ) |
Gets the data format for the specified UART.
The data format includes the baud rate, number of data bits, number of stop bits, and parity.
| InstancePtr | is a pointer to the XUartPsv instance. |
| FormatPtr | is a pointer to a format structure that will contain the data format after this call completes. |
References XUartPsv_Config::BaseAddress, XUartPsvFormat::BaudRate, XUartPsv::BaudRate, XUartPsv::Config, XUartPsvFormat::DataBits, XUartPsv::IsReady, XUartPsvFormat::Parity, XUartPsvFormat::StopBits, XUartPsv_ReadReg, XUARTPSV_UARTLCR_OFFSET, XUARTPSV_UARTLCR_PARITY_MASK, XUARTPSV_UARTLCR_PARITY_SHIFT, XUARTPSV_UARTLCR_STP_MASK, XUARTPSV_UARTLCR_STP_SHIFT, XUARTPSV_UARTLCR_WLEN_MASK, and XUARTPSV_UARTLCR_WLEN_SHIFT.
| u8 XUartPsv_GetFifoThreshold | ( | XUartPsv * | InstancePtr | ) |
This function gets the Tx and Rx FIFO trigger level.
The receive or transmit trigger level specifies the number of bytes in the FIFO that cause a receive or transmit data event (interrupt) to be generated.
| InstancePtr | is a pointer to the XUartPsv instance. |
References XUartPsv_Config::BaseAddress, XUartPsv::Config, XUartPsv::IsReady, XUartPsv_ReadReg, XUARTPSV_UARTIFLS_OFFSET, XUARTPSV_UARTIFLS_RXIFLSEL_MASK, and XUARTPSV_UARTIFLS_TXIFLSEL_MASK.
| u32 XUartPsv_GetInterruptMask | ( | XUartPsv * | InstancePtr | ) |
This function gets the interrupt mask.
| InstancePtr | is a pointer to the XUartPsv instance. |
References XUartPsv_Config::BaseAddress, XUartPsv::Config, XUartPsv_ReadReg, and XUARTPSV_UARTIMSC_OFFSET.
Referenced by XUartPsv_Recv().
| u16 XUartPsv_GetModemStatus | ( | XUartPsv * | InstancePtr | ) |
This function gets the modem status from the specified UART.
The modem status indicates any changes of the modem signals. This function allows the modem status to be read in a polled mode. The modem status is updated whenever it is read such that reading it twice may not yield the same results.
| InstancePtr | is a pointer to the XUartPsv instance. |
References XUartPsv_Config::BaseAddress, XUartPsv::Config, XUartPsv::IsReady, XUartPsv_ReadReg, and XUARTPSV_UARTRIS_OFFSET.
| u8 XUartPsv_GetOperMode | ( | XUartPsv * | InstancePtr | ) |
This function gets the operational mode of the UART.
The UART can operate in one of four modes: Normal, Local Loopback, Remote Loopback, or automatic echo.
| InstancePtr | is a pointer to the XUartPsv instance. |
References XUartPsv_Config::BaseAddress, XUartPsv::Config, XUartPsv::IsReady, XUARTPSV_OPER_MODE_LOCAL_LOOP, XUARTPSV_OPER_MODE_NORMAL, XUartPsv_ReadReg, XUARTPSV_UARTCR_LBE, XUARTPSV_UARTCR_MODE_MASK, XUARTPSV_UARTCR_MODE_NORMAL, XUARTPSV_UARTCR_MODE_SHIFT, and XUARTPSV_UARTCR_OFFSET.
| u16 XUartPsv_GetOptions | ( | XUartPsv * | InstancePtr | ) |
Gets the options for the specified driver instance.
The options are implemented as bit masks such that multiple options may be enabled or disabled simultaneously.
| InstancePtr | is a pointer to the XUartPsv instance. |
References XUartPsv_Config::BaseAddress, XUartPsv::Config, XUartPsv::IsReady, XUARTPSV_NUM_OPTIONS, and XUartPsv_ReadReg.
| void XUartPsv_InterruptHandler | ( | XUartPsv * | InstancePtr | ) |
This function is the interrupt handler for the driver.
It must be connected to an interrupt system by the application such that it can be called when an interrupt occurs.
| InstancePtr | contains a pointer to the driver instance |
References XUartPsv_Config::BaseAddress, XUartPsv::CallBackRef, XUartPsv::Config, XUartPsv::Handler, XUartPsv::IsReady, XUARTPSV_EVENT_PARE_FRAME_BRKE, XUartPsv_ReadReg, XUARTPSV_UARTICR_OFFSET, XUARTPSV_UARTIMSC_OFFSET, XUARTPSV_UARTRIS_BERIS, XUARTPSV_UARTRIS_CTSRMIS, XUARTPSV_UARTRIS_DCDRMIS, XUARTPSV_UARTRIS_DSRRMIS, XUARTPSV_UARTRIS_FERIS, XUARTPSV_UARTRIS_OERIS, XUARTPSV_UARTRIS_OFFSET, XUARTPSV_UARTRIS_PERIS, XUARTPSV_UARTRIS_RIRMIS, XUARTPSV_UARTRIS_RTRIS, XUARTPSV_UARTRIS_RXRIS, XUARTPSV_UARTRIS_TXRIS, and XUartPsv_WriteReg.
Referenced by UartPsvIntrExample().
| u32 XUartPsv_IsSending | ( | XUartPsv * | InstancePtr | ) |
This function determines if the specified UART is sending data.
| InstancePtr | is a pointer to the XUartPsv instance. |
References XUartPsv_Config::BaseAddress, XUartPsv::Config, XUartPsv::IsReady, XUartPsv_ReadReg, XUARTPSV_UARTFR_BUSY, XUARTPSV_UARTFR_OFFSET, and XUARTPSV_UARTFR_TXFE.
| XUartPsv_Config * XUartPsv_LookupConfig | ( | u16 | DeviceId | ) |
Looks up the device configuration based on the unique device ID.
The table contains the configuration info for each device in the system.
| DeviceId | contains the ID of the device |
References XUartPsv_ConfigTable.
Referenced by UartPsvHelloWorldExample(), UartPsvIntrExample(), UartPsvPolledExample(), and UartPsvSelfTestExample().
| void XUartPsv_ProgramCtrlReg | ( | XUartPsv * | InstancePtr, |
| u32 | CtrlRegister | ||
| ) |
This function reprograms the control register according to the following sequence mentioned in the TRM.
Sequence to Program Control Register.
| InstancePtr | is a pointer to the XUartPsv instance |
| CtrlRegister | value to be written |
References XUartPsv_Config::BaseAddress, XUartPsv::Config, XUartPsv_IsTransmitbusy, XUartPsv_ReadReg, XUARTPSV_UARTCR_OFFSET, XUARTPSV_UARTCR_UARTEN, XUARTPSV_UARTLCR_FEN, XUARTPSV_UARTLCR_OFFSET, and XUartPsv_WriteReg.
Referenced by XUartPsv_SelfTest(), and XUartPsv_SetOperMode().
| u32 XUartPsv_ReceiveBuffer | ( | XUartPsv * | InstancePtr | ) |
This function receives a buffer that has been previously specified by setting up the instance variables of the instance.
This function is an internal function, and it may be called from a shell function that sets up the buffer or from an interrupt handler.
This function attempts to receive a specified number of bytes from the device and store it into the specified buffer. This function works for either polled or interrupt driven modes. It is non-blocking.
In polled mode, this function only receives as much data as in the RX FIFO. The application may need to call it repeatedly to receive the entire buffer. Polled mode is the default mode for the driver.
In interrupt mode, this function starts the receiving, if not the entire buffer has been received, the interrupt handler will continue until the entire buffer has been received. A callback function, as specified by the application, will be called to indicate the completion of the receiving or error conditions.
| InstancePtr | is a pointer to the XUartPsv instance |
References XUartPsv_Config::BaseAddress, XUartPsv::Config, XUartPsvBuffer::NextBytePtr, XUartPsv::ReceiveBuffer, XUartPsvBuffer::RemainingBytes, XUartPsv_ReadReg, XUARTPSV_UARTDR_OFFSET, XUARTPSV_UARTFR_OFFSET, and XUARTPSV_UARTFR_RXFE.
Referenced by XUartPsv_Recv().
| u32 XUartPsv_Recv | ( | XUartPsv * | InstancePtr, |
| u8 * | BufferPtr, | ||
| u32 | NumBytes | ||
| ) |
This function attempts to receive a specified number of bytes of data from the device and store it into the specified buffer.
This function works for both polled or interrupt driven modes. It is non-blocking.
In a polled mode, this function will only receive the data already in the RX FIFO. The application may need to call it repeatedly to receive the entire buffer. Polled mode is the default mode of operation for the device.
In interrupt mode, this function will start the receiving, if not the entire buffer has been received, the interrupt handler will continue receiving data until the entire buffer has been received. A callback function, as specified by the application, will be called to indicate the completion of the receiving or error conditions.
| InstancePtr | is a pointer to the XUartPsv instance |
| BufferPtr | is pointer to buffer for data to be received into |
| NumBytes | is the number of bytes to be received. A value of zero will stop a previous receive operation that is in progress in interrupt mode. |
References XUartPsv::IsReady, XUartPsvBuffer::NextBytePtr, XUartPsv::ReceiveBuffer, XUartPsvBuffer::RemainingBytes, XUartPsvBuffer::RequestedBytes, XUartPsv_GetInterruptMask(), and XUartPsv_ReceiveBuffer().
Referenced by UartPsvIntrExample(), UartPsvPolledExample(), and XUartPsv_SelfTest().
| u8 XUartPsv_RecvByte | ( | UINTPTR | BaseAddress | ) |
This function receives a byte from the device.
It operates in polled mode and blocks until a byte has received.
| BaseAddress | contains the base address of the device. |
References XUartPsv_IsReceiveData, XUartPsv_ReadReg, and XUARTPSV_UARTDR_OFFSET.
| void XUartPsv_ResetHw | ( | UINTPTR | BaseAddress | ) |
This function resets UART.
(To be implemented if needed)
| BaseAddress | contains the base address of the device. |
| s32 XUartPsv_SelfTest | ( | XUartPsv * | InstancePtr | ) |
This function runs a self-test on the driver and hardware device.
This self test performs a local loopback and verifies data can be sent and received.
The time for this test is proportional to the baud rate that has been set prior to calling this function.
The mode and control registers are restored before return.
| InstancePtr | is a pointer to the XUartPsv instance |
References XUartPsv_Config::BaseAddress, XUartPsv::Config, XUartPsv::IsReady, XUARTPSV_OPER_MODE_LOCAL_LOOP, XUartPsv_ProgramCtrlReg(), XUartPsv_ReadReg, XUartPsv_Recv(), XUartPsv_Send(), XUartPsv_SetOperMode(), XUARTPSV_TOTAL_BYTES, XUARTPSV_UARTCR_OFFSET, XUARTPSV_UARTFR_OFFSET, and XUARTPSV_UARTFR_RXFE.
Referenced by UartPsvHelloWorldExample(), UartPsvIntrExample(), UartPsvPolledExample(), and UartPsvSelfTestExample().
| u32 XUartPsv_Send | ( | XUartPsv * | InstancePtr, |
| u8 * | BufferPtr, | ||
| u32 | NumBytes | ||
| ) |
This functions sends the specified buffer using the device in either polled or interrupt driven mode.
This function is non-blocking, if the device is busy sending data, it will return and indicate zero bytes were sent. Otherwise, it fills the TX FIFO as much as it can, and return the number of bytes sent.
In a polled mode, this function will only send as much data as TX FIFO can buffer. The application may need to call it repeatedly to send the entire buffer.
In interrupt mode, this function will start sending the specified buffer, then the interrupt handler will continue sending data until the entire buffer has been sent. A callback function, as specified by the application, will be called to indicate the completion of sending.
| InstancePtr | is a pointer to the XUartPsv instance. |
| BufferPtr | is pointer to a buffer of data to be sent. |
| NumBytes | contains the number of bytes to be sent. A value of zero will stop a previous send operation that is in progress in interrupt mode. Any data that was already put into the transmit FIFO will be sent. |
References XUartPsv::IsReady, XUartPsvBuffer::NextBytePtr, XUartPsvBuffer::RemainingBytes, XUartPsvBuffer::RequestedBytes, XUartPsv::SendBuffer, and XUartPsv_SendBuffer().
Referenced by UartPsvHelloWorldExample(), UartPsvIntrExample(), UartPsvPolledExample(), and XUartPsv_SelfTest().
| u32 XUartPsv_Send_NoWait | ( | XUartPsv * | InstancePtr, |
| u8 * | BufferPtr, | ||
| u32 | NumBytes | ||
| ) |
| InstancePtr | is a pointer to the XUartPsv instance. |
| BufferPtr | is pointer to a buffer of data to be sent. |
| NumBytes | contains the number of bytes to be sent. A value of |
References XUartPsv_Config::BaseAddress, XUartPsv::Config, XUartPsv::IsReady, XUartPsvBuffer::NextBytePtr, XUartPsvBuffer::RemainingBytes, XUartPsvBuffer::RequestedBytes, XUartPsv::SendBuffer, and XUartPsv_IsTransmitbusy.
| u32 XUartPsv_SendBuffer | ( | XUartPsv * | InstancePtr | ) |
This function sends a buffer that has been previously specified by setting up the instance variables of the instance.
This function is an internal function for the XUartPsv driver such that it may be called from a shell function that sets up the buffer or from an interrupt handler.
This function sends the specified buffer in either polled or interrupt driven modes. This function is non-blocking.
In a polled mode, this function only sends as much data as the TX FIFO can buffer. The application may need to call it repeatedly to send the entire buffer.
In interrupt mode, this function starts the sending of the buffer, if not the entire buffer has been sent, then the interrupt handler continues the sending until the entire buffer has been sent. A callback function, as specified by the application, will be called to indicate the completion of sending.
| InstancePtr | is a pointer to the XUartPsv instance |
References XUartPsv_Config::BaseAddress, XUartPsv::Config, XUartPsvBuffer::NextBytePtr, XUartPsvBuffer::RemainingBytes, XUartPsv::SendBuffer, XUartPsv_IsTransmitFull, XUARTPSV_UARTDR_OFFSET, XUARTPSV_UARTFR_BUSY, XUARTPSV_UARTFR_OFFSET, and XUartPsv_WriteReg.
Referenced by XUartPsv_Send().
| void XUartPsv_SendByte | ( | UINTPTR | BaseAddress, |
| u8 | Data | ||
| ) |
This function sends one byte using the device.
This function operates in polled mode and blocks until the data has been put into the TX FIFO register.
| BaseAddress | contains the base address of the device. |
| Data | contains the byte to be sent. |
References XUartPsv_IsTransmitFull, XUARTPSV_UARTDR_OFFSET, and XUartPsv_WriteReg.
| s32 XUartPsv_SetBaudRate | ( | XUartPsv * | InstancePtr, |
| u32 | BaudRate | ||
| ) |
Sets the baud rate for the device.
Checks the input value for validity and also verifies that the requested rate can be configured to within the maximum error range specified by XUARTPSV_MAX_BAUD_ERROR_RATE. If the provided rate is not possible, the current setting is unchanged.
| InstancePtr | is a pointer to the XUartPsv instance |
| BaudRate | to be set |
References XUartPsv_Config::BaseAddress, XUartPsv::BaudRate, XUartPsv::Config, XUartPsv_Config::InputClockHz, XUartPsv::IsReady, XUartPsv_DisableUart, XUartPsv_EnableUart, XUARTPSV_MAX_BAUD_ERROR_RATE, XUARTPSV_MAX_RATE, XUARTPSV_MIN_RATE, XUartPsv_ReadReg, XUARTPSV_UARTFBRD_OFFSET, XUARTPSV_UARTIBRD_OFFSET, XUARTPSV_UARTLCR_OFFSET, and XUartPsv_WriteReg.
Referenced by XUartPsv_CfgInitialize(), and XUartPsv_SetDataFormat().
| s32 XUartPsv_SetDataFormat | ( | XUartPsv * | InstancePtr, |
| XUartPsvFormat * | FormatPtr | ||
| ) |
Sets the data format for the device.
The data format includes the baud rate, number of data bits, number of stop bits, and parity. It is the caller's responsibility to ensure that the UART is not sending or receiving data when this function is called.
| InstancePtr | is a pointer to the XUartPsv instance. |
| FormatPtr | is a pointer to a format structure containing the data format to be set. |
References XUartPsv_Config::BaseAddress, XUartPsvFormat::BaudRate, XUartPsv::Config, XUartPsvFormat::DataBits, XUartPsv::IsReady, XUartPsvFormat::Parity, XUartPsvFormat::StopBits, XUARTPSV_FORMAT_2_STOP_BIT, XUARTPSV_FORMAT_8_BITS, XUARTPSV_FORMAT_EN_PARITY, XUARTPSV_FORMAT_EN_STICK_PARITY, XUARTPSV_FORMAT_EN_STICK_PARITY_SHIFT, XUARTPSV_FORMAT_EVEN_PARITY, XUARTPSV_FORMAT_EVEN_PARITY_SHIFT, XUARTPSV_FORMAT_PARITY_MASK, XUartPsv_ReadReg, XUartPsv_SetBaudRate(), XUARTPSV_UARTLCR_OFFSET, XUARTPSV_UARTLCR_PARITY_MASK, XUARTPSV_UARTLCR_PARITY_SHIFT, XUARTPSV_UARTLCR_STP_MASK, XUARTPSV_UARTLCR_STP_SHIFT, XUARTPSV_UARTLCR_WLEN_MASK, XUARTPSV_UARTLCR_WLEN_SHIFT, and XUartPsv_WriteReg.
| void XUartPsv_SetFifoThreshold | ( | XUartPsv * | InstancePtr, |
| u8 | TriggerLevel | ||
| ) |
This functions sets the Tx and Rx FIFO trigger level to the 'TriggerLevel' argument.
The same value is set for Tx and Rx FIFOs. The receive or transmit trigger level specifies the number of bytes in the FIFO that cause a receive or transmit data event (interrupt) to be generated.
| InstancePtr | is a pointer to the XUartPsv instance. |
| TriggerLevel | contains the trigger level to set. This is a value from 0-7 |
References XUartPsv_Config::BaseAddress, XUartPsv::Config, XUartPsv::IsReady, XUartPsv_ReadReg, XUARTPSV_UARTIFLS_OFFSET, XUARTPSV_UARTIFLS_RXIFLSEL_MASK, XUARTPSV_UARTIFLS_RXIFLSEL_SHIFT, XUARTPSV_UARTIFLS_TXIFLSEL_MASK, XUARTPSV_UARTIFLS_TXIFLSEL_SHIFT, and XUartPsv_WriteReg.
| void XUartPsv_SetHandler | ( | XUartPsv * | InstancePtr, |
| XUartPsv_Handler | FuncPtr, | ||
| void * | CallBackRef | ||
| ) |
This function sets the handler that will be called when an event (interrupt) occurs that needs application's attention.
| InstancePtr | is a pointer to the XUartPsv instance |
| FuncPtr | is the pointer to the callback function. |
| CallBackRef | is the upper layer callback reference passed back when the callback function is invoked. |
References XUartPsv::CallBackRef, XUartPsv::Handler, and XUartPsv::IsReady.
Referenced by UartPsvIntrExample().
| void XUartPsv_SetInterruptMask | ( | XUartPsv * | InstancePtr, |
| u32 | Mask | ||
| ) |
This function sets the interrupt mask.
| InstancePtr | is a pointer to the XUartPsv instance |
| Mask | contains the interrupts to be enabled or disabled. A '1' enables an interrupt, and a '0' disables. |
References XUartPsv_Config::BaseAddress, XUartPsv::Config, XUARTPSV_UARTIMSC_MASK, XUARTPSV_UARTIMSC_OFFSET, and XUartPsv_WriteReg.
Referenced by UartPsvIntrExample().
| void XUartPsv_SetOperMode | ( | XUartPsv * | InstancePtr, |
| u8 | OperationMode | ||
| ) |
This function sets the operational mode of the UART.
The UART can operate in one of four modes: Normal, Local Loopback, Remote Loopback, or automatic echo.
| InstancePtr | is a pointer to the XUartPsv instance. |
| OperationMode | is the mode of the UART. |
References XUartPsv_Config::BaseAddress, XUartPsv::Config, XUartPsv::IsReady, XUARTPSV_OPER_MODE_LOCAL_LOOP, XUARTPSV_OPER_MODE_NORMAL, XUartPsv_ProgramCtrlReg(), XUartPsv_ReadReg, XUARTPSV_UARTCR_LBE, XUARTPSV_UARTCR_MODE_MASK, XUARTPSV_UARTCR_MODE_NORMAL, and XUARTPSV_UARTCR_OFFSET.
Referenced by UartPsvIntrExample(), UartPsvPolledExample(), and XUartPsv_SelfTest().
| void XUartPsv_SetOptions | ( | XUartPsv * | InstancePtr, |
| u16 | Options | ||
| ) |
Sets the options for the specified driver instance.
The options are implemented as bit masks such that multiple options may be enabled or disabled simultaneously.
The GetOptions function may be called to retrieve the currently enabled options. The result is ORed in the desired new settings to be enabled and ANDed with the inverse to clear the settings to be disabled. The resulting value is then used as the options for the SetOption function call.
| InstancePtr | is a pointer to the XUartPsv instance. |
| Options | contains the options to be set which are bit masks contained in the file xuartpsv.h and named XUARTPSV_OPTION_*. |
References XUartPsv_Config::BaseAddress, XUartPsv::Config, XUartPsv::IsReady, XUARTPSV_NUM_OPTIONS, XUartPsv_ReadReg, and XUartPsv_WriteReg.
| void XUartPsv_SetRxFifoThreshold | ( | XUartPsv * | InstancePtr, |
| u8 | TriggerLevel | ||
| ) |
This functions sets the Rx FIFO trigger level to the 'TriggerLevel' argument.
This value is set for Rx FIFO. Tx FIFO trigger level is unchanged. The receive or transmit trigger level specifies the number of bytes in the FIFO that cause a receive or transmit data event (interrupt) to be generated.
| InstancePtr | is a pointer to the XUartPsv instance. |
| TriggerLevel | contains the trigger level to set. This is a value from 0-32 (XUARTPSV_UARTIFLS_RXIFLSEL_1_8 - XUARTPSV_UARTIFLS_RXIFLSEL_7_8) |
References XUartPsv_Config::BaseAddress, XUartPsv::Config, XUartPsv::IsReady, XUartPsv_ReadReg, XUARTPSV_UARTIFLS_OFFSET, XUARTPSV_UARTIFLS_RXIFLSEL_MASK, and XUartPsv_WriteReg.
Referenced by UartPsvIntrExample().
| void XUartPsv_SetTxFifoThreshold | ( | XUartPsv * | InstancePtr, |
| u8 | TriggerLevel | ||
| ) |
This functions sets the Tx FIFO trigger level to the 'TriggerLevel' argument.
This value is set for Tx FIFO. Rx FIFO trigger level is unchanged. The receive or transmit trigger level specifies the number of bytes in the FIFO that cause a receive or transmit data event (interrupt) to be generated.
| InstancePtr | is a pointer to the XUartPsv instance. |
| TriggerLevel | contains the trigger level to set. This is a value from 0-4 (XUARTPSV_UARTIFLS_TXIFLSEL_1_8 - XUARTPSV_UARTIFLS_TXIFLSEL_7_8) |
References XUartPsv_Config::BaseAddress, XUartPsv::Config, XUartPsv::IsReady, XUartPsv_ReadReg, XUARTPSV_UARTIFLS_OFFSET, XUARTPSV_UARTIFLS_TXIFLSEL_MASK, XUARTPSV_UARTIFLS_TXIFLSEL_SHIFT, and XUartPsv_WriteReg.
Referenced by UartPsvIntrExample().
| XUartPsv_Config XUartPsv_ConfigTable[] |
Config structure.
Referenced by XUartPsv_LookupConfig().