Xilinx Vitis Drivers API Documentation
xxvethernet Documentation

The Xilinx XXV Ethernet MAC driver component. This driver supports both XXV Ethernet core and USXGMII core on Zynq Ultrascale+ MPSoC. The MAC portion of USXMGII and XXV ethernet is similar. Speed supported for XXV Ethernet core is 10Gbps. Speed supported for USXGMII core is 1Gbps or 2.5Gbps.

For a full description of XXV Ethernet features, please see the hardware spec. This driver supports the following features:

  • Access to host interface registers
  • Interfacing to target MCDMA device via application
  • Full duplex operation
  • Automatic PAD & FCS insertion and stripping (programmable)
  • Jumbo frame support

For full description of USXGMII features, please refer to hardware spec. In addition to the above MAC features, USXGMII core supports USXGMII PHY functionality. This driver supports the same.

Driver Description

The device driver enables higher layer software (e.g., an application) to configure an Xxv Ethernet device. It is intended that this driver be used in cooperation with another MCDMA driver for data communication..

Initialization & Configuration

The XXxvEthernet_Config structure can be used by the driver to configure itself. This configuration structure is typically created by the tool-chain based on hardware build properties.

The driver instance can be initialized using the XXvEthernet_CfgInitialze() routine.

Interrupts and Asynchronous Callbacks

The driver has no dependencies on the interrupt controller. It provides no interrupt handlers. The application/OS software should set up its own interrupt handlers if required based on the target DMA device.

Device Reset

When an Xxv Ethernet device is connected up to a MCDMA core in hardware, reset is controlled by the latter. If a reset is performed, the calling code should also reconfigure and reapply the proper settings in the Xxv Ethernet device. When an Xxv Ethernet device reset is required, XXxvEthernet_Reset() should be utilized. For GT/Serdes reset, refer to the example.

Transferring Data

The Xxv Ethernet core by itself is not capable of transmitting or receiving data in any meaningful way. Instead the Xxv Ethernet device needs to be connected to a FIFO or DMA core in hardware, currently MCDMA is supported.

This Xxv Ethernet driver is modeled in a similar fashion where the application code or O/S adapter driver needs to make use of a separate MCDMA driver in connection with this driver to establish meaningful communication over Ethernet.

PHY Communication

XXV Ethernet core: This device supports clause 49 10GBaseKR at the moment. There is no autonegotiation enabled by default - the autonegotiation speed is limited to 10G.

USXGMII core: This driver supports USXMGII autonegotiation at 1G and and 2.5G. The core also supports 10G and 5G speeds but it is not validated with this driver. There is also an option to bypass autonegotiation.


Asserts are used within all Xilinx drivers to enforce constraints on argument values. Asserts can be turned off on a system-wide basis by defining, at compile time, the NDEBUG identifier. By default, asserts are turned on and it is recommended that users leave asserts on during development. For deployment use -DNDEBUG compiler switch to remove assert code.


Xilinx drivers are typically composed of two components, one is the driver and the other is the adapter. The driver is independent of OS and processor and is intended to be highly portable. The adapter is OS-specific and facilitates communication between the driver and an OS.

This driver is intended to be RTOS and processor independent. Any needs for dynamic memory management, threads or thread mutual exclusion, or cache control must be satisfied by the layer above this driver.

Ver   Who  Date     Changes

1.0 hk 6/16/17 First release hk 2/15/18 Add support for USXGMII 1.1 mj 3/30/18 Add Macro XXxvEthernet_IsMcDma(InstancePtr) to check McDma is connected or not. 1.4 rsp 05/08/20 Include sleep.h header 1.6 sk 02/18/21 Use UINTPTR instead of u32 for XxvDevBaseAddress variable.