Kria™ KV260 Vision AI Starter Kit
Hardware Architecture of the Accelerator
Hardware Architecture of the Accelerator¶
Pre-processing IPs and DPU¶
The Vitis™ software platform overlay includes the pre-processing IPs and DPU.
The pre-processing block as shown in the figure below includes the following functions:
Cvtcolor: Reads an NV12 video frame and converts the color format to BGR
Resizing: Scales down the original 4K/1080p frame to at most 720x720
Quantizing: Performs linear transformation (scaling and shifting) to each pixel of BGR frame to satisfy DPU input requirement
The desgin uses Vitis Vision Library functions to build the pre-processing block. The Vitis functions used are, cvtcolor, resize, and blobfromimage.
The DPU IP as shown in the figure below can be configured.
For this design, the following features should be enabled:
Relu, LeakyRelu and Relu6
To learn more about the DPU, please refer the PG338
Vitis integrates the pre-processing IP and DPU IP in the platform. The table below shows utilization numbers after optimization of the hardware design.
Resource usage of current design
Other* : AXI interconnects and Interrupt concat block added by Vitis
The table below shows estimated DPU performance and overall power on the K26 chip (including 4K based pre-processing and other IPs). The DPU runs at 300MHz/600MHz.
DPU performance and power (estimated)
|TOPS (Peak)||TOPS (DenseBox)1||Power (Overall)2|
We use DenseBox_640x360 model to estimate the real performance of DPU, and this model has 1.1GOPs;
We can only estimate the overall power of K26 chip (including DPU and other IPs)
DPU B3136 bandwidth estimates are shown in the table below
DPU B3136 bandwidth estimates
Vitis Vision functions:
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