Iron-level explicit per-tile DMA program.
Peer of :class:`Worker` (which describes the compute body of a tile).
A :class:`TileDma` describes the DMA engine program for the same (or a
different) tile — what each hardware DMA channel does, which buffers
it reads/writes, and how it synchronizes with the compute side via
locks.
Used together with :class:`Flow` / :class:`PacketFlow` (which describe
the AXI-stream routes) and explicit :class:`Buffer` + :class:`Lock`
declarations, for designs where :class:`ObjectFifo` would hide too much
to be useful.
