4.2. Create the Vitis Platform

4.2.1. Prerequisites

  • Reference Design source files

  • Vivado Design Suite 2022.2

  • Vitis Unified Software Platform 2022.2

4.2.2. Build Flow Tutorial

Clone the Reference Design Files:

Skip this step if the design has already been cloned and extracted to a working directory

  1. Clone the VCK190 Base TRD repository using the following command

    git clone --branch 2022.2 --recursive https://github.com/Xilinx/vck190-pcie-trd.git

The directory structure is described in the Introduction Section.

Create a Vitis Extensible Platform:

  1. To create the Vitis platform, run the following Make script:

    cd $working_dir
make platform PFM=vck190_mipiRxSingle_hdmiTx

  2. The generated platform will be located at:

    $working_dir/platforms/xilinx_vck190_mipiRxSingle_hdmiTx_202220_1

    It will be used as input when building the Vitis accelerator projects.

  3. The Makefile implements the following:

    • Builds the ISP pipeline from the Vitis Vision Libraries using Vitis HLS tool.

    • Generates the XSA for the platform using Vivado tool.

  4. The following is a list of important output products:

    • IP files

      $working_dir/platforms/vivado/ip

    • Vivado project

      $working_dir/platforms/vivado/vck190_mipiRxSingle_hdmiTx/project/vck190_mipiRxSingle_hdmiTx.xpr

    • XSA

      $working_dir/platforms/vivado/vck190_mipiRxSingle_hdmiTx/project/vck190_mipiRxSingle_hdmiTx.xsa

View Platform Interfaces (Optional)

  1. Open the Vivado project.

    At the command prompt enter:

    cd $working_dir/platform/vivado/vck190_mipiRxSingle_hdmiTx/project
vivado vck190_mipiRxSingle_hdmiTx.xpr

  2. In the Flow Navigator pane on the left-hand side under IP Integrator, click on Open Block Design. An IP Integrator (IPI) block design (vck190_mipiRxSingle_hdmiTx.bd) becomes visible that contains the Control, Interface and Processing System (CIPS) IP, NOC IP, AXI Performace Monitors (APM), MIPI CSI capture pipeline and HDMI Tx display pipeline.

  3. To view the Platform interfaces that are enabled for Vitis compiler to stitch in accelerators, on the tool bar at the top click on Window > Platform Setup. Platform interfaces are enabled under the following IPs

    • clk_wiz: Clocks used to drive clock inputs on the accelerator.

    • smartconnect_gp2: AXI Memory Mapped master ports to drive the accelerator control port.

    • NOC_0: AXI Memory Mapped slave ports driven by the accelerator data port.

    • intc_0: Interrupt contoller to forward interrupts from the accelerator to the Procesing System

    Tip

    For more information on how to setup Platform Interfaces refer to Section - Creating an Embedded Platform in Xilinx Vitis Unified Software Platform Documentation(UG1393)

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