Hardware Architecture of the Accelerator

Processing Pipeline

A memory-to-memory (M2M) pipeline reads video frames from memory, does certain processing, and then writes the processed frames back into memory. A block diagram of the process pipeline is shown in the following figure.

../../../_images/M2M_Processing_Pipeline_Showing_Hardware_Accelerator_and_DataMotion.png

The M2M processing pipeline with the 2D convolution filter in the design is entirely generated by the Vitis™ tool based on a C-code description. The 2D filter function is translated to RTL using the Vivado® HLS compiler. The data motion network used to transfer video buffers to/from memory and to program parameters (such as video dimensions and filter coefficients) is inferred automatically by the v++ compiler within the Vitis tool.

Resource usage of current design

Table 1: Key Component Clock Frequencies

xcvm1802-vsva2197

CLB LUTs

BRAM

DSP

URAM

Available

899840

967

1968

463

Platform

128707

269

418

2

Filter2d_pl

7330

24.5

81

0

Total

136037

293.5

499

2

Next Steps

License

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