DMA test case description¶

The goal of this test case is to check communication and available bandwidth between host and memories available on the Alveo™ card (for example: DDR/HBM) through the PCIe. Data integrity and write/read bandwidths are measured.

The DMA test case consists of writing and reading back data to and from the entire range of the memory under test over and over during a certain period. A write-read-check cycle is never interrupted, meaning that:

Data is always fully sent and read back to and from the entire range of the memory and checked for data integrity.

If required, a test duration can be extended to perform all write-read-check cycle operations.

The data sent and read back to and from the memory is:

Generated via an 8-bit counter that is randomly initialized at the beginning of each write-read-check cycle.

Split into buffers which are transferred (via DMA driver) to or from the Alveo card.

The test JSON parameter total_size can be used to override the quantity of data (in MB) sent and read back to and from the memory for each type of memory available on the card (for example HBM/DDR). When not specified, total_size defaults to the memory size.

The write/read bandwidths are computed after all write/read data transfers in each write-read-check cycle and the values are averaged over the test duration.

Important

By default, the average read and write bandwidths are not checked against any pass/fail criteria, but this can be overruled by setting check_bw.

Test parameters¶

The mandatory test configuration parameters are listed below. For more information, see DMA test JSON members.

duration: The duration of the test (in seconds).

target: Name of the memory type (for example: DDR/HBM) or tag (for example: DDR[0]/HBM[12]) of memory to access.

The following optional parameter may also be specified:

buffer_size: Write/read buffer size.

Main test steps¶

For each test configuration, the following steps are repeated:

Allocate N host buffers aligned with memory page size.

The number of buffers N equals total_size divided by buffer_size.

The memory page size is detected automatically and displayed at the beginning of the DMA test case in xbtest.log file.

Allocate and initialize the reference buffer used to check data integrity.

Write-read-check cycles are repeated for the duration of the test. One cycle consists of the following steps:

Set host buffers with reference data (8-bit counter).

Write host buffers to the card memory, measure bandwidth.

Reset host buffers to 0.

Read from the card memory, measure bandwidth.

Check that the host buffers contain the same data as the reference buffers (data integrity). Host buffers are set with reference data if data integrity fails.

Note

These steps constitute a write-read-check cycle which is always entirely executed. If stop_on_error is set, the DMA test case aborts in case of write/read transfer or data integrity error.

Compute write and read minimum, maximum, and average bandwidths.

If enabled, compare the average read and write bandwidths against their thresholds.

Release all host buffers.

Low DMA bandwidth troubleshooting¶

The DMA test always reports the read and write bandwidths. There are many factors influencing these bandwidths:

Server PCIe architecture.

PCIe load on other cards.

E.g. DMA.

PCIe link training:

xbtest reports a message if the PCIe is not operating at its best rate.

The Linux command lspci can also report the speed and the quantity of lanes in use.
CPU affinity (NUMA nodes): the CPU affinity of the card is reported by the following command:
$ ami_tool pcieinfo -d <BDF>
Use the Linux command taskset to run xbtest on the desired CPUs. For example:
$ taskset -c 0,2,4,6,8,10 xbtest -d <BDF> -c dma

DMA test JSON members¶

Definition¶

The following table shows all members available for this test case. More details are provided for each member in the subsequent sections.

DMA test case members¶
Member	Memory Type Override	Mandatory / Optional	Description
test_sequence	No	Mandatory	Describes the sequence of tests to perform.
check_bw	Yes	Optional	Enable bandwidth checking. Disabled by default.
stop_on_error	Yes	Optional	Enable stop test case on error. Disabled by default.
hi_thresh_wr hi_thresh_rd	Only	Optional	Overwrite high threshold of the write/read bandwidth (MB/s) for specified memory type.
lo_thresh_wr lo_thresh_rd	Only	Optional	Overwrite low threshold of the write/read bandwidth (MB/s) for specified memory type.
total_size	Only	Optional	Total amount of data (MB) per bandwidth measurement for specified memory type.

Basic examples¶

The following is a basic example of a DMA test case targeting all DDR and HBM memories available on the card. All memories are tested serially.

"dma": {
  "global_config": {
    "test_sequence": [
      { "duration": 10, "target": "DDR" },
      { "duration": 10, "target": "HBM" }
    ]
  }
}

Some test JSON members can be overwritten for all memories based on memory type using the test JSON member memory_type_config which child members are memory type names.

Following is an example of DMA test case where the comparison of the average read and write bandwidths against thresholds is enabled only for all memories of type HBM.

"dma": {
  "global_config": {
    "stop_on_error": true,
    "test_sequence": [
      { "duration": 10, "target": "DDR" },
      { "duration": 10, "target": "HBM" }
    ]
  },
  "memory_type_config": {
    "HBM": {
      "check_bw": true,
      "hi_thresh_wr": 13000,
      "hi_thresh_rd": 13000,
      "lo_thresh_wr": 9000,
      "lo_thresh_rd": 9000
    }
  }
}

Note

By default, bandwidths are not checked, so check_bw is set to true.

The following example shows how to run DMA test case only for one (identified by memory tag DDR[1]) of the memories of the type named DDR, overriding total_size value to 1GB:

"dma": {
  "global_config": {
    "test_sequence": [
      { "duration": 10, "target": "DDR[1]" }
    ]
  },
  "memory_type_config": {
    "DDR": {
      "total_size" : 1024
    }
  }
}

`test_sequence`¶

Mandatory. Describes the sequence of tests to perform. Tests are performed serially, and a failure in one test does not stop the sequence (the next test will be launched). There is no limitation to the length of the test sequence.

This field contains a list of tests, each test being defined by an object of key–value parameters pairs: [ {}, {}, {} ].

The following table defines the parameters supported in the DMA test sequence:

DMA test sequence parameters¶
Member	Mandatory / Optional	Description
`duration`	Mandatory	The duration of the test in seconds; Range [1, 2³²-1].
`target`	Mandatory	Name of the memory type (for example: DDR/HBM) or tag (for example DDR[0]/HBM[12]) of memory to access: The index must be within the range specified in Card definition JSON file. When a test is defined by memory type. One test is created for each memory tag of the memory type. Note The memory tags applicable for each memory type are displayed when the DMA test case starts. The test fails when the name provided does not match any of the memory type available in the xbtest metadata.
`buffer_size`	Optional	Write/read buffer size in MB. Range [1, `max_buffer_size`] where `max_buffer_size` equals the memory size capped at 2048 MB. Default: specified in the Card definition, typically 256 MB. The number of buffers used in the test equals total_size divided by buffer_size.

Note

The different Alveo™ cards have different memory types.

The following command, using option -g, allows to identify the names of available memory types and associated memory tags on the card selected with card BDF <BDF>:

$ xbtest -d <BDF> -g dma

For example:

Single test:

"test_sequence": [ { "duration": 50, "target": "DDR" } ]

"test_sequence": [ { "duration": 50, "target": "HBM" } ]

"test_sequence": [ { "duration": 50, "target": "DDR[0]" } ]

"test_sequence": [ { "duration": 50, "target": "HBM[1]", "buffer_size": 128 } ]

Multiple tests:

"test_sequence": [
  { "duration": 50, "target": "DDR[0]" },
  { "duration": 20, "target": "DDR[1]" },
  { "duration": 10, "target": "DDR[2]" }
]

Note

If, in xbtest metadata, the memory tags DDR[0] and DDR[1] are available for the memory type named DDR, then the sequence set to:

"test_sequence": [ { "duration": 15, "target": "DDR[0]" }, { "duration": 15, "target": "DDR[1]" } ]

is equivalent to the sequence:

"test_sequence": [ { "duration": 15, "target": "DDR" } ]

`check_bw`¶

Optional; Type : boolean; Possible values: false or true; Default : false.

By setting this member to true, average bandwidth measurements will be compared against defined thresholds. When set to false, no average bandwidth measurement will be checked.

Default bandwidth limits are defined in Card definition and are displayed at the beginning of the tests.

The bandwidth limits can be overwritten using the following parameters:

hi_thresh_wr, hi_thresh_rd.

lo_thresh_wr, lo_thresh_rd.

`stop_on_error`¶

Optional; Type : boolean; Possible values: false or true; Default : false.

By default, the write-read-check cycles are always executed during the entire test duration even if errors occurred during a cycle. By setting this member to true, the DMA test case will stop in case of write / read transfer or data integrity error.

`hi_thresh_wr`, `hi_thresh_rd`¶

Optional; Type : integer; Possible values: from 1 to 2³²-1; Default : specified in the Card definition.

Overwrite high threshold of the write/read bandwidth (MB/s) specified in the Card definition for specified memory type. After all bandwidth measurements made during the test duration are complete, if the measured bandwidth is greater than this threshold, the test fails.

`lo_thresh_wr`, `lo_thresh_rd`¶

Optional; Type : integer; Range : [1, 2³²-1]; Default: specified in the Card definition.

Overwrite low threshold of the DDR/HBM write/read bandwidth (MB/s) specified in the Card definition for specified memory type. After all bandwidth measurements made during the test duration are complete, if the measured bandwidth is lower than this threshold, the test fails. Low threshold must be lower than high threshold.

`total_size`¶

Optional; Type : integer; Possible values: from minimum buffer size to memory size; Default : memory size.

Override the total amount of data (in MB) per transfer cycle for specified memory type. When not specified, it defaults to the memory size. This must be a multiple of the buffer_size parameter for all tests in the test_sequence.

Output files¶

All DMA measurements are stored in output CSV files which are generated in xbtest logging directory. The values are stored in CSV type format with one column for each information type.

Important

If the command line option -L is used while calling xbtest application software (xbtSW), no output file is generated.

In the DMA test case, two different CSV files are used to store all test results. They are named with the following convention:

dma_detail.csv

dma_result.csv

`dma_detail.csv` output file¶

This file contains all intermediate bandwidth measurements for all memory types available on the card (for example: DDR/HBM). There is one line of result for every write-read-check cycle of each test of the test_sequence. The following table summarizes the content of this file, where the following columns represent groups of columns present in the file for a Alveo Versal Example Design (AVED) containing a memory type named DDR with the two tags DDR[0] and DDR[1] associated and containing also a memory type named HBM with the 32 tags associated: HBM[0] to HBM[31]:

write results: Group of columns for DMA write results.
read results: Group of columns for DMA read results.

Example: `dma_detail.csv`¶
Test	memory tag	buffer size (MB)	Cycle ID	Data integrity	write results	read results
1	DDR[0]	256	0	OK	…	…
1	DDR[0]	256	1	OK	…	…
…	…	…	…	…	…	…
2	DDR[1]	256	0	OK	…	…
2	DDR[1]	256	1	OK	…	…
…	…	…	…	…	…	…
3	HBM[0]	256	0	OK	…	…
…	…	…	…	…	…	…
4	HBM[1]	256	0	OK	…	…
…	…	…	…	…	…	…
34	HBM[31]	256	0	OK	…	…

Where:

Test: Index of current test within the test_sequence. Index of first test is 1.

memory tag: Tested memory name.

buffer size (MB): Size of buffers transferred during the test.

Cycle ID: Index of the write-read-check cycle: the number of cycles depends on test duration and quantity of data transferred.

Data integrity: Data integrity result for the current write-read-check cycle.

write results: This group contains the following columns:

live write BW (MBps): DMA write BW measurements for the current write-read-check cycle.

minimum write BW (MBps): Minimum of DMA write BW measurements.

average write BW (MBps): Average of DMA write BW measurements.

maximum write BW (MBps): Maximum of DMA write BW measurements.

read results: This group contains the following columns:

live read BW (MBps): DMA read BW measurements for the current write-read-check cycle.

minimum read BW (MBps): Minimum of DMA read BW measurements.

average read BW (MBps): Average of DMA read BW measurements.

maximum read BW (MBps): Maximum of DMA read BW measurements.

`dma_result.csv` output file¶

For each test of the test_sequence, a new row containing the test configuration and results computed is present in this file. The following table summarizes the content of this file, where the following columns represent groups of columns present in the file (see description below) for a Alveo Versal Example Design (AVED) containing a memory type named DDR with the two tags DDR[0] and DDR[1] associated and containing also a memory type named HBM with the 32 tags associated HBM[0] to HBM[31]:

configuration: Group of columns for DMA write/read configuration.

write results: Group of columns for DMA write results.

read results: Group of columns for DMA read results.

Example: `dma_result.csv`¶
Test	memory tag	duration (s)	configuration	Number of cycles	Data integrity	write results	read results
1	DDR[0]	10	…	…	OK	…	…
2	DDR[1]	10	…	…	OK	…	…
3	HBM[0]	10	…	…	OK	…	…
4	HBM[1]	10	…	…	OK	…	…
…	…	…	…	…	…	…	…
34	HBM[31]	10	…	…	OK	…	…

Where:

Test: Index of current test within the test_sequence. Index of first test is 1.

memory tag: Tested memory name.

duration (s): Test duration.

configuration: This group contains the following columns:

buffer size (MB): Size of buffers transferred during the test.

number of buffers: Quantity of buffers transferred in each write-read-check cycle.

total size (MB): Total quantity of data transferred in each write-read-check cycle.

Number of cycles: Total number of write-read-check cycles performed: the number of cycles depends on test duration and quantity of data transferred.

Data integrity: Data integrity result.

write results: This group contains the following columns:

minimum write BW (MBps): Minimum of DMA write BW measurements.

average write BW (MBps): Average of DMA write BW measurements.

maximum write BW (MBps): Maximum of DMA write BW measurements.

read results: This group contains the following columns:

minimum read BW (MBps): Minimum of DMA read BW measurements.

average read BW (MBps): Average of DMA read BW measurements.

maximum read BW (MBps): Maximum of DMA read BW measurements.

DMA test case description¶

Test parameters¶

Main test steps¶

Low DMA bandwidth troubleshooting¶

DMA test JSON members¶

Definition¶

Basic examples¶

test_sequence¶

check_bw¶

stop_on_error¶

hi_thresh_wr, hi_thresh_rd¶

lo_thresh_wr, lo_thresh_rd¶

total_size¶

Output files¶

dma_detail.csv output file¶

dma_result.csv output file¶

`test_sequence`¶

`check_bw`¶

`stop_on_error`¶

`hi_thresh_wr`, `hi_thresh_rd`¶

`lo_thresh_wr`, `lo_thresh_rd`¶

`total_size`¶

`dma_detail.csv` output file¶

`dma_result.csv` output file¶