Document Revision History¶
The following table shows the revision history for this document.
|Feb 01, 2021||1.0||Genesis|
|Mar 05, 2021||1.1||Fix typos; Add FPGA flash commands; Expand CSDR response|
|Apr 01, 2021||1.2||Fix typos; Fix SMBus recap commands; Fix CSDR response|
|Apr 19, 2021||1.3||Fix typos; Edit CSDR response, Add SC flash & FPGA flash read back commands|
These documents provide supplemental material useful with this guide:
- *Intelligent Platform Management Interface FRU Specification*
- Alveo FRU Data Specification (UG1378)
- *PLDM base specification*
- *PLDM for platform monitoring and control specification*
- *SMBus 2.0 Specification*
- *MCTP SMBus/I2C Transport Binding Specification*
- Alveo U200 and U250 Data Center Accelerator Cards Data Sheet (DS962)
- Alveo U280 Data Center Accelerator Cards Data Sheet (DS963)
- Alveo U50 Data Center Accelerator Cards Data Sheet (DS965)
- MSP432P4xx SimpleLink™ Microcontrollers Bootloader (BSL)
- UltraScale Architecture Configuration User Guide (UG570)
- Zynq UltraScale+ Device Technical Reference Manual (UG1085)
For support resources such as answers, documentation, downloads, and forums, see the Alveo Accelerator Cards Xilinx Community Forum.
Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License.
You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
All images and documentation, including all debug and support documentation, are licensed under the Creative Commons (CC) Attribution 4.0 International License (the “CC-BY-4.0 License”); you may not use this file except in compliance with the CC-BY-4.0 License.
You may obtain a copy of the CC-BY-4.0 License at https://creativecommons.org/licenses/by/4.0/
Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.
XD038 | © Copyright 2021 Xilinx, Inc.