I2C/SMBus Implementation and Protocol Recap¶

Xilinx® Alveo™ cards support OoB communication via Standard I2C/SMBus commands at I2C slave address 0x65 (0xCA in 8-bit). The implementation is SMBus v2.0 Specification compliant. This chapter captures some of the frequently used SMBus commands between SC and Server BMC. Note that all the standard SMBus commands between SC and Server BMC are implemented without PEC.

NOTE: For detailed SMBus spec, refer System Management Bus Specification - version 2.0

Figure: SMBus Packet

Table: SMBus Packet diagram element Key

Key	Description
S	Start condition
Sr	Repeated start condition
R	Read (bit value of 1)
W	Write (bite value of 0)
A	ACK
N	NACK
P	Stop condition
□	Master-to-slave
■	Slave-to-master
PEC	Packet error code
…	Continuation of protocol

Figure: SMBus Commands

AMD Support

For support resources such as answers, documentation, downloads, and forums, see the Alveo Accelerator Cards AMD/Xilinx Community Forum.

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