Vitis DSP Library¶
The Vitis™ digital signal processing library (DSPLib) provides an implementation of different L1/L2/L3 primitives for digital signal processing.
The DSPLib contains PL and AI Engine solutions. For documentation on AI Engine solutions, see Introduction.
The current PL library consists of an implementation of a Discrete Fourier Transform using a Fast Fourier Transform algorithm for acceleration on Xilinx® FPGAs. The library is planned to provide three types of implementations namely L1 primitives, L2 kernels, and L3 software APIs. Those implementations are organized in their corresponding directories L1, L2, and L3.
The L1 primitives can be leveraged by developers working on harware design implementation or designing hardware kernels for acceleration. They are particularly suitable for hardware designers. The L2 kernels are HLS-based predesigned kernels that can be directly used for FPGA acceleration of different applications on integration with the Xilinx Runtime (XRT). The L3 provides software APIs in C, C++, and Python which allow software developers to offload FFT calculation to FPGAs for acceleration. Before an FPGA can perform the FFT computation, the FPGA needs to be configured with a particular image called an overlay.
Since all the kernel code is developed with the permissive Apache 2.0 license, advanced users can easily tailor, optimize, or combine them for their own needs. Demos and usage examples of different level implementations are also provided for reference.
- 1-Dimensional(Line) SSR FFT L1 FPGA Module
- Multi-Instance Support
- Data Type Support for Synthesis
- Managing Bit Growth in SSR FFT Stages
- Configurations for Fixed Point Implementation (Recommended Flow)
- 1-D SSR FFT Library Usage
- 2-Dimensional(Matrix) SSR FFT L1 FPGA Module
- Block Level Interface
- 2-D SSR FFT Architecture
- Supported Data Types
- L1 API for 2-D SSR FFT
- Library Usage
- 2-D SSR FFT Examples
- DSP Library Functions
- Compiling and Simulating Using the Makefile
- Using the Examples