1. 1-Dimensional(Line) SSR FFT L1 FPGA Module

1.1. Overview

Vitis DSP Library offers a fully synthesizable Super Sample data Rate (SSR) FFT with a systolic architecture to process multiple input samples every clock cycle. The number of samples processed in parallel per cycle is denoted by the SSR factor. The SSR FFT is implemented as a C++ template function that synthesizes into a streaming architecture. The SSR FFT architecture used for implementation can be parameterized through template parameters, which are grouped in a C++ struct of type ssr_fft_default_params. A new structure can be defined by extending the default structure and re-defining required member constants as follows:

struct ssr_fft_fix_params:ssr_fft_default_params
{
        static const int N = 1024;
        static const int R = 4;
        static const scaling_mode_enum scaling_mode = SSR_FFT_NO_SCALING;
        static const fft_output_order_enum output_data_order = SSR_FFT_NATURAL;
        static const int twiddle_table_word_length = 18;
        static const int twiddle_table_integer_part_length = 2;
        static const transform_direction_enum transform_direction = FORWARD_TRANSFORM;
        static const butterfly_rnd_mode_enum butterfly_rnd_mode = TRN;
};

The structure above defines:

  • N: Size or length of transform
  • R: The number of samples to be processed in parallel SSR Factor and radix of SSR FFT algorithm used
  • scaling_mode: The scaling mode as enumeration type (SSR FFT has three different scaling modes)
  • output_data_order: Which will decided if data will be in natural order or digit reversed transposed order
  • twiddle_table_word_length: Defines total number of bits to be used for storing twiddle table factors
  • twiddle_table_integer_part_length: The number of integer bits used for storing integer part of twiddles
  • transform_direction : Defines the direction of transform, inverse transform (SSR IFFT) or forward transform (SSR FFT)
  • butterfly_rnd_mode : Defines the rounding mode used by butterflies in SSR FFT stages

1.2. Multi-Instance Support

Single-instance example:

xf::dsp::fft::fft<fftParams><ssr_fft_fix_params>(...);

The current release of Vitis SSR FFT supports the use of multiple instances of 1-D SSR FFT in a single design. To enable the use of multiple instances, the fft function takes as an input a new template parameter besides the parameter structure. This parameter gets a default value if no value is provided for it. But if multiple instance support is required, all the instances used should be provided with the unique integer template parameter, like:

xf::dsp::fft::fft<fftParams,1><ssr_fft_fix_params>(...);
xf::dsp::fft::fft<fftParams,2><ssr_fft_fix_params>(...);

1.3. Data Type Support for Synthesis

Currently 1-D SSR FFT supports fixed point and floating point complex inputs for synthesis.

1.3.1. Fixed Point

The fixed point SSR FFT implementation is based on fixed point data types std::complex<ap_fixed<>> which are used for synthesis and implementation. It is possible to use floating point types std::complex<float> and std::complex<double> for simulation but these floating point complex models will consume massive resources if synthesized to hardware. For the best results with fixed point type, limit the data bit width to 27 bits (integer + fraction) as it helps to map multiplication and addition within SSR FFT butterflies directly onto a single DSP block. Larger inputs can be used but may lead to slower Fmax and more resource utilization. Finally, note that the complex exponential/twiddle factor storage is on 18 bits (16F+2I bits). The selection of 18-bit is made keeping in view the 18x27 multipliers available within DSP blocks on Xilinx FPGAs.

1.3.2. Floating Point

1-D SSR FFT also supports synthesis for single or double precision floating point type. For synthesizing a complex floating point type, it is required that std::complex type not to be used as a complex wrapper. Since this wrapper has some issues and it is required that a wrapper class provided with the Vitis DSP library called complex_wrapper<…> is used for wrapping complex float numbers. Also while synthesizing floating point 1-D SSR FFT the parameters in the structure which carry information such as scaling mode, twiddle factor storage bits, butterfly rounding mode etc. which are only related to fixed point data-path, carry no meaning. Instead SSR FFT parameter structure can simply define relevant parameters as shown below:

struct ssr_fft_fix_params:ssr_fft_default_params
{
        static const int N = 1024;
        static const int R = 4;
        static const fft_output_order_enum output_data_order = SSR_FFT_NATURAL;
        static const transform_direction_enum transform_direction = FORWARD_TRANSFORM;
};

1.4. Managing Bit Growth in SSR FFT Stages

The bit growth management is required for fixed point implementation only. The SSR FFT supports three different modes to manage bit growth between SSR FFT stages. These three modes can be used to allow bit growth in every stage, or use scaling in every stage without any bit growth, or allow bit growth until 27 bits and then start using scaling. The detailed description for the different modes are as follows:

1.4.1. SSR_FFT_GROW_TO_MAX_WIDTH

When the scaling_mode constant in the parameter structure is set to SSR_FFT_GROW_TO_MAX_WIDTH, it specifies growth from stage to stage, starting from the first stage to a specified max bit width. The output bit width grows until 27 bits and then saturates. The output bit width grows by log2(R) bits in every stage, and then maxes outs at 27 bits to keep the butterfly operation mapping to DSPs. This option is useful when the initial input bit width is less than 27 bits.

1.4.2. SSR_FFT_SCALE

When the scaling_mode constant in the parameter structure is set to SSR_FFT_SCALE, it enables scaling of outputs in every stage. The output is scaled in every stage and loses precision. An FFT with size L and Radix=SSR=R has logR(L) stages. This option is useful when the input bit width is already close to 27 bits and it is required that the output does not grow beyond 27 bits so that multiplication can be mapped to DSPs.

1.4.3. SSR_FFT_NO_SCALE

When the scaling_mode constant in the parameter structure is set to SSR_FFT_NO_SCALE, the bit growth is allowed in every stage and the output grows unbounded by log2(R) in every stage. This setting can be useful when high precision is required. However, if the output bit width grows beyond 27 bits, the multiplication may not map to only DSPs, but also start using FPGA fabric logic in combination. This may reduce the clock speed and increase resource utilization.

1.6. 1-D SSR FFT Library Usage

Following sections describe how to use SSR FFT from Vitis DSP Library.

1.6.1. Fixed Point 1-D SSR FFT Usage

The Vitis 1-D SSR FFT L1 module can be used in a C++ HLS design by: 1- cloning the Vitis DSP Library git repository and add the following path to compiler include path:

REPO_PATH/dsp/L1/include/hw/vitis_fft/fixed/

2- Include vt_fft.hpp

3- Use namespace xf::dsp::fft

4- Define fft parameter structure say call it params_fix by extending ssr_fft_default_params like Defining 1-D SSR FFT Parameter Structure

5- call fft<params_fix>(input_stream,output_stream)

The following section gives usage examples and explains some other interface level details for use in C++ based HLS design. To use the 1-D SSR FFT L1 module:

  1. Include the vt_fft.hpp header:
#include "vt_fft.hpp"
  1. Use namespace xf::dsp::fft
using namespace xf::dsp::fft;
  1. Define a C++ structure that extends ssr_fft_default_params:
struct params_fix:ssr_fft_default_params
{
        static const int N-SSR_FFT_L;
        static const int R=SSR_FFT_R;
        static const scaling_mode_enum
        scaling_mode=SSR_FFT_GROW_TO_MAX_WIDTH;
        static const fft_output_order_enum
        output_data_order=SSR_FFT_NATURAL;
        static const int twiddle_table_word_length=18;
        static const int twiddle_table_intger_part_length=2;
};
  1. Call 1-D SSR FFT as follows:
fft<params_fix>(inD,outD);
//OR
fft<params_fix,IID>(inD,outD);
// IID: is a constant giving instance ID

where inD and outD are 1-dimensional hls::stream of complex of ap_fixed, float or double type, synthesis and simulation use is already explained in the previous table. The I/O arrays can be declared as follows:

Fixed Point Type First define input type, then using type traits calculate output type based on ssr_fft_params struct (output type calculation takes in consideration scaling mode based bit-growth and input bit-widths).

1.6.2. Floating Point 1-D SSR FFT Usage

The Vitis 1-D SSR FFT L1 module can be used in a C++ HLS design by:

1- Cloning the Vitis DSP Library git repository and add the following path to compiler include path:

REPO_PATH/dsp/L1/include/hw/vitis_fft/float/

2- Include vt_fft.hpp

3- Use namespace xf::dsp::fft

4- Define fft parameter structure lets say call it params_float by extending ssr_fft_default_params like Defining 1-D SSR FFT Parameter Structure

5- call fft<params_float>(input_stream,output_stream)

The following section gives usage examples and explains some other interface level details for use in C++ based HLS design. To use the 1-D SSR FFT L1 module:

  1. Include the vt_fft.hpp header:
#include "vt_fft.hpp"
  1. Use namespace xf::dsp::fft
using namespace xf::dsp::fft;
  1. Define a C++ structure that extends ssr_fft_default_params:
struct params_float:ssr_fft_default_params
{
   static const int N = 1024;
   static const int R = 4;
   static const fft_output_order_enum output_data_order = SSR_FFT_NATURAL;
   static const transform_direction_enum transform_direction = FORWARD_TRANSFORM;
};
  1. Call 1-D SSR FFT as follows:
fft<params_float>(inD,outD);
//OR
fft<ssr_fft_params,IID>(inD,outD);
// IID: is a constant giving instance ID

where inD and outD are 1-dimensional hls::stream complex of ap_fixed, float or double type, synthesis and simulation use is already explained in the previous table. The I/O arrays can be declared as follows:

Fixed Point Type: First define input type, then using type traits calculate output type based on ssr_fft_params struct (output type calculation takes into consideration scaling mode based bit-growth and input bit-widths not relevant for type float).

typedef std::complex< float > I_TYPE;
typedef xf::dsp::fft::ssr_fft_output_type<ssr_fft_params,I_TYPE>::t_ssr_fft_out O_TYPE;
I_TYPE inD[SSR_FFT_R][SSR_FFT_L/SSR_FFT_R];
O_TYPE outD [R][L/R];

Here SSR_FFT_R defines SSR factor and SSR_FFT_L defines the size of the FFT transform.

Float/Double Type: First define the double/float input type, then using type traits calculate output type based on ssr_fft_params struct. For float types the output type calculation will return the same type as input.

typedef std::complex< float/double > I_TYPE;
typedef hls::ssr_fft::ssr_fft_output_type<ssr_fft_params,I_TYPE>::t_ssr_fft_out O_TYPE;
I_TYPE inD[SSR_FFT_R][SSR_FFT_L/SSR_FFT_R];
O_TYPE outD[SSR_FFT_R][SSR_FFT_L/SSR_FFT_R];

1.6.3. 1-D SSR FFT Input Stream Reading and Writing Considerations

After synthesis, 1-D SSR FFT HLS IP maps to a processing block with stream interface at both the input and output.

If user requires a streaming 1-D SSR FFT block with FIFO interface at both the input and output, as shown in the following figure:

doc tool flow
  1. Declares the input and output streams explicitly with corresponding stream depth:
// input stream of innerFFT
hls::stream<I_TYPE, FIFO_DEPTH> inStrm[R];
// output stream of innerFFT
hls::stream<O_TYPE, FIFO_DEPTH> outStrm[R];
  1. Feeds data to the input FIFO, or eats from the output one:
for (int t = 0; t < L / R; t++)
{
        for (int r = 0; r < R; r++)
        {
    inStrm[r].write(inD[r][t]);
        }
}

for (int t = 0; t < L / R; t++)
{
        for (int r = 0; r < R; r++)
        {
    outD[r][t] = outStrm[r].read();
        }
}

3. If the 1-D SSR FFT IP is facing another HLS IP in the input chain or output chain, the inner loop doing reading and writing should be unrolled.

1.6.4. 1-D SSR FFT Usage in Dataflow Region Streaming

1-D SSR FFT internally relies heavily on HLS dataflow optimization. The potential use case for 1-D SSR FFT could interconnect with an SSR FFT input or output in two ways:

1.6.4.1. Streaming Connection

The current version of the 1-D SSR FFT naturally support streaming connection at the output and input.

// just call it
fft<params_float>(inD, outD);
//OR
fft<ssr_fft_params, IID>(inD, outD);
// IID: is a constant giving instance ID

1.6.5. 1-D SSR FFT Tests

Different tests are provided for fixed point and floating point 1-D SSR FFT. These tests can be ran individually using the makefile or they can all be lauched at the same time by using a provided script. All the 1-D SSR FFT tests are in folder REPO_PATH/dsp/L1/tests/hw/1dfft

1.6.5.1. Launching an Individual Test

To launch an individual test first it is required to setup environment for lanching Vitis HLS Compiler which can be done as follows:
setup of environment variable TA_PATH to point to the installation path of your Vitis, and run following commands to set up the environment.
export XILINX_VITIS=${TA_PATH}/Vitis/2021.1
export XILINX_VIVADO=${TA_PATH}/Vivado/2021.1
source ${XILINX_VIVADO}/settings64.sh

Once the environment settings are done an individual test can be launched by going to test folder (any folder inside sub-directory at any level of REPO_PATH/dsp/L1/test/hw/1dfft that has a Makefile is a test) and running the make command :

make run XPART='xcu200-fsgd2104-2-e' CSIM=1 CSYNTH=1 COSIM=1 you can choose the part number as required and by settting CSIM/CSYNTH/COSIM=0 choose what to build and run with make target