Vitis DSP Library

The Vitis™ digital signal processing library (DSPLib) provides an implementation of different L1/L2/L3 elements for digital signal processing.

The DSPLib contains:

• PL DSP library.
• AI Engine DSP library.

PL DSP library

The current PL (Programmable Logic) library consists of an implementation of a Discrete Fourier Transform using a Fast Fourier Transform (FFT) algorithm for acceleration on Xilinx® FPGAs. The library is planned to provide three types of implementations, namely L1 PL primitives, L2 PL kernels, and L3 software APIs. Those implementations are organized in hardware (hw) sub-directories of the corresponding L1, L2, and L3.

The L1 PL primitives can be leveraged by developers working on harware design implementation or designing hardware kernels for acceleration. They are particularly suitable for hardware designers. The L2 PL kernels are HLS-based predesigned kernels that can be directly used for FPGA acceleration of different applications on integration with the Xilinx Runtime (XRT). The L3 provides software APIs in C, C++, and Python which allow software developers to offload FFT calculation to FPGAs for acceleration. Before an FPGA can perform the FFT computation, the FPGA needs to be configured with a particular image called an overlay.

Vitis™ PL DSP Library provides a fully synthesizable PL based Super Sample data Rate (SSR) FFT, as well as a 2-Dimensional FFT version. For detailed documentation, plese refer to: 1-Dimensional(Line) SSR FFT L1 FPGA Module and 2-Dimensional(Matrix) SSR FFT L1 FPGA Module.

AI Engine DSP library

AIE DSP library consists of designs of various DSP algorithms, optimized to take full advantage of the processing power of the Xilinx® Versal® Adaptive Computing Acceleration Platform (ACAP) devices, which contain an array of Xilinx® AI Engines - high-performance vector processors.

The library is organized into three types of AIE designs, namely:

• L1 AIE kernels,
• L2 AIE graphs, and
• L3 software APIs.

Please refer to Introduction for more information.

Vitis™ AIE DSP Library provides a SSR FFT implementation targeting AIE, as well as various SSR Finite Impulse Response (FIR) filters, SSR Direct Digital Synthesis (DDS), General Matrix Multiply (GeMM) impementation. For a full list of available DSP functions, please refer to DSP Library Functions.

Library Overview

• Requirements
  • Software Platform
  • PCIE Accelerator Card
• License
• Trademark Notice
• Release Note
  • 2022.1
  • 2021.2
  • 2021.1
  • 2020.2
  • 2020.1

L1 PL DSP Library User Guide

• 1. 1-Dimensional(Line) SSR FFT L1 FPGA Module
  • 1.1. Overview
  • 1.2. Multi-Instance Support
  • 1.3. Data Type Support for Synthesis
    • 1.3.1. Fixed Point
    • 1.3.2. Floating Point
  • 1.4. Managing Bit Growth in SSR FFT Stages
    • 1.4.1. SSR_FFT_GROW_TO_MAX_WIDTH
    • 1.4.2. SSR_FFT_SCALE
    • 1.4.3. SSR_FFT_NO_SCALE
  • 1.5. Configurations for Fixed Point Implementation (Recommended Flow)
    • 1.5.1. Start With Floating Point Model
    • 1.5.2. Fixed Point Modeling and Implementation
      • 1.5.2.1. Fixed Point Model
      • 1.5.2.2. Selecting Bit Widths for Inputs
      • 1.5.2.3. Twiddle Factor or Sine/Cosine Lookup Table Quantization
      • 1.5.2.4. Choosing the Best Scaling Mode
      • 1.5.2.5. SSR_FFT_NO_SCALING
      • 1.5.2.6. SSR_FFT_GROW_TO_MAX_WIDTH
      • 1.5.2.7. SSR_FFT_SCALE
  • 1.6. 1-D SSR FFT Library Usage
    • 1.6.1. Fixed Point 1-D SSR FFT Usage
    • 1.6.2. Floating Point 1-D SSR FFT Usage
    • 1.6.3. 1-D SSR FFT Input Stream Reading and Writing Considerations
    • 1.6.4. 1-D SSR FFT Usage in Dataflow Region Streaming
      • 1.6.4.1. Streaming Connection
    • 1.6.5. 1-D SSR FFT Tests
      • 1.6.5.1. Launching an Individual Test
• 2. 2-Dimensional(Matrix) SSR FFT L1 FPGA Module
  • 2.1. Overview
  • 2.2. Block Level Interface
  • 2.3. 2-D SSR FFT Architecture
  • 2.4. Supported Data Types
  • 2.5. L1 API for 2-D SSR FFT
    • 2.5.1. Template Parameters
    • 2.5.2. Constraints on the Choice of Template Parameters
  • 2.6. Library Usage
    • 2.6.1. Fixed Point 2-D SSR FFT L1 Module Usage
    • 2.6.2. Floating Point 2-D SSR FFT L1 Module Usage
  • 2.7. 2-D SSR FFT Examples
    • 2.7.1. 2-D Fixed Point Example
      • 2.7.1.1. Top Level Definition and main Function
      • 2.7.1.2. Compiling and Building Example HLS Project
    • 2.7.2. 2-D Floating Point Example
      • 2.7.2.1. Top Level Definition and main Function
      • 2.7.2.2. Compiling and Building Example HLS Project
    • 2.7.3. 2-D SSR FFT Tests
      • 2.7.3.1. Launching an Individual Test

L2 DSP Library User Guide

• 1. Introduction
  • 1.1. Navigating Content by Design Process
  • 1.2. Organization
  • 1.3. Using Library Elements within User Defined Graphs
  • 1.4. Known Issues
  • 1.5. Vitis Tutorials
• 2. DSP Library Functions
  • 2.1. Filters
    • 2.1.1. Entry Point
    • 2.1.2. Supported Types
    • 2.1.3. Template Parameters
    • 2.1.4. Access functions
    • 2.1.5. Ports
    • 2.1.6. Design Notes
      • 2.1.6.1. Coefficient array for Filters
      • 2.1.6.2. Window interface for Filters
      • 2.1.6.3. Streaming interface for Filters
      • 2.1.6.4. Maximum FIR Length
      • 2.1.6.5. Minimum Cascade Length
      • 2.1.6.6. Optimum Cascade Length
      • 2.1.6.7. Super Sample Rate Operation
      • 2.1.6.8. Constraints
    • 2.1.7. Code Example including constraints
  • 2.2. FFT/iFFT
    • 2.2.1. Entry Point
    • 2.2.2. Supported Types
    • 2.2.3. Template Parameters
    • 2.2.4. Access functions
    • 2.2.5. Ports
    • 2.2.6. Design Notes
      • 2.2.6.1. Dynamic Point Size
      • 2.2.6.2. Super Sample Rate Operation
      • 2.2.6.3. Scaling
      • 2.2.6.4. Saturation
      • 2.2.6.5. Constraints
    • 2.2.7. Code Example including constraints
  • 2.3. Matrix Multiply
    • 2.3.1. Entry Point
    • 2.3.2. Supported Types
    • 2.3.3. Template Parameters
    • 2.3.4. Access functions
    • 2.3.5. Ports
    • 2.3.6. Design Notes
      • 2.3.6.1. Tiling
      • 2.3.6.2. Constraints
    • 2.3.7. Code Example including constraints
  • 2.4. Widget API Cast
    • 2.4.1. Entry Point
    • 2.4.2. Supported Types
    • 2.4.3. Template Parameters
    • 2.4.4. Access functions
    • 2.4.5. Ports
    • 2.4.6. Design Notes
    • 2.4.7. Code Example including constraints
  • 2.5. Widget Real to Complex
    • 2.5.1. Entry Point
    • 2.5.2. Supported Types
    • 2.5.3. Template Parameters
    • 2.5.4. Access functions
    • 2.5.5. Ports
    • 2.5.6. Design Notes
    • 2.5.7. Code Example including constraints
  • 2.6. DDS / Mixer
    • 2.6.1. Entry Point
    • 2.6.2. Supported Types
    • 2.6.3. Template Parameters
    • 2.6.4. Access functions
    • 2.6.5. Ports
    • 2.6.6. Design Notes
      • 2.6.6.1. Scaling
      • 2.6.6.2. Super Sample Rate Operation
    • 2.6.7. Code Example including constraints
• 3. Compiling and Simulating Using the Makefile
  • 3.1. L2 Library Element Unit Test
  • 3.2. L2 Library Element Configuration Parameters
    • 3.2.1. L2 FIR configuration parameters
    • 3.2.2. L2 FFT configuration parameters
    • 3.2.3. L2 Matrix Multiply Configuration Parameters
    • 3.2.4. L2 Widgets Configuration Parameters
    • 3.2.5. L2 DDS/Mixer Configuration Parameters
• 4. Benchmark/QoR
  • 4.1. Filters
  • 4.2. FFT
  • 4.3. Matrix Multiply
  • 4.4. Widgets
  • 4.5. DDS/Mixer