Vitis DSP Library

The Vitis™ digital signal processing library (DSPLib) provides an implementation of different L1/L2/L3 elements for digital signal processing.

The DSPLib contains:

PL DSP library

The current PL (Programmable Logic) library consists of an implementation of a Discrete Fourier Transform using a Fast Fourier Transform (FFT) algorithm for acceleration on Xilinx® FPGAs. The library is planned to provide three types of implementations, namely L1 PL primitives, L2 PL kernels, and L3 software APIs. Those implementations are organized in hardware (hw) sub-directories of the corresponding L1, L2, and L3.

The L1 PL primitives can be leveraged by developers working on harware design implementation or designing hardware kernels for acceleration. They are particularly suitable for hardware designers. The L2 PL kernels are HLS-based predesigned kernels that can be directly used for FPGA acceleration of different applications on integration with the Xilinx Runtime (XRT). The L3 provides software APIs in C, C++, and Python which allow software developers to offload FFT calculation to FPGAs for acceleration. Before an FPGA can perform the FFT computation, the FPGA needs to be configured with a particular image called an overlay.

Vitis™ PL DSP Library provides a fully synthesizable PL based Super Sample data Rate (SSR) FFT, as well as a 2-Dimensional FFT version. For detailed documentation, plese refer to: 1-Dimensional(Line) SSR FFT L1 FPGA Module and 2-Dimensional(Matrix) SSR FFT L1 FPGA Module.

AI Engine DSP library

AIE DSP library consists of designs of various DSP algorithms, optimized to take full advantage of the processing power of the Xilinx® Versal® Adaptive Computing Acceleration Platform (ACAP) devices, which contain an array of Xilinx® AI Engines - high-performance vector processors.

The library is organized into three types of AIE designs, namely:

  • L1 AIE kernels,
  • L2 AIE graphs, and
  • L3 software APIs.

Please refer to Introduction for more information.

Vitis™ AIE DSP Library provides a SSR FFT implementation targeting AIE, as well as various SSR Finite Impulse Response (FIR) filters, SSR Direct Digital Synthesis (DDS), General Matrix Multiply (GeMM) impementation. For a full list of available DSP functions, please refer to DSP Library Functions.

L1 PL DSP Library User Guide

L2 DSP Library User Guide