AMR RAVE - Expansion I/O

This feature is RAVE-specific.

The expansion connector enables application-specific daughtercards.

Overview

Note: Image shows 160-pin Samtec connector, GTYP Bank 104 routing, daughtercard ecosystem.

The RAVE Boards include a 160-pin Samtec SEAM/SEAF expansion connector providing access to:

  • GT transceivers (GTYP Bank 104)

  • High-speed I/O (XPIO)

  • High-density I/O (HDIO)

  • Power and ground

This enables a daughtercard ecosystem for application-specific interfaces (networking, cameras, custom I/O).

Samtec Expansion Connector

The 160-pin expansion connector provides access to:

Signal Type Resources
GTYP Lanes 4 lanes from Bank 104
XPIO/HDIO General purpose and high-density I/O
Reference Clocks Differential clock pairs
Power VCC, GND

Note: For connector specifications and pinout details, refer to the hardware design repository and Sapphire RAVE1 EDGE+.

GTYP Bank 104 (Expansion GT)

GT Transceiver Allocation

Bank 103: Used for PCIe (x4 lanes to Ryzen)

Bank 104: Available for expansion via Samtec connector

GT Lane TX Pins RX Pins Availability
Lane 0 TXP0, TXN0 RXP0, RXN0 ✓ Expansion
Lane 1 TXP1, TXN1 RXP1, RXN1 ✓ Expansion
Lane 2 TXP2, TXN2 RXP2, RXN2 ✓ Expansion
Lane 3 TXP3, TXN3 RXP3, RXN3 ✓ Expansion

Reference Clocks:

  • REFP0/REFN0 - Expansion reference clock 0

  • REFP1/REFN1 - Expansion reference clock 1

  • RREF - GT reference

  • AVTTRCAL - GT calibration

GT Protocols Supported

Bank 104 can support:

  • 10G/25G Ethernet (via MRMAC or 10G MAC)

  • PCIe (additional lanes)

  • Custom high-speed protocols

  • GMSL (via protocol conversion)

  • Aurora

  • JESD204

  • Other GT-based protocols

Daughtercard Ecosystem

RAVE supports multiple daughtercards for different applications:

Available Daughtercards

RAVE supports multiple daughtercard options for different applications:

Ethernet Cards:

  • 1G Ethernet (XPIO/HDIO based)

  • 10G/25G Ethernet (GT-based with SFP+)

Camera Cards:

  • GMSL camera interfaces for vision applications

Use Cases:

  • Networking and data transfer

  • Automotive vision systems

  • Industrial inspection

  • Multi-camera applications

Note: For daughtercard part numbers, schematics, and specifications, refer to the hardware design repository.

Custom Daughtercards

160-pin connector enables custom interfaces:

Available Resources:

  • 4× GT lanes (Bank 104) - up to 25 Gbps each

  • XPIO pins - General purpose I/O

  • HDIO pins - High-density I/O

  • Reference clocks

  • Power rails

Example Custom Applications:

  • CAN/CAN-FD interfaces (automotive)

  • Industrial protocols (EtherCAT, PROFINET)

  • Additional storage interfaces

  • Sensor interfaces (radar, lidar)

  • Custom high-speed serial

Design Considerations for Daughtercards

FPGA Design Requirements

To use daughtercard:

  1. Instantiate appropriate IP:

    • Ethernet: MRMAC, 10G MAC, 1G MAC

    • GMSL: ISP pipeline, video processing

    • Custom: Protocol-specific IP

  2. Configure GT transceivers:

    • Set line rate (1.25G, 10G, 25G)

    • Configure reference clock source

    • Set GT location (Bank 104)

  3. Add to block design:

    • Connect to NoC for memory access

    • Wire interrupts if needed

    • Provide clocks and resets

  4. Update constraints:

    • Pin LOC constraints for GTYP

    • XPIO / HDIO pin assignments

    • Timing constraints

DFX (Dynamic Function eXchange)

RAVE supports DFX for daughtercard flexibility:

Base Logic Platform (BLP):

  • Fixed: CIPS, NoC, PCIe, XDMA, memory

  • Provides isolation interface to reconfigurable region

User Logic Platform (ULP):

  • Daughtercard-specific IP

  • Multiple PDI configurations for different cards

Example PDI Programming:

# Load 1G Ethernet configuration
ami_tool pdi_program -i ethernet_1g.pdi

I/O Bank Details

GTYP Banks

Bank Usage Lanes Speed
103 PCIe to Ryzen 4× Gen3 (8 GT/s)
104 Expansion 4× Up to 25 GT/s

XPIO / HDIO Banks

Additional I/O available on expansion connector:

  • XPIO: Extended programmable I/O

  • HDIO: High-density I/O

  • Mixed voltage support

  • Configurable I/O standards

See: VE2302 pinout and I/O planning guide for details.

Reference Designs

Available RAVE Vivado boards

From: https://github.com/Xilinx/amr_vivado_designs.git

board Daughtercard Description
ve2302_1gEth 1G Ethernet Dual 1G Ethernet channels
ve2302_10g_mrmac 10G/25G Ethernet Dual 10G using MRMAC
ve2302_gmsl GMSL Camera GMSL video pipeline
ve2302_xdma_gmsl GMSL Camera GMSL with XDMA/PCIe
ve2302_xdma_base None (DFX base) DFX-capable base platform

DFX Reconfigurable Modules

Swappable modules for ve2302_xdma_base:

  • bram_gpio - BRAM + GPIO test

  • eth_1g - 1G Ethernet

  • eth_10g - 10G Ethernet with MRMAC

  • training - Reference training module

Expansion Connector Pinout

High-Level Pin Groups

Pin Group Approximate Count Purpose
GTYP TX[0-3] 8 (differential) GT transmit lanes
GTYP RX[0-3] 8 (differential) GT receive lanes
GT REF CLK 4 (differential) Reference clocks
XPIO 20-40+ General purpose I/O
HDIO 20-40+ High-density I/O
Power 20-40 VCC, GND rails
Control 4-8 I2C, enables, status

See: RAVE hardware schematics for exact pinout.

Mechanical Considerations

Daughtercard Form Factor

Mechanical constraints:

  • Mating height with Samtec connector

  • Clearance for Mini-ITX chassis

  • Thermal considerations (airflow, heatsinks)

  • Connector retention and locking

Reference Daughtercard Designs

Sapphire-provided schematics:

  • Ethernet cards: 7D778 (1G), 7D780 (10G/25G)

  • GMSL card: 7D779 v1.1

  • Can be used as templates for custom designs

Power Budget for Daughtercards

Available Power

Power provided via expansion connector:

  • VCC rails (TBD voltages)

  • Current limit: TBD

  • Total power budget: TBD

Thermal Considerations:

  • VE2302 power consumption

  • Daughtercard power consumption

  • Mini-ITX chassis cooling

  • Total system power limit

| Expansion Connector | ✓ 160-pin Samtec | ❌ None | | GT Expansion | ✓ Bank 104 (4 lanes) | ❌ None | | Daughtercards | ✓ Ecosystem | ❌ N/A | | DFX Support | ✓ Yes (for daughtercards) | Planned | | I/O Flexibility | ✓ High (application-specific) | Fixed (PCIe only) | | Custom Interfaces | ✓ Via daughtercards | ❌ N/A |

Daughtercard Development Flow

Creating Custom Daughtercard

Steps:

  1. Define Requirements:

    • Interface protocols needed

    • I/O count and types

    • GT lane count and speed

    • Power requirements

  2. Design Hardware:

    • Use reference schematics as templates

    • Interface to 160-pin Samtec

    • Follow RAVE signal assignments

    • Thermal and mechanical design

  3. Develop FPGA Design:

    • Create IP integrator design or HDL

    • Configure GT transceivers (Bank 104)

    • Assign XPIO/HDIO pins

    • Connect to NoC for memory access

    • Add interrupts if needed

  4. Create Partial PDI (if DFX):

    • Define reconfigurable partition

    • Build partial bitstream

    • Package as deployable PDI

  5. Test and Validate:

    • Hardware bring-up

    • Protocol compliance

    • Performance testing

    • Thermal testing

Software Support for Daughtercards

Driver Integration

Each daughtercard may need:

  • Linux device driver (for APU Linux)

  • Firmware support (for RPU firmware)

  • User-space libraries

  • XRT kernel (for Vitis workflow)

PDI Programming Support

For daughtercard configurations:

  • AMI PDI programming commands

  • Partition management

  • Daughtercard detection/identification

Application Examples

Industrial Vision

GMSL Daughtercard + Vision Processing:

  • 4× GMSL cameras

  • Real-time ISP pipeline

  • AI inference on frames

  • H.264/H.265 encoding

  • Network output (Ethernet card)

Automotive ADAS

Multi-sensor Fusion:

  • GMSL cameras (surround view)

  • Radar data (custom daughtercard)

  • Lidar data (custom daughtercard)

  • CAN/CAN-FD (custom daughtercard)

  • Sensor fusion in Versal AIE

High-Speed Networking

10G/25G Ethernet:

  • Dual SFP+ ports

  • Network processing in PL

  • Packet inspection/filtering

  • Traffic generation/analysis

Edge AI Gateway

Connectivity Hub:

  • Ethernet for network

  • GMSL for cameras

  • USB for peripherals

  • Process data locally

  • Cloud upload (Ethernet)

Design Constraints for Expansion I/O

XDC Pin Constraints

Example for GTYP Bank 104:

# GTYP Bank 104 - Expansion GT lanes
set_property PACKAGE_PIN <pin> [get_ports {exp_gtyp_txp[0]}]
set_property PACKAGE_PIN <pin> [get_ports {exp_gtyp_txn[0]}]
set_property PACKAGE_PIN <pin> [get_ports {exp_gtyp_rxp[0]}]
set_property PACKAGE_PIN <pin> [get_ports {exp_gtyp_rxn[0]}]
# ... (lanes 1-3)

# Reference clocks
set_property PACKAGE_PIN <pin> [get_ports exp_refclk0_p]
set_property PACKAGE_PIN <pin> [get_ports exp_refclk0_n]

See: RAVE Board XDC files for complete pin assignments.

Limitations and Considerations

Resource Sharing

Constraints when using expansion I/O:

  • GT Bank 104 shared with expansion (4 lanes available)

  • XPIO/HDIO pins limited by VE2302 package

  • NoC bandwidth shared with PCIe/memory

  • PL resources shared with PCIe/XDMA IP

Thermal Constraints

Heat dissipation:

  • VE2302 + daughtercard in enclosed space

  • Mini-ITX chassis cooling

  • Active cooling may be required for high-power cards

  • Monitor junction temperature

Electrical Considerations

Signal integrity:

  • High-speed GT signals require proper PCB design

  • Impedance control on daughtercard

  • Differential pair routing

  • Reference clock quality

Future Daughtercard Roadmap

Potential future daughtercards:

  • CAN/CAN-FD for automotive

  • Additional camera interfaces

  • Storage interfaces (SATA, NVMe)

  • Industrial protocols (EtherCAT, PROFINET)

  • 5G/wireless interfaces

  • Sensor aggregation cards

References