AMR RAVE - XDMA Configuration

For common DMA concepts, see Common Hardware Documentation

This document describes the RAVE (VE2302) XDMA PL IP implementation.

Overview

The RAVE Board uses the XDMA PL IP (xilinx.com:ip:xdma) for DMA functionality. The VE2302 device is a Versal Edge-series device that does not include a CPM block, so DMA must be implemented in soft logic within the programmable fabric.

XDMA provides a channel-based DMA architecture supporting 2 physical functions (PF0 for management with device ID 0x5710, PF1 for user/DMA with device ID 0x5711). The IP supports multiple DMA channels with memory-mapped and streaming interfaces for efficient data transfer between host and device memory.

Note: Legacy RAVE designs used QDMA (Queue DMA) with 512 queues. The platform has migrated to XDMA for improved simplicity and compatibility with VE2302 Embedded+ platform requirements.

XDMA PL IP

IP Information

Parameter Value
IP Name XDMA
Vendor xilinx.com:ip:xdma
Version Latest for Vivado 2026.1
Implementation Soft logic in PL fabric
Physical Functions 2 (PF0: 0x5710, PF1: 0x5711)

Reference: XDMA Product Guide (PG195)

RAVE XDMA Configuration

XDMA Settings

Setting RAVE Value Notes
Physical Functions 2 (PF0, PF1) Standard AMR configuration
PF0 Device ID 0x5710 Management function
PF1 Device ID 0x5711 User/DMA function
Vendor ID 0x10EE Xilinx vendor ID
Mode Selection Advanced Multi-PF support
Function Level Reset Disabled In both XDMA & PCIe IP
Data Width 256-bit AXI data width

Physical Function Configuration

PF0 (Management)

XDMA PF0 Settings:

  • Device ID: 0x5710

  • Base Class: 12 (Memory controller)

  • Sub Class: 00

  • BAR0: 8 MB (64-bit, non-prefetchable)

PF1 (User/DMA)

XDMA PF1 Settings:

  • Device ID: 0x5711

  • Base Class: 12 (Memory controller)

  • Sub Class: 00

  • BAR0: 16 MB (64-bit, non-prefetchable) - XDMA control registers

  • BAR2: 64 KB (64-bit, non-prefetchable) - AXI-Lite bridge for PL peripherals

  • BAR4: 256 MB (64-bit, prefetchable) - AXI bypass interface for memory access

  • MSI-X: Enabled

AXI Interfaces

XDMA AXI Master (H2C - Host to Card)

For DMA data transfer:

Interface Configuration
M_AXI AXI4-MM master interface
Data Width 256-bit
Connection To NoC (via SmartConnect)
Target LPDDR4 memory, PL slaves

XDMA AXI-Lite Master

For register access:

Interface Configuration
M_AXI_LITE AXI4-Lite master interface
Size 16 MB address space
Prefetchable False
Purpose PL peripheral access via PF1 BAR2

XDMA AXI Bypass

For memory-mapped access:

Interface Configuration
M_AXI_BYPASS AXI4-MM bypass interface
Size 256 MB address space
Prefetchable True
Purpose Direct memory access via PF1 BAR4
64-bit addressing Enabled

NoC Integration

XDMA to NoC Connection

XDMA routes through SmartConnect to NoC:

XDMA PL IP M_AXI (256-bit)
  ↓
SmartConnect (width/protocol conversion)
  ↓
NMU (in AXI NoC IP)
  ↓
NoC Interconnect
  ↓
DDRMC_NSU → LPDDR4

Configuration:

  • SmartConnect provides width conversion and protocol adaptation

  • Custom axi_addr_mask IP applies address masks for BAR-to-AXI translation

  • NoC handles routing to LPDDR4 memory controllers

  • Clock domain crossing handled by SmartConnect and NoC

Address Translation

Address Masking

RAVE uses custom axi_addr_mask IP for BAR address translation:

Interface Mask Purpose
AXI-Lite 0x0000000000FFFFFF Translates PF1 BAR2 to local peripheral addresses
AXI Bypass 0x000000000FFFFFFF Translates PF1 BAR4 to LPDDR4 addresses

Clocking and Resets

XDMA Clock Domains

Clock Source Purpose
axi_aclk PCIe user clock XDMA AXI interfaces
axi_ctl_aclk PCIe user clock XDMA control interface

XDMA Reset Inputs

Reset Source Purpose
sys_rst_n PCIe reset logic System reset
axi_aresetn proc_sys_reset AXI interface reset

Reset Synchronization:

  • Use proc_sys_reset blocks for proper clock domain synchronization

  • Coordinate PCIe reset with XDMA reset sequencing

Design Integration

Key Configuration Parameters

From RAVE config_bd.tcl:

# XDMA IP configuration
CONFIG.PF1_SUBSYSTEM_ID {000e}
CONFIG.axi_bypass_64bit_en {true}
CONFIG.axi_bypass_prefetchable {true}
CONFIG.axi_data_width {256_bit}
CONFIG.axilite_master_prefetchable {false}
CONFIG.axilite_master_size {16}
CONFIG.axist_bypass_size {256}
CONFIG.mode_selection {Advanced}
CONFIG.mult_pf_des {true}
CONFIG.pf0_device_id {5710}
CONFIG.pf1_device_id {5711}
CONFIG.vendor_id {10EE}

References