AMR V80 - Clock Reset Module

For common clock/reset concepts, see Common Clock Reset

This document describes V80-specific clock and reset configuration.

Overview

The V80 base design uses CIPS-generated clocks (100 MHz, 33.33 MHz, 250 MHz) directly without clock generation IP. A single processor system reset block in the PF1 hierarchy provides reset synchronization for the test logic. The design can be extended with clocking wizards and additional reset blocks when user kernels require custom clock domains.

CIPS Clock Outputs

The CIPS IP provides multiple PL reference clocks for use in the programmable logic:

Clock Signal Frequency Usage in Base Design
pl0_ref_clk 100 MHz PF1 hierarchy (SmartConnect, GPIO, proc_sys_reset_0)
pl1_ref_clk 33.3333 MHz Available for future expansion (user clocking wizard input)
pl2_ref_clk 250 MHz NoC AXI interfaces (axi_noc_cips aclk4)

Base Design Reset Structure

PF1 proc_sys_reset_0

This processor system reset block (xilinx.com:ip:proc_sys_reset:5.0) is instantiated within the PF1 hierarchical block:

Inputs:

  • ext_reset_in: Connected to PF1 aresetn (external reset input)

  • slowest_sync_clk: Connected to pl0_ref_clk (100 MHz)

Outputs:

  • interconnect_aresetn: Reset for SmartConnect (smartconnect_pf1)

  • peripheral_aresetn: Reset for AXI GPIO (axi_gpio_test_pf1)

Function: Synchronizes the external reset signal to the 100 MHz clock domain and generates appropriately timed resets for the SmartConnect interconnect and AXI GPIO peripheral.

Future Expansion - User Clock Domains

For designs requiring custom clock frequencies, the following structure can be added:

usr_clk_wiz (Optional - Not in Base Design)

A Clocking Wizard IP can use the 33.333333MHz from CIPS (pl1_ref_clk) to generate custom frequencies for user kernels (e.g., 300 MHz, 500 MHz). Additional Processor System Reset blocks would synchronize resets to these clock domains.

Additional PSR Blocks (Optional - Not in Base Design)

  • pl_psr: Synchronizes CIPS reset (pl0_resetn) to 100MHz (pl0_ref_clk)

  • pcie_psr: Creates reset synchronous to PCIe clock domain

  • usr_N_psr: Creates resets synchronous to user clock domains from clocking wizard

Flash Reload

AMR uses software-based device reboot via the device_boot command to reload the design from flash. This requires functional AMC firmware and established AMC-to-AMI communication. GPIO-based PCIe hot reset is not supported due to the system complexity of resets described below.

  • When PCIe Reset asserts, this reset does not naturally progress to the rest of the device.

  • The reset structure of Versal is not structured/tested in a way that it can be reset properly without reloading the entire design from flash (in the desired time frame).

    • The programmatic way to reset NOC, PS, DDR, HBM, etc is by issuing a POR and reloading the design from flash.

  • The device POR cannot be issued until the host has issued the PCIe reset sequence or adverse behavior on the host may be observed.

    • Some DELL servers reboot themselves if the PCIe link goes down unexpectedly.

  • When AMC-to-AMI communication is not established or if the AMC is not in a good state, a complete power cycle of the device is required.