AMR - Address Mapping Concepts (Common)

For board-specific address maps, see:

Overview

This document describes common address mapping concepts for all AMR boards. All boards require address translation between PCIe and AXI address domains.

All AMR boards follow common address mapping patterns despite board-specific implementation differences. PCIe addressing uses 64-bit addresses in the terabyte range starting from 0x200_0000_0000 and above, while AXI addressing employs local address spaces typically starting from lower values. Translation between these address domains occurs through PCIEBAR2AXIBAR registers (configured in either CPM or PCIe IP depending on board) and through NoC REMAPS parameters in the AXI NoC IP configuration. The two physical functions (PF0 for management, PF1 for user) occupy separate address ranges enabling independent access control and address space management.

Versal Address Space (Common)

4GB Address Space (32-bit)

Range: 0x000_0000_0000 - 0x000_FFFF_FFFF

The 4GB address space contains the PS and PMC peripheral registers providing control and status access to integrated peripherals. The lower DDR memory region occupies a portion of this space, accessible through standard memory addressing. On-Chip Memory (OCM) provides fast local memory for critical code and data. This address range represents the maximum directly addressable by the RPU due to its 32-bit addressing limitation, influencing firmware memory allocation strategies.

Reference: Versal 4GB Address Map

16TB Address Space (64-bit)

Range: 0x000_0000_0000 - 0x0FF_FFFF_FFFF

The 16TB address space encompasses the complete 4GB space described above along with extended regions for larger memory allocations. Upper DDR regions occupy addresses above the 4GB boundary, accessible through 64-bit addressing from capable masters. High-Bandwidth Memory (HBM) address space exists on boards featuring HBM devices, providing dedicated addressing for the HBM controller access. Programmable logic address space begins at 0x200_0000_0000 and above, with PCIe BARs typically mapped into this region.

Reference: Versal 16TB Address Map

PCIe to AXI Address Translation

Translation Mechanism

All boards translate PCIe addresses to AXI:

PCIe Address Space:

  • TB-range 64-bit addresses

  • Example: 0x201_0000_0000 (PF0), 0x202_0000_0000 (PF1)

AXI Local Address Space:

  • Typically 0x0000_0000 or 0x1000_0000 base

  • Smaller address ranges

Translation Configured In:

  • V80: CPM5 PCIEBAR2AXIBAR_QDMA_* registers

  • RAVE: PCIe IP PCIEBAR2AXIBAR configuration

  • Both: NoC REMAPS parameter in AXI NoC IP

NoC Address Remapping

AXI NoC IP REMAPS configuration:

CONFIG.REMAPS {M00_INI {{0x201_0000_0000 0x1000_0000 8M}}}

Syntax:

  • PCIe address: 0x201_0000_0000

  • AXI local address: 0x1000_0000

  • Size: 8M

Physical Function Address Spaces

PF0 (Management) Address Space

Common Pattern:

  • Address range in TB space (0x201_xxxx_xxxx)

  • BAR0 provides management register access

  • Size varies by board (V80: 8MB, RAVE: configurable)

  • No hardware IP in base design (address space reserved)

PF1 (User/DMA) Address Space

Common Pattern:

  • Address range in TB space (0x202_xxxx_xxxx)

  • BAR0: DMA registers and descriptors

  • BAR2: AXI bridge to PL (test GPIO, user logic)

  • Size varies by board

DDR Memory Regions (Common Concepts)

Lower DDR (0x000_0000_0000 - 0x000_7FFF_FFFF)

This lower DDR region serves multiple purposes during system operation. The PMC uses portions of this space during boot and configuration activities. The RPU firmware execution requires memory in this region for code sections, initialized data, BSS sections, stack allocation, and heap management. Software GCQ buffers reside in this region to enable efficient RPU access without address extension. Remaining portions are available for general firmware use including data structures, buffers, and runtime allocations.

Upper DDR (0x500_0000_0000+)

The upper DDR regions provide additional memory capacity beyond the 32-bit addressable range. These regions hold user application data, DMA transfer buffers, and extended data structures that do not require direct RPU access. The PCIe host and other 64-bit capable masters access these regions through the NoC. Specific address ranges and total upper DDR capacity vary significantly by board depending on the memory architecture and installed memory devices.

PL Address Space (Common Concept)

PL Region Base Addresses

Typical PL address range:

  • Starts at 0x200_0000_0000+ (TB range)

  • Divided by Physical Function

Common Allocation:

  • 0x201_xxxx_xxxx: PF0 address space

  • 0x202_xxxx_xxxx: PF1 address space

  • 0x203_xxxx_xxxx+: Additional PFs (if enabled)

Local AXI Address Space in PL

After NoC remapping:

  • PL IP typically sees local addresses

  • Example: 0x1000_0000 base address

  • SmartConnect further routes to peripherals

Board-Specific Address Maps

For detailed address maps with specific ranges:

V80 Address Map

V80 Memory Map

V80-Specific Address Regions:

  • PF0: 0x201_0000_0000 - 0x201_007F_FFFF (8MB)

  • PF1: 0x202_0000_0000 - 0x202_0FFF_FFFF (256MB via 1GB aperture)

  • DDR: 4GB discrete SDRAM + 32GB DIMM

  • HBM: Dedicated address space (V80 only)

RAVE Address Map

RAVE Memory Map

RAVE-Specific Address Regions:

  • PF0: Configurable in PCIe IP

  • PF1: Configurable in PCIe IP

  • LPDDR4: 8-16GB total

  • No HBM regions

Address Remapping Examples

Example 1: PF0 Management Space (V80)

PCIe Side (Host View):

BAR0: 0x201_0000_0000 - 0x201_007F_FFFF (8MB)

AXI Side (Versal View):

Local: 0x1000_0000 - 0x107F_FFFF (8MB)

Configuration:

  • CPM5: PCIEBAR2AXIBAR_QDMA_0 = 0x0201_0000_0000

  • NoC: REMAPS {M00_INI {{0x201_0000_0000 0x1000_0000 8M}}}

Example 2: Software GCQ Buffer

Host Access via PCIe:

Mapped region in PF0 BAR (e.g., 0x201_0800_0000)
  ↓ (NoC remap)
DRAM physical address (e.g., 0x000_1000_0000)

RPU Access:

Direct DRAM address: 0x000_1000_0000

Both access same physical DDR location via different address paths.

Design Guidelines

Allocating PL Address Space

When adding custom IP:

  1. Check available address space

    • PF0: Management space (board-dependent size)

    • PF1: User space (board-dependent size)

  2. Use SmartConnect for routing

    • Connect to PF0/PF1 AXI interfaces

    • SmartConnect decodes local addresses

  3. Update address maps

    • Document IP base addresses

    • Update NoC REMAPS if needed

    • Ensure no conflicts

Shared Memory for IPC

Software GCQ pattern:

  • Allocate DRAM region accessible by both host and RPU

  • Configure NoC remap for host PCIe access

  • RPU accesses directly via DDR address

  • Synchronize via firmware protocols

References