![]() |
axipcie
Vitis Drivers API Documentation
|
Data Structures | |
struct | XAxiPcie_Config |
This typedef contains IP hardware configuration information. More... | |
struct | XAxiPcie |
The XAxiPcie driver instance data. More... | |
struct | XAxiPcie_BarAddr |
The user is required to use this strucuture when reading or writing translation vector between local bus BARs and AXI PCIe BARs. More... | |
Macros | |
#define | XAXIPCIE_VSEC1 0x00 |
First VSEC Register. More... | |
#define | XAXIPCIE_VSEC2 0x01 |
Second VSEC Register. More... | |
#define | XAxiPcie_IsLinkUp(InstancePtr) |
Check whether link is up or not. More... | |
#define | XAxiPcie_IsEcamBusy(InstancePtr) |
Check whether ECAM is busy or not. More... | |
#define | XAxiPcie_ReadReg(BaseAddress, RegOffset) Xil_In32((BaseAddress) + (RegOffset)) |
Macro to read register. More... | |
#define | XAxiPcie_WriteReg(BaseAddress, RegOffset, Data) Xil_Out32((BaseAddress) + (RegOffset), (Data)) |
Macro to write register. More... | |
Functions | |
XAxiPcie_Config * | XAxiPcie_LookupConfig (u16 DeviceId) |
Lookup the device configuration based on the unique device ID. More... | |
int | XAxiPcie_CfgInitialize (XAxiPcie *InstancePtr, XAxiPcie_Config *CfgPtr, UINTPTR EffectiveAddress) |
Initialize the XAxiPcie instance provided by the caller based on the given Config structure. More... | |
void | XAxiPcie_GetVsecCapability (XAxiPcie *InstancePtr, u8 VsecNum, u16 *VsecIdPtr, u8 *VersionPtr, u16 *NextCapPtr) |
This API is used to read the VSEC Capability Register. More... | |
void | XAxiPcie_GetVsecHeader (XAxiPcie *InstancePtr, u8 VsecNum, u16 *VsecIdPtr, u8 *RevisionPtr, u16 *LengthPtr) |
This API is used to read the VSEC Header Register. More... | |
void | XAxiPcie_GetBridgeInfo (XAxiPcie *InstancePtr, u8 *Gen2Ptr, u8 *RootPortPtr, u8 *ECAMSizePtr) |
This API Reads the Bridge info register. More... | |
void | XAxiPcie_GetRequesterId (XAxiPcie *InstancePtr, u8 *BusNumPtr, u8 *DevNumPtr, u8 *FunNumPtr, u8 *PortNumPtr) |
Read the Bus Location register. More... | |
void | XAxiPcie_GetPhyStatusCtrl (XAxiPcie *InstancePtr, u32 *PhyState) |
This API is used to read the Phy Status/Control Register. More... | |
void | XAxiPcie_GetRootPortStatusCtrl (XAxiPcie *InstancePtr, u32 *StatusPtr) |
Read Root Port Status/Control Register. More... | |
void | XAxiPcie_SetRootPortStatusCtrl (XAxiPcie *InstancePtr, u32 StatusData) |
Write Value in Root Port Status/Control Register. More... | |
int | XAxiPcie_SetRootPortMSIBase (XAxiPcie *InstancePtr, unsigned long long MsiBase) |
Write MSI Base Address to Root Port MSI Base Address Register. More... | |
void | XAxiPcie_GetRootPortErrFIFOMsg (XAxiPcie *InstancePtr, u16 *ReqIdPtr, u8 *ErrType, u8 *ErrValid) |
Read Root Port Error FIFO Message. More... | |
void | XAxiPcie_ClearRootPortErrFIFOMsg (XAxiPcie *InstancePtr) |
Clear Root Port Error FIFO Message. More... | |
int | XAxiPcie_GetRootPortIntFIFOReg (XAxiPcie *InstancePtr, u16 *ReqIdPtr, u16 *MsiAddr, u8 *MsiInt, u8 *IntValid, u16 *MsiMsgData) |
Read Root Port Interrupt FIFO message Register 1 & 2. More... | |
void | XAxiPcie_ClearRootPortIntFIFOReg (XAxiPcie *InstancePtr) |
Clear Root Port FIFO Interrupt message Register 1 & 2. More... | |
void | XAxiPcie_GetLocalBusBar2PcieBar (XAxiPcie *InstancePtr, u8 BarNumber, XAxiPcie_BarAddr *BarAddrPtr) |
Read PCIe address translation vector that corresponds to one of AXI local bus bars passed by the caller. More... | |
void | XAxiPcie_SetLocalBusBar2PcieBar (XAxiPcie *InstancePtr, u8 BarNumber, XAxiPcie_BarAddr *BarAddrPtr) |
Write PCIe address translation vector that corresponds to one of AXI local bus bars passed by the caller. More... | |
void | XAxiPcie_ReadLocalConfigSpace (XAxiPcie *InstancePtr, u16 Offset, u32 *DataPtr) |
Read 32-bit value from one of this IP own configuration space. More... | |
void | XAxiPcie_WriteLocalConfigSpace (XAxiPcie *InstancePtr, u16 Offset, u32 Data) |
Write 32-bit value to one of this IP own configuration space. More... | |
void | XAxiPcie_ReadRemoteConfigSpace (XAxiPcie *InstancePtr, u8 Bus, u8 Device, u8 Function, u16 Offset, u32 *DataPtr) |
Read 32-bit value from external PCIe Function's configuration space. More... | |
void | XAxiPcie_WriteRemoteConfigSpace (XAxiPcie *InstancePtr, u8 Bus, u8 Device, u8 Function, u16 Offset, u32 Data) |
Write 32-bit value to external PCIe function's configuration space. More... | |
void | XAxiPcie_EnableGlobalInterrupt (XAxiPcie *InstancePtr) |
Enable the Global Interrupt. More... | |
void | XAxiPcie_DisableGlobalInterrupt (XAxiPcie *InstancePtr) |
Disable the Global Interrupt. More... | |
void | XAxiPcie_EnableInterrupts (XAxiPcie *InstancePtr, u32 EnableMask) |
Enable the IP interrupt bits passed into "EnableMask". More... | |
void | XAxiPcie_DisableInterrupts (XAxiPcie *InstancePtr, u32 DisableMask) |
Disable the IP interrupt bits passed into "DisableMask". More... | |
void | XAxiPcie_GetEnabledInterrupts (XAxiPcie *InstancePtr, u32 *EnabledMaskPtr) |
Get the currently enabled interrupt bits of the IP and pass them back to the caller into "EnabledMask". More... | |
void | XAxiPcie_GetPendingInterrupts (XAxiPcie *InstancePtr, u32 *PendingMaskPtr) |
Get the currently pending interrupt bits of the IP and pass them back to the caller into "PendingMask". More... | |
void | XAxiPcie_ClearPendingInterrupts (XAxiPcie *InstancePtr, u32 ClearMask) |
Clear the currently pending interrupt bits of the IP passed from the caller into "ClearMask". More... | |
Registers | |
Register offsets for this device. Some of the registers are configurable at hardware build time such that may or may not exist in the hardware. | |
#define | XAXIPCIE_PCIE_CORE_OFFSET 0x000 |
PCI Express hard core configuration register offset. More... | |
#define | XAXIPCIE_VSECC_OFFSET 0x128 |
VSEC Capability Register. More... | |
#define | XAXIPCIE_VSECH_OFFSET 0x12C |
VSEC Header Register. More... | |
#define | XAXIPCIE_BI_OFFSET 0x130 |
Bridge Info Register. More... | |
#define | XAXIPCIE_BSC_OFFSET 0x134 |
Bridge Status and Control Register. More... | |
#define | XAXIPCIE_ID_OFFSET 0x138 |
Interrupt Decode Register. More... | |
#define | XAXIPCIE_IM_OFFSET 0x13C |
Interrupt Mask Register. More... | |
#define | XAXIPCIE_BL_OFFSET 0x140 |
Bus Location Register. More... | |
#define | XAXIPCIE_PHYSC_OFFSET 0x144 |
Physical status and Control Register. More... | |
#define | XAXIPCIE_RPSC_OFFSET 0x148 |
Root Port Status & Control Register. More... | |
#define | XAXIPCIE_RPMSIB_UPPER_OFFSET 0x14C |
Root Port MSI Base 1 Register Upper 32 bits from 64 bit address are written. More... | |
#define | XAXIPCIE_RPMSIB_LOWER_OFFSET 0x150 |
Root Port MSI Base 2 Register Lower 32 bits from 64 bit address are written. More... | |
#define | XAXIPCIE_RPEFR_OFFSET 0x154 |
Root Port Error FIFO Read Register. More... | |
#define | XAXIPCIE_RPIFR1_OFFSET 0x158 |
Root Port Interrupt FIFO Read1 Register. More... | |
#define | XAXIPCIE_RPIFR2_OFFSET 0x15C |
Root Port Interrupt FIFO Read2 Register. More... | |
#define | XAXIPCIE_AXIBAR2PCIBAR_0U_OFFSET 0x208 |
AXIBAR 2 PCIBAR translation 0 upper 32 bits. More... | |
#define | XAXIPCIE_AXIBAR2PCIBAR_0L_OFFSET 0x20C |
AXIBAR to PCIBAR translation 0 lower 32 bits. More... | |
#define | XAXIPCIE_AXIBAR2PCIBAR_1U_OFFSET 0x210 |
AXIBAR to PCIBAR translation 1 upper 32 bits. More... | |
#define | XAXIPCIE_AXIBAR2PCIBAR_1L_OFFSET 0x214 |
AXIBAR to PCIBAR translation 1 lower 32 bits. More... | |
#define | XAXIPCIE_AXIBAR2PCIBAR_2U_OFFSET 0x218 |
AXIBAR to PCIBAR translation 2 upper 32 bits. More... | |
#define | XAXIPCIE_AXIBAR2PCIBAR_2L_OFFSET 0x21C |
AXIBAR to PCIBAR translation 2 lower 32 bits. More... | |
#define | XAXIPCIE_AXIBAR2PCIBAR_3U_OFFSET 0x220 |
AXIBAR to PCIBAR translation 3 upper 32 bits. More... | |
#define | XAXIPCIE_AXIBAR2PCIBAR_3L_OFFSET 0x224 |
AXIBAR to PCIBAR translation 3 lower 32 bits. More... | |
#define | XAXIPCIE_AXIBAR2PCIBAR_4U_OFFSET 0x228 |
AXIBAR to PCIBAR translation 4 upper 32 bits. More... | |
#define | XAXIPCIE_AXIBAR2PCIBAR_4L_OFFSET 0x22C |
AXIBAR to PCIBAR translation 4 lower 32 bits. More... | |
#define | XAXIPCIE_AXIBAR2PCIBAR_5U_OFFSET 0x230 |
AXIBAR to PCIBAR translation 5 upper 32 bits. More... | |
#define | XAXIPCIE_AXIBAR2PCIBAR_5L_OFFSET 0x234 |
AXIBAR to PCIBAR translation 5 lower 32 bits. More... | |
VSECC Register bitmaps and masks | |
#define | XAXIPCIE_VSECC_ID_MASK 0x0000FFFF |
Vsec capability Id. More... | |
#define | XAXIPCIE_VSECC_VER_MASK 0x000F0000 |
Version of capability Structure. More... | |
#define | XAXIPCIE_VSECC_NEXT_MASK 0xFFF00000 |
Offset to next capability. More... | |
#define | XAXIPCIE_VSECC_VER_SHIFT 16 |
VSEC Version shift. More... | |
#define | XAXIPCIE_VSECC_NEXT_SHIFT 20 |
Next capability offset shift. More... | |
VSECH Register bitmaps and masks | |
#define | XAXIPCIE_VSECH_ID_MASK 0x0000FFFF |
Vsec structure Id. More... | |
#define | XAXIPCIE_VSECH_REV_MASK 0x000F0000 |
Vsec header version. More... | |
#define | XAXIPCIE_VSECH_LEN_MASK 0xFFF00000 |
Length of Vsec capability structure. More... | |
#define | XAXIPCIE_VSECH_REV_SHIFT 16 |
Vsec version shift. More... | |
#define | XAXIPCIE_VSECH_LEN_SHIFT 20 |
Vsec length shift. More... | |
Bridge Info Register bitmaps and masks | |
#define | XAXIPCIE_BI_GEN2_MASK 0x00000001 |
PCIe Gen2 Speed Support Mask. More... | |
#define | XAXIPCIE_BI_RP_MASK 0x00000002 |
PCIe Root Port Support. More... | |
#define | XAXIPCIE_UP_CONFIG_CAPABLE 0x00000004 |
Up Config Capable. More... | |
#define | XAXIPCIE_BI_ECAM_SIZE_MASK 0x00070000 |
ECAM size. More... | |
#define | XAXIPCIE_BI_RP_SHIFT 1 |
PCIe Root Port Shift. More... | |
#define | XAXIPCIE_BI_ECAM_SIZE_SHIFT 16 |
PCIe ECAM Size Shift. More... | |
Bridge Status & Control Register bitmaps and masks | |
#define | XAXIPCIE_BSC_ECAM_BUSY_MASK 0x00000001 |
ECAM Busy Status. More... | |
#define | XAXIPCIE_BSC_GI_MASK 0x00000100 |
Global Interrupt Disable. More... | |
#define | XAXIPCIE_BSC_RW1C_MASK 0x00010000 |
RW Permissions to RW1C Registers. More... | |
#define | XAXIPCIE_BSC_RO_MASK 0x00020000 |
RW Permissions to RO Registers. More... | |
#define | XAXIPCIE_BSC_GI_SHIFT 8 |
Global Interrupt Disable Shift. More... | |
#define | XAXIPCIE_BSC_RW1C_SHIFT 16 |
RW1C Shift. More... | |
#define | XAXIPCIE_BSC_RO_SHIFT 17 |
RO as RW Shift. More... | |
Interrupt Decode Register bitmaps and masks | |
#define | XAXIPCIE_ID_LINK_DOWN_MASK 0x00000001 |
Link Down Mask. More... | |
#define | XAXIPCIE_ID_ECRC_ERR_MASK 0x00000002 |
Rx Packet CRC failed. More... | |
#define | XAXIPCIE_ID_STR_ERR_MASK 0x00000004 |
Streaming Error Mask. More... | |
#define | XAXIPCIE_ID_HOT_RST_MASK 0x00000008 |
Hot Reset Mask. More... | |
#define | XAXIPCIE_ID_CFG_COMPL_STATE_MASK 0x000000E0 |
Cfg Completion Status Mask. More... | |
#define | XAXIPCIE_ID_CFG_TIMEOUT_MASK 0x00000100 |
Cfg timeout Mask. More... | |
#define | XAXIPCIE_ID_CORRECTABLE_ERR_MASK 0x00000200 |
Correctable Error Mask. More... | |
#define | XAXIPCIE_ID_NONFATAL_ERR_MASK 0x00000400 |
Non-Fatal Error Mask. More... | |
#define | XAXIPCIE_ID_FATAL_ERR_MASK 0x00000800 |
Fatal Error Mask. More... | |
#define | XAXIPCIE_ID_INTX_INTERRUPT 0x00010000 |
INTX Interrupt. More... | |
#define | XAXIPCIE_ID_MSI_INTERRUPT 0x00020000 |
MSI Interrupt. More... | |
#define | XAXIPCIE_ID_UNSUPP_CMPL_MASK 0x00100000 |
Slave Unsupported Request Mask. More... | |
#define | XAXIPCIE_ID_UNEXP_CMPL_MASK 0x00200000 |
Slave Unexpected Completion Mask. More... | |
#define | XAXIPCIE_ID_CMPL_TIMEOUT_MASK 0x00400000 |
Slave completion Time Mask. More... | |
#define | XAXIPCIE_ID_SLV_EP_MASK 0x00800000 |
Slave Error Poison Mask. More... | |
#define | XAXIPCIE_ID_CMPL_ABT_MASK 0x01000000 |
Slave completion Abort Mask. More... | |
#define | XAXIPCIE_ID_ILL_BURST_MASK 0x02000000 |
Slave Illegal Burst Mask. More... | |
#define | XAXIPCIE_ID_DECODE_ERR_MASK 0x04000000 |
Master Decode Error Interrupt Mask. More... | |
#define | XAXIPCIE_ID_SLAVE_ERR_MASK 0x08000000 |
Master Slave Error Interrupt Mask. More... | |
#define | XAXIPCIE_ID_MASTER_EP_MASK 0x10000000 |
Master Error Poison Mask. More... | |
#define | XAXIPCIE_ID_CLEAR_ALL_MASK 0xFFFFFFFF |
Mask of all Interrupts. More... | |
Interrupt Mask Register bitmaps and masks | |
#define | XAXIPCIE_IM_ENABLE_ALL_MASK 0xFFFFFFFF |
Enable All Interrupts. More... | |
#define | XAXIPCIE_IM_DISABLE_ALL_MASK 0x00000000 |
Disable All Interrupts. More... | |
Bus Location Register bitmaps and masks | |
#define | XAXIPCIE_BL_FUNC_MASK 0x00000007 |
Requester ID Function Number. More... | |
#define | XAXIPCIE_BL_DEV_MASK 0x000000F8 |
Requester ID Device Number. More... | |
#define | XAXIPCIE_BL_BUS_MASK 0x0000FF00 |
Requester ID Bus Number. More... | |
#define | XAXIPCIE_BL_PORT_MASK 0x00FF0000 |
Requester ID Port Number. More... | |
#define | XAXIPCIE_BL_DEV_SHIFT 3 |
Requester ID Device Number Shift Value. More... | |
#define | XAXIPCIE_BL_BUS_SHIFT 8 |
Requester ID Bus Number Shift Value. More... | |
#define | XAXIPCIE_BL_PORT_SHIFT 16 |
Requester ID Bus Number Shift Value. More... | |
PHY Status & Control Register bitmaps and masks | |
#define | XAXIPCIE_PHYSC_LINK_RATE_MASK 0x00000001 |
Link Rate. More... | |
#define | XAXIPCIE_PHYSC_LINK_WIDTH_MASK 0x00000006 |
Link Width Mask. More... | |
#define | XAXIPCIE_PHYSC_LTSSM_STATE_MASK 0x000001F8 |
LTSSM State Mask. More... | |
#define | XAXIPCIE_PHYSC_LANE_REV_MASK 0x00000600 |
Lane Reversal Mask. More... | |
#define | XAXIPCIE_PHYSC_LINK_UP_MASK 0x00000800 |
Link Up Status Mask. More... | |
#define | XAXIPCIE_PHYSC_DLW_MASK 0x00030000 |
Directed Link Width to change Mask. More... | |
#define | XAXIPCIE_PHYSC_DLWS_MASK 0x00040000 |
Directed Link Width Speed to change Mask. More... | |
#define | XAXIPCIE_PHYSC_DLA_MASK 0x00080000 |
Directed Link Change change to reliability or Autonomus Mask. More... | |
#define | XAXIPCIE_PHYSC_DLC_MASK 0x00300000 |
Directed Link change Mask. More... | |
#define | XAXIPCIE_PHYSC_LINK_WIDTH_SHIFT 1 |
Link Status Shift. More... | |
#define | XAXIPCIE_PHYSC_LTSSM_STATE_SHIFT 3 |
LTSSM State Shift. More... | |
#define | XAXIPCIE_PHYSC_LANE_REV_SHIFT 9 |
Lane Reversal Shift. More... | |
#define | XAXIPCIE_PHYSC_LINK_UP_SHIFT 11 |
Link Up Status Shift. More... | |
#define | XAXIPCIE_PHYSC_DLW_SHIFT 16 |
Directed Link Width to change Shift. More... | |
#define | XAXIPCIE_PHYSC_DLWS_SHIFT 18 |
Directed Link Width Speed to change Shift. More... | |
#define | XAXIPCIE_PHYSC_DLA_SHIFT 19 |
Directed Link change to reliability or Autonomus Shift. More... | |
#define | XAXIPCIE_PHYSC_DLC_SHIFT 20 |
Directed Link change Shift. More... | |
Root Port Status/Control Register bitmaps and masks | |
#define | XAXIPCIE_RPSC_MASK 0x0FFF0001 |
Root Port Register mask. More... | |
#define | XAXIPCIE_RPSC_BRIDGE_ENABLE_MASK 0x00000001 |
Bridge Enable Mask. More... | |
#define | XAXIPCIE_RPSC_ERR_FIFO_NOT_EMPTY_MASK 0x00010000 |
Root Port Error FIFO Not Empty. More... | |
#define | XAXIPCIE_RPSC_ERR_FIFO_OVERFLOW_MASK 0x00020000 |
Root Port Error FIFO Overflow. More... | |
#define | XAXIPCIE_RPSC_INT_FIFO_NOT_EMPTY_MASK 0x00040000 |
Root Port Interrupt FIFO Not Empty. More... | |
#define | XAXIPCIE_RPSC_INT_FIFO_OVERFLOW_MASK 0x00080000 |
Root Port Interrupt FIFO Overflow. More... | |
#define | XAXIPCIE_RPSC_COMP_TIMEOUT_MASK 0x0FF00000 |
Root Port Completion Timeout. More... | |
#define | XAXIPCIE_RPSC_ERR_FIFO_NOT_EMPTY_SHIFT 16 |
Root Port Error FIFO Empty Shift. More... | |
#define | XAXIPCIE_RPSC_ERR_FIFO_OVERFLOW_SHIFT 17 |
Root Port Error FIFO Overflow Shift. More... | |
#define | XAXIPCIE_RPSC_INT_FIFO_NOT_EMPTY_SHIFT 18 |
Root Port Interrupt FIFO Empty Shift. More... | |
#define | XAXIPCIE_RPSC_INT_FIFO_OVERFLOW_SHIFT 19 |
Root Port Interrupt FIFO Overflow Shift. More... | |
#define | XAXIPCIE_RPSC_COMP_TIMEOUT_SHIFT 20 |
Root Port Completion Timeout Shift. More... | |
Root Port MSI Base Register bitmaps and masks | |
#define | XAXIPCIE_RPMSIB_UPPER_MASK 0xFFFFFFFF |
Upper 32 bits of 64 bit MSI Base Address. More... | |
#define | XAXIPCIE_RPMSIB_UPPER_SHIFT 32 /* Shift of Upper 32 bits */ |
#define | XAXIPCIE_RPMSIB_LOWER_MASK 0xFFFFF000 |
Lower 32 bits of 64 bit MSI Base Address. More... | |
Root Port Error FIFO Read Register bitmaps and masks | |
#define | XAXIPCIE_RPEFR_REQ_ID_MASK 0x0000FFFF |
Requester of Error Msg. More... | |
#define | XAXIPCIE_RPEFR_ERR_TYPE_MASK 0x00030000 |
Type of Error. More... | |
#define | XAXIPCIE_RPEFR_ERR_VALID_MASK 0x00040000 |
Error Read Succeeded Status. More... | |
#define | XAXIPCIE_RPEFR_ERR_TYPE_SHIFT 16 |
Type of Error Shift. More... | |
#define | XAXIPCIE_RPEFR_ERR_VALID_SHIFT 18 |
Error Read Succeeded Status Shift. More... | |
Root Port Interrupt FIFO Read 1 Register bitmaps and masks | |
#define | XAXIPCIE_RPIFR1_REQ_ID_MASK 0x0000FFFF |
Requester Id of Interrupt Message. More... | |
#define | XAXIPCIE_RPIFR1_MSI_ADDR_MASK 0x07FF0000 |
MSI Address. More... | |
#define | XAXIPCIE_RPIFR1_INTR_LINE_MASK 0x18000000 |
Intr Line Mask. More... | |
#define | XAXIPCIE_RPIFR1_INTR_ASSERT_MASK 0x20000000 |
Whether Interrupt INTx is asserted. More... | |
#define | XAXIPCIE_RPIFR1_MSIINTR_VALID_MASK 0x40000000 |
Whether Interrupt is MSI or INTx. More... | |
#define | XAXIPCIE_RPIFR1_INTR_VALID_MASK 0x80000000 |
Interrupt Read Succeeded Status. More... | |
#define | XAXIPCIE_RPIFR1_MSI_ADDR_SHIFT 16 |
MSI Address Shift. More... | |
#define | XAXIPCIE_RPIFR1_MSIINTR_VALID_SHIFT 30 |
MSI/INTx Interrupt Shift. More... | |
#define | XAXIPCIE_RPIFR1_INTR_VALID_SHIFT 31 |
Interrupt Read Valid Shift. More... | |
Root Port Interrupt FIFO Read 2 Register bitmaps and masks | |
#define | XAXIPCIE_RPIFR2_MSG_DATA_MASK 0x0000FFFF |
Pay Load for MSI Message. More... | |
ECAM Address Register bitmaps and masks | |
#define | XAXIPCIE_ECAM_MASK 0x0FFFFFFF |
Mask of all valid bits. More... | |
#define | XAXIPCIE_ECAM_BUS_MASK 0x0FF00000 |
Bus Number Mask. More... | |
#define | XAXIPCIE_ECAM_DEV_MASK 0x000F8000 |
Device Number Mask. More... | |
#define | XAXIPCIE_ECAM_FUN_MASK 0x00007000 |
Function Number Mask. More... | |
#define | XAXIPCIE_ECAM_REG_MASK 0x00000FFC |
Register Number Mask. More... | |
#define | XAXIPCIE_ECAM_BYT_MASK 0x00000003 |
Byte Address Mask. More... | |
#define | XAXIPCIE_ECAM_BUS_SHIFT 20 |
Bus Number Shift Value. More... | |
#define | XAXIPCIE_ECAM_DEV_SHIFT 15 |
Device Number Shift Value. More... | |
#define | XAXIPCIE_ECAM_FUN_SHIFT 12 |
Function Number Shift Value. More... | |
#define | XAXIPCIE_ECAM_REG_SHIFT 2 |
Register Number Shift Value. More... | |
#define | XAXIPCIE_ECAM_BYT_SHIFT 0 |
Byte Offset Shift Value. More... | |
#define XAXIPCIE_AXIBAR2PCIBAR_0L_OFFSET 0x20C |
AXIBAR to PCIBAR translation 0 lower 32 bits.
Referenced by XAxiPcie_GetLocalBusBar2PcieBar(), and XAxiPcie_SetLocalBusBar2PcieBar().
#define XAXIPCIE_AXIBAR2PCIBAR_0U_OFFSET 0x208 |
AXIBAR 2 PCIBAR translation 0 upper 32 bits.
Referenced by XAxiPcie_GetLocalBusBar2PcieBar(), and XAxiPcie_SetLocalBusBar2PcieBar().
#define XAXIPCIE_AXIBAR2PCIBAR_1L_OFFSET 0x214 |
AXIBAR to PCIBAR translation 1 lower 32 bits.
#define XAXIPCIE_AXIBAR2PCIBAR_1U_OFFSET 0x210 |
AXIBAR to PCIBAR translation 1 upper 32 bits.
#define XAXIPCIE_AXIBAR2PCIBAR_2L_OFFSET 0x21C |
AXIBAR to PCIBAR translation 2 lower 32 bits.
#define XAXIPCIE_AXIBAR2PCIBAR_2U_OFFSET 0x218 |
AXIBAR to PCIBAR translation 2 upper 32 bits.
#define XAXIPCIE_AXIBAR2PCIBAR_3L_OFFSET 0x224 |
AXIBAR to PCIBAR translation 3 lower 32 bits.
#define XAXIPCIE_AXIBAR2PCIBAR_3U_OFFSET 0x220 |
AXIBAR to PCIBAR translation 3 upper 32 bits.
#define XAXIPCIE_AXIBAR2PCIBAR_4L_OFFSET 0x22C |
AXIBAR to PCIBAR translation 4 lower 32 bits.
#define XAXIPCIE_AXIBAR2PCIBAR_4U_OFFSET 0x228 |
AXIBAR to PCIBAR translation 4 upper 32 bits.
#define XAXIPCIE_AXIBAR2PCIBAR_5L_OFFSET 0x234 |
AXIBAR to PCIBAR translation 5 lower 32 bits.
#define XAXIPCIE_AXIBAR2PCIBAR_5U_OFFSET 0x230 |
AXIBAR to PCIBAR translation 5 upper 32 bits.
#define XAXIPCIE_BI_ECAM_SIZE_MASK 0x00070000 |
ECAM size.
Referenced by XAxiPcie_CfgInitialize(), and XAxiPcie_GetBridgeInfo().
#define XAXIPCIE_BI_ECAM_SIZE_SHIFT 16 |
PCIe ECAM Size Shift.
Referenced by XAxiPcie_CfgInitialize(), and XAxiPcie_GetBridgeInfo().
#define XAXIPCIE_BI_GEN2_MASK 0x00000001 |
PCIe Gen2 Speed Support Mask.
Referenced by XAxiPcie_GetBridgeInfo().
#define XAXIPCIE_BI_OFFSET 0x130 |
Bridge Info Register.
Referenced by XAxiPcie_CfgInitialize(), and XAxiPcie_GetBridgeInfo().
#define XAXIPCIE_BI_RP_MASK 0x00000002 |
PCIe Root Port Support.
Referenced by XAxiPcie_GetBridgeInfo().
#define XAXIPCIE_BI_RP_SHIFT 1 |
PCIe Root Port Shift.
Referenced by XAxiPcie_GetBridgeInfo().
#define XAXIPCIE_BL_BUS_MASK 0x0000FF00 |
Requester ID Bus Number.
Referenced by XAxiPcie_GetRequesterId().
#define XAXIPCIE_BL_BUS_SHIFT 8 |
Requester ID Bus Number Shift Value.
Referenced by XAxiPcie_GetRequesterId().
#define XAXIPCIE_BL_DEV_MASK 0x000000F8 |
Requester ID Device Number.
Referenced by XAxiPcie_GetRequesterId().
#define XAXIPCIE_BL_DEV_SHIFT 3 |
Requester ID Device Number Shift Value.
Referenced by XAxiPcie_GetRequesterId().
#define XAXIPCIE_BL_FUNC_MASK 0x00000007 |
Requester ID Function Number.
Referenced by XAxiPcie_GetRequesterId().
#define XAXIPCIE_BL_OFFSET 0x140 |
Bus Location Register.
Referenced by XAxiPcie_GetRequesterId().
#define XAXIPCIE_BL_PORT_MASK 0x00FF0000 |
Requester ID Port Number.
Referenced by XAxiPcie_GetRequesterId().
#define XAXIPCIE_BL_PORT_SHIFT 16 |
Requester ID Bus Number Shift Value.
Referenced by XAxiPcie_GetRequesterId().
#define XAXIPCIE_BSC_ECAM_BUSY_MASK 0x00000001 |
ECAM Busy Status.
#define XAXIPCIE_BSC_GI_MASK 0x00000100 |
Global Interrupt Disable.
Referenced by XAxiPcie_DisableGlobalInterrupt(), and XAxiPcie_EnableGlobalInterrupt().
#define XAXIPCIE_BSC_GI_SHIFT 8 |
Global Interrupt Disable Shift.
Referenced by XAxiPcie_DisableGlobalInterrupt(), and XAxiPcie_EnableGlobalInterrupt().
#define XAXIPCIE_BSC_OFFSET 0x134 |
Bridge Status and Control Register.
Referenced by XAxiPcie_DisableGlobalInterrupt(), and XAxiPcie_EnableGlobalInterrupt().
#define XAXIPCIE_BSC_RO_MASK 0x00020000 |
RW Permissions to RO Registers.
#define XAXIPCIE_BSC_RO_SHIFT 17 |
RO as RW Shift.
#define XAXIPCIE_BSC_RW1C_MASK 0x00010000 |
RW Permissions to RW1C Registers.
#define XAXIPCIE_BSC_RW1C_SHIFT 16 |
RW1C Shift.
#define XAXIPCIE_ECAM_BUS_MASK 0x0FF00000 |
Bus Number Mask.
#define XAXIPCIE_ECAM_BUS_SHIFT 20 |
Bus Number Shift Value.
#define XAXIPCIE_ECAM_BYT_MASK 0x00000003 |
Byte Address Mask.
#define XAXIPCIE_ECAM_BYT_SHIFT 0 |
Byte Offset Shift Value.
#define XAXIPCIE_ECAM_DEV_MASK 0x000F8000 |
Device Number Mask.
#define XAXIPCIE_ECAM_DEV_SHIFT 15 |
Device Number Shift Value.
#define XAXIPCIE_ECAM_FUN_MASK 0x00007000 |
Function Number Mask.
#define XAXIPCIE_ECAM_FUN_SHIFT 12 |
Function Number Shift Value.
#define XAXIPCIE_ECAM_MASK 0x0FFFFFFF |
Mask of all valid bits.
#define XAXIPCIE_ECAM_REG_MASK 0x00000FFC |
Register Number Mask.
#define XAXIPCIE_ECAM_REG_SHIFT 2 |
Register Number Shift Value.
#define XAXIPCIE_ID_CFG_COMPL_STATE_MASK 0x000000E0 |
Cfg Completion Status Mask.
#define XAXIPCIE_ID_CFG_TIMEOUT_MASK 0x00000100 |
Cfg timeout Mask.
#define XAXIPCIE_ID_CLEAR_ALL_MASK 0xFFFFFFFF |
Mask of all Interrupts.
Referenced by PCIeEndPointInitialize(), and PcieInitRootComplex().
#define XAXIPCIE_ID_CMPL_ABT_MASK 0x01000000 |
Slave completion Abort Mask.
#define XAXIPCIE_ID_CMPL_TIMEOUT_MASK 0x00400000 |
Slave completion Time Mask.
#define XAXIPCIE_ID_CORRECTABLE_ERR_MASK 0x00000200 |
Correctable Error Mask.
#define XAXIPCIE_ID_DECODE_ERR_MASK 0x04000000 |
Master Decode Error Interrupt Mask.
#define XAXIPCIE_ID_ECRC_ERR_MASK 0x00000002 |
Rx Packet CRC failed.
#define XAXIPCIE_ID_FATAL_ERR_MASK 0x00000800 |
Fatal Error Mask.
#define XAXIPCIE_ID_HOT_RST_MASK 0x00000008 |
Hot Reset Mask.
#define XAXIPCIE_ID_ILL_BURST_MASK 0x02000000 |
Slave Illegal Burst Mask.
#define XAXIPCIE_ID_INTX_INTERRUPT 0x00010000 |
INTX Interrupt.
#define XAXIPCIE_ID_LINK_DOWN_MASK 0x00000001 |
Link Down Mask.
#define XAXIPCIE_ID_MASTER_EP_MASK 0x10000000 |
Master Error Poison Mask.
#define XAXIPCIE_ID_MSI_INTERRUPT 0x00020000 |
MSI Interrupt.
#define XAXIPCIE_ID_NONFATAL_ERR_MASK 0x00000400 |
Non-Fatal Error Mask.
#define XAXIPCIE_ID_OFFSET 0x138 |
Interrupt Decode Register.
Referenced by XAxiPcie_ClearPendingInterrupts(), and XAxiPcie_GetPendingInterrupts().
#define XAXIPCIE_ID_SLAVE_ERR_MASK 0x08000000 |
Master Slave Error Interrupt Mask.
#define XAXIPCIE_ID_SLV_EP_MASK 0x00800000 |
Slave Error Poison Mask.
#define XAXIPCIE_ID_STR_ERR_MASK 0x00000004 |
Streaming Error Mask.
#define XAXIPCIE_ID_UNEXP_CMPL_MASK 0x00200000 |
Slave Unexpected Completion Mask.
#define XAXIPCIE_ID_UNSUPP_CMPL_MASK 0x00100000 |
Slave Unsupported Request Mask.
#define XAXIPCIE_IM_DISABLE_ALL_MASK 0x00000000 |
Disable All Interrupts.
Referenced by XAxiPcie_CfgInitialize().
#define XAXIPCIE_IM_ENABLE_ALL_MASK 0xFFFFFFFF |
Enable All Interrupts.
Referenced by PCIeEndPointInitialize(), and PcieInitRootComplex().
#define XAXIPCIE_IM_OFFSET 0x13C |
Interrupt Mask Register.
Referenced by XAxiPcie_DisableInterrupts(), XAxiPcie_EnableInterrupts(), and XAxiPcie_GetEnabledInterrupts().
#define XAxiPcie_IsEcamBusy | ( | InstancePtr | ) |
Check whether ECAM is busy or not.
InstancePtr | is the XAxiPcie instance to operate on. |
Referenced by XAxiPcie_ReadRemoteConfigSpace(), and XAxiPcie_WriteRemoteConfigSpace().
#define XAxiPcie_IsLinkUp | ( | InstancePtr | ) |
Check whether link is up or not.
InstancePtr | is the XAxiPcie instance to operate on. |
Referenced by PCIeEndPointInitialize(), and PcieInitRootComplex().
#define XAXIPCIE_PCIE_CORE_OFFSET 0x000 |
PCI Express hard core configuration register offset.
Referenced by XAxiPcie_ReadLocalConfigSpace(), and XAxiPcie_WriteLocalConfigSpace().
#define XAXIPCIE_PHYSC_DLA_MASK 0x00080000 |
Directed Link Change change to reliability or Autonomus Mask.
#define XAXIPCIE_PHYSC_DLA_SHIFT 19 |
Directed Link change to reliability or Autonomus Shift.
#define XAXIPCIE_PHYSC_DLC_MASK 0x00300000 |
Directed Link change Mask.
#define XAXIPCIE_PHYSC_DLC_SHIFT 20 |
Directed Link change Shift.
#define XAXIPCIE_PHYSC_DLW_MASK 0x00030000 |
Directed Link Width to change Mask.
#define XAXIPCIE_PHYSC_DLW_SHIFT 16 |
Directed Link Width to change Shift.
#define XAXIPCIE_PHYSC_DLWS_MASK 0x00040000 |
Directed Link Width Speed to change Mask.
#define XAXIPCIE_PHYSC_DLWS_SHIFT 18 |
Directed Link Width Speed to change Shift.
#define XAXIPCIE_PHYSC_LANE_REV_MASK 0x00000600 |
Lane Reversal Mask.
#define XAXIPCIE_PHYSC_LANE_REV_SHIFT 9 |
Lane Reversal Shift.
#define XAXIPCIE_PHYSC_LINK_RATE_MASK 0x00000001 |
Link Rate.
#define XAXIPCIE_PHYSC_LINK_UP_MASK 0x00000800 |
Link Up Status Mask.
#define XAXIPCIE_PHYSC_LINK_UP_SHIFT 11 |
Link Up Status Shift.
#define XAXIPCIE_PHYSC_LINK_WIDTH_MASK 0x00000006 |
Link Width Mask.
#define XAXIPCIE_PHYSC_LINK_WIDTH_SHIFT 1 |
Link Status Shift.
#define XAXIPCIE_PHYSC_LTSSM_STATE_MASK 0x000001F8 |
LTSSM State Mask.
#define XAXIPCIE_PHYSC_LTSSM_STATE_SHIFT 3 |
LTSSM State Shift.
#define XAXIPCIE_PHYSC_OFFSET 0x144 |
Physical status and Control Register.
Referenced by XAxiPcie_GetPhyStatusCtrl().
#define XAxiPcie_ReadReg | ( | BaseAddress, | |
RegOffset | |||
) | Xil_In32((BaseAddress) + (RegOffset)) |
Macro to read register.
BaseAddress | is the base address of the PCIe. |
RegOffset | is the register offset. |
Referenced by XAxiPcie_CfgInitialize(), XAxiPcie_ClearPendingInterrupts(), XAxiPcie_DisableGlobalInterrupt(), XAxiPcie_DisableInterrupts(), XAxiPcie_EnableGlobalInterrupt(), XAxiPcie_EnableInterrupts(), XAxiPcie_GetBridgeInfo(), XAxiPcie_GetEnabledInterrupts(), XAxiPcie_GetLocalBusBar2PcieBar(), XAxiPcie_GetPendingInterrupts(), XAxiPcie_GetPhyStatusCtrl(), XAxiPcie_GetRequesterId(), XAxiPcie_GetRootPortErrFIFOMsg(), XAxiPcie_GetRootPortIntFIFOReg(), XAxiPcie_GetRootPortStatusCtrl(), XAxiPcie_GetVsecCapability(), XAxiPcie_GetVsecHeader(), XAxiPcie_ReadLocalConfigSpace(), XAxiPcie_ReadRemoteConfigSpace(), and XAxiPcie_WriteRemoteConfigSpace().
#define XAXIPCIE_RPEFR_ERR_TYPE_MASK 0x00030000 |
Type of Error.
Referenced by XAxiPcie_GetRootPortErrFIFOMsg().
#define XAXIPCIE_RPEFR_ERR_TYPE_SHIFT 16 |
Type of Error Shift.
Referenced by XAxiPcie_GetRootPortErrFIFOMsg().
#define XAXIPCIE_RPEFR_ERR_VALID_MASK 0x00040000 |
Error Read Succeeded Status.
Referenced by XAxiPcie_GetRootPortErrFIFOMsg().
#define XAXIPCIE_RPEFR_ERR_VALID_SHIFT 18 |
Error Read Succeeded Status Shift.
Referenced by XAxiPcie_GetRootPortErrFIFOMsg().
#define XAXIPCIE_RPEFR_OFFSET 0x154 |
Root Port Error FIFO Read Register.
Referenced by XAxiPcie_ClearRootPortErrFIFOMsg(), and XAxiPcie_GetRootPortErrFIFOMsg().
#define XAXIPCIE_RPEFR_REQ_ID_MASK 0x0000FFFF |
Requester of Error Msg.
Referenced by XAxiPcie_GetRootPortErrFIFOMsg().
#define XAXIPCIE_RPIFR1_INTR_ASSERT_MASK 0x20000000 |
Whether Interrupt INTx is asserted.
#define XAXIPCIE_RPIFR1_INTR_LINE_MASK 0x18000000 |
Intr Line Mask.
#define XAXIPCIE_RPIFR1_INTR_VALID_MASK 0x80000000 |
Interrupt Read Succeeded Status.
Referenced by XAxiPcie_GetRootPortIntFIFOReg().
#define XAXIPCIE_RPIFR1_INTR_VALID_SHIFT 31 |
Interrupt Read Valid Shift.
Referenced by XAxiPcie_GetRootPortIntFIFOReg().
#define XAXIPCIE_RPIFR1_MSI_ADDR_MASK 0x07FF0000 |
MSI Address.
Referenced by XAxiPcie_GetRootPortIntFIFOReg().
#define XAXIPCIE_RPIFR1_MSI_ADDR_SHIFT 16 |
MSI Address Shift.
Referenced by XAxiPcie_GetRootPortIntFIFOReg().
#define XAXIPCIE_RPIFR1_MSIINTR_VALID_MASK 0x40000000 |
Whether Interrupt is MSI or INTx.
Referenced by XAxiPcie_GetRootPortIntFIFOReg().
#define XAXIPCIE_RPIFR1_MSIINTR_VALID_SHIFT 30 |
MSI/INTx Interrupt Shift.
Referenced by XAxiPcie_GetRootPortIntFIFOReg().
#define XAXIPCIE_RPIFR1_OFFSET 0x158 |
Root Port Interrupt FIFO Read1 Register.
Referenced by XAxiPcie_ClearRootPortIntFIFOReg(), and XAxiPcie_GetRootPortIntFIFOReg().
#define XAXIPCIE_RPIFR1_REQ_ID_MASK 0x0000FFFF |
Requester Id of Interrupt Message.
Referenced by XAxiPcie_GetRootPortIntFIFOReg().
#define XAXIPCIE_RPIFR2_MSG_DATA_MASK 0x0000FFFF |
Pay Load for MSI Message.
Referenced by XAxiPcie_GetRootPortIntFIFOReg().
#define XAXIPCIE_RPIFR2_OFFSET 0x15C |
Root Port Interrupt FIFO Read2 Register.
Referenced by XAxiPcie_GetRootPortIntFIFOReg().
#define XAXIPCIE_RPMSIB_LOWER_MASK 0xFFFFF000 |
Lower 32 bits of 64 bit MSI Base Address.
Referenced by XAxiPcie_SetRootPortMSIBase().
#define XAXIPCIE_RPMSIB_LOWER_OFFSET 0x150 |
Root Port MSI Base 2 Register Lower 32 bits from 64 bit address are written.
Referenced by XAxiPcie_SetRootPortMSIBase().
#define XAXIPCIE_RPMSIB_UPPER_MASK 0xFFFFFFFF |
Upper 32 bits of 64 bit MSI Base Address.
Referenced by XAxiPcie_SetRootPortMSIBase().
#define XAXIPCIE_RPMSIB_UPPER_OFFSET 0x14C |
Root Port MSI Base 1 Register Upper 32 bits from 64 bit address are written.
Referenced by XAxiPcie_SetRootPortMSIBase().
#define XAXIPCIE_RPSC_BRIDGE_ENABLE_MASK 0x00000001 |
Bridge Enable Mask.
Referenced by PCIeEnumerateFabric().
#define XAXIPCIE_RPSC_COMP_TIMEOUT_MASK 0x0FF00000 |
Root Port Completion Timeout.
#define XAXIPCIE_RPSC_COMP_TIMEOUT_SHIFT 20 |
Root Port Completion Timeout Shift.
#define XAXIPCIE_RPSC_ERR_FIFO_NOT_EMPTY_MASK 0x00010000 |
Root Port Error FIFO Not Empty.
#define XAXIPCIE_RPSC_ERR_FIFO_NOT_EMPTY_SHIFT 16 |
Root Port Error FIFO Empty Shift.
#define XAXIPCIE_RPSC_ERR_FIFO_OVERFLOW_MASK 0x00020000 |
Root Port Error FIFO Overflow.
#define XAXIPCIE_RPSC_ERR_FIFO_OVERFLOW_SHIFT 17 |
Root Port Error FIFO Overflow Shift.
#define XAXIPCIE_RPSC_INT_FIFO_NOT_EMPTY_MASK 0x00040000 |
Root Port Interrupt FIFO Not Empty.
#define XAXIPCIE_RPSC_INT_FIFO_NOT_EMPTY_SHIFT 18 |
Root Port Interrupt FIFO Empty Shift.
#define XAXIPCIE_RPSC_INT_FIFO_OVERFLOW_MASK 0x00080000 |
Root Port Interrupt FIFO Overflow.
#define XAXIPCIE_RPSC_INT_FIFO_OVERFLOW_SHIFT 19 |
Root Port Interrupt FIFO Overflow Shift.
#define XAXIPCIE_RPSC_MASK 0x0FFF0001 |
Root Port Register mask.
Referenced by XAxiPcie_SetRootPortStatusCtrl().
#define XAXIPCIE_RPSC_OFFSET 0x148 |
Root Port Status & Control Register.
Referenced by XAxiPcie_GetRootPortStatusCtrl(), and XAxiPcie_SetRootPortStatusCtrl().
#define XAXIPCIE_UP_CONFIG_CAPABLE 0x00000004 |
Up Config Capable.
#define XAXIPCIE_VSEC1 0x00 |
First VSEC Register.
#define XAXIPCIE_VSEC2 0x01 |
Second VSEC Register.
#define XAXIPCIE_VSECC_ID_MASK 0x0000FFFF |
Vsec capability Id.
Referenced by XAxiPcie_GetVsecCapability().
#define XAXIPCIE_VSECC_NEXT_MASK 0xFFF00000 |
Offset to next capability.
Referenced by XAxiPcie_GetVsecCapability().
#define XAXIPCIE_VSECC_NEXT_SHIFT 20 |
Next capability offset shift.
Referenced by XAxiPcie_GetVsecCapability().
#define XAXIPCIE_VSECC_OFFSET 0x128 |
VSEC Capability Register.
Referenced by XAxiPcie_GetVsecCapability().
#define XAXIPCIE_VSECC_VER_MASK 0x000F0000 |
Version of capability Structure.
Referenced by XAxiPcie_GetVsecCapability().
#define XAXIPCIE_VSECC_VER_SHIFT 16 |
VSEC Version shift.
Referenced by XAxiPcie_GetVsecCapability().
#define XAXIPCIE_VSECH_ID_MASK 0x0000FFFF |
Vsec structure Id.
Referenced by XAxiPcie_GetVsecHeader().
#define XAXIPCIE_VSECH_LEN_MASK 0xFFF00000 |
Length of Vsec capability structure.
Referenced by XAxiPcie_GetVsecHeader().
#define XAXIPCIE_VSECH_LEN_SHIFT 20 |
Vsec length shift.
Referenced by XAxiPcie_GetVsecHeader().
#define XAXIPCIE_VSECH_OFFSET 0x12C |
VSEC Header Register.
Referenced by XAxiPcie_GetVsecHeader().
#define XAXIPCIE_VSECH_REV_MASK 0x000F0000 |
Vsec header version.
Referenced by XAxiPcie_GetVsecHeader().
#define XAXIPCIE_VSECH_REV_SHIFT 16 |
Vsec version shift.
Referenced by XAxiPcie_GetVsecHeader().
#define XAxiPcie_WriteReg | ( | BaseAddress, | |
RegOffset, | |||
Data | |||
) | Xil_Out32((BaseAddress) + (RegOffset), (Data)) |
Macro to write register.
BaseAddress | is the base address of the PCIe. |
RegOffset | is the register offset. |
Data | is the data to write. |
Referenced by XAxiPcie_ClearPendingInterrupts(), XAxiPcie_ClearRootPortErrFIFOMsg(), XAxiPcie_ClearRootPortIntFIFOReg(), XAxiPcie_DisableGlobalInterrupt(), XAxiPcie_DisableInterrupts(), XAxiPcie_EnableGlobalInterrupt(), XAxiPcie_EnableInterrupts(), XAxiPcie_SetLocalBusBar2PcieBar(), XAxiPcie_SetRootPortMSIBase(), XAxiPcie_SetRootPortStatusCtrl(), XAxiPcie_WriteLocalConfigSpace(), and XAxiPcie_WriteRemoteConfigSpace().
int XAxiPcie_CfgInitialize | ( | XAxiPcie * | InstancePtr, |
XAxiPcie_Config * | CfgPtr, | ||
UINTPTR | EffectiveAddress | ||
) |
Initialize the XAxiPcie instance provided by the caller based on the given Config structure.
InstancePtr | is the XAxiPcie instance to operate on.The memory of the pointer references must be pre-allocated by the caller. |
CfgPtr | is the device configuration structure containing required HW build data. |
EffectiveAddress | is the Physical address of the hardware in a Virtual Memory operating system environment.It is the Base Address in a stand alone environment. |
- XST_SUCCESS Initialization was successful.
References XAxiPcie_Config::BaseAddress, XAxiPcie::Config, XAxiPcie::IsReady, XAxiPcie::MaxNumOfBuses, XAXIPCIE_BI_ECAM_SIZE_MASK, XAXIPCIE_BI_ECAM_SIZE_SHIFT, XAXIPCIE_BI_OFFSET, XAxiPcie_DisableInterrupts(), XAXIPCIE_IM_DISABLE_ALL_MASK, and XAxiPcie_ReadReg.
Referenced by PCIeEndPointInitialize(), and PcieInitRootComplex().
void XAxiPcie_ClearPendingInterrupts | ( | XAxiPcie * | InstancePtr, |
u32 | ClearMask | ||
) |
Clear the currently pending interrupt bits of the IP passed from the caller into "ClearMask".
InstancePtr | is the XAxiPcie instance to operate on. |
ClearMask | is the bit pattern for pending interrupts wanted to be cleared. |
References XAxiPcie_Config::BaseAddress, XAxiPcie::Config, XAxiPcie::IsReady, XAXIPCIE_ID_OFFSET, XAxiPcie_ReadReg, and XAxiPcie_WriteReg.
Referenced by PCIeEndPointInitialize(), and PcieInitRootComplex().
void XAxiPcie_ClearRootPortErrFIFOMsg | ( | XAxiPcie * | InstancePtr | ) |
Clear Root Port Error FIFO Message.
InstancePtr | is the PCIe component to operate on. |
References XAxiPcie_Config::BaseAddress, XAxiPcie::Config, XAxiPcie_Config::IncludeRootComplex, XAxiPcie::IsReady, XAXIPCIE_RPEFR_OFFSET, and XAxiPcie_WriteReg.
void XAxiPcie_ClearRootPortIntFIFOReg | ( | XAxiPcie * | InstancePtr | ) |
Clear Root Port FIFO Interrupt message Register 1 & 2.
InstancePtr | is the PCIe component to operate on |
References XAxiPcie_Config::BaseAddress, XAxiPcie::Config, XAxiPcie_Config::IncludeRootComplex, XAxiPcie::IsReady, XAXIPCIE_RPIFR1_OFFSET, and XAxiPcie_WriteReg.
void XAxiPcie_DisableGlobalInterrupt | ( | XAxiPcie * | InstancePtr | ) |
Disable the Global Interrupt.
InstancePtr | is the XAxiPcie instance to operate on. |
References XAxiPcie_Config::BaseAddress, XAxiPcie::Config, XAxiPcie::IsReady, XAXIPCIE_BSC_GI_MASK, XAXIPCIE_BSC_GI_SHIFT, XAXIPCIE_BSC_OFFSET, XAxiPcie_ReadReg, and XAxiPcie_WriteReg.
void XAxiPcie_DisableInterrupts | ( | XAxiPcie * | InstancePtr, |
u32 | DisableMask | ||
) |
Disable the IP interrupt bits passed into "DisableMask".
InstancePtr | is the XAxiPcie instance to operate on. |
DisableMask | is the bit pattern for interrupts wanted to be disabled. |
References XAxiPcie_Config::BaseAddress, XAxiPcie::Config, XAxiPcie::IsReady, XAXIPCIE_IM_OFFSET, XAxiPcie_ReadReg, and XAxiPcie_WriteReg.
Referenced by PCIeEndPointInitialize(), PcieInitRootComplex(), and XAxiPcie_CfgInitialize().
void XAxiPcie_EnableGlobalInterrupt | ( | XAxiPcie * | InstancePtr | ) |
Enable the Global Interrupt.
InstancePtr | is the XAxiPcie instance to operate on. |
References XAxiPcie_Config::BaseAddress, XAxiPcie::Config, XAxiPcie::IsReady, XAXIPCIE_BSC_GI_MASK, XAXIPCIE_BSC_GI_SHIFT, XAXIPCIE_BSC_OFFSET, XAxiPcie_ReadReg, and XAxiPcie_WriteReg.
void XAxiPcie_EnableInterrupts | ( | XAxiPcie * | InstancePtr, |
u32 | EnableMask | ||
) |
Enable the IP interrupt bits passed into "EnableMask".
InstancePtr | is the XAxiPcie instance to operate on. |
EnableMask | is the bit pattern for interrupts wanted to be enabled. |
References XAxiPcie_Config::BaseAddress, XAxiPcie::Config, XAxiPcie::IsReady, XAXIPCIE_IM_OFFSET, XAxiPcie_ReadReg, and XAxiPcie_WriteReg.
void XAxiPcie_GetBridgeInfo | ( | XAxiPcie * | InstancePtr, |
u8 * | Gen2Ptr, | ||
u8 * | RootPortPtr, | ||
u8 * | ECAMSizePtr | ||
) |
This API Reads the Bridge info register.
InstancePtr | is the XAxiPcie instance to operate on. |
Gen2Ptr | is a pointer to a variable indicating whether underlying PCIe block support PCIe Gen2 Speed. |
RootPortPtr | is a pointer to a variable indication whether underlying PCIe block is root port. |
ECAMSizePtr | is a pointer to a variable where it indicates ECAM size. Value is between 1 to 8. Total address bits dedicated to ECAM is 20 + ECAM size. |
References XAxiPcie_Config::BaseAddress, XAxiPcie::Config, XAxiPcie::IsReady, XAXIPCIE_BI_ECAM_SIZE_MASK, XAXIPCIE_BI_ECAM_SIZE_SHIFT, XAXIPCIE_BI_GEN2_MASK, XAXIPCIE_BI_OFFSET, XAXIPCIE_BI_RP_MASK, XAXIPCIE_BI_RP_SHIFT, and XAxiPcie_ReadReg.
void XAxiPcie_GetEnabledInterrupts | ( | XAxiPcie * | InstancePtr, |
u32 * | EnabledMaskPtr | ||
) |
Get the currently enabled interrupt bits of the IP and pass them back to the caller into "EnabledMask".
InstancePtr | is the XAxiPcie instance to operate on. |
EnabledMaskPtr | is a pointer to a variable where the driver will pass back the enabled interrupt bits after reading them from IP. |
References XAxiPcie_Config::BaseAddress, XAxiPcie::Config, XAxiPcie::IsReady, XAXIPCIE_IM_OFFSET, and XAxiPcie_ReadReg.
Referenced by PCIeEndPointInitialize(), and PcieInitRootComplex().
void XAxiPcie_GetLocalBusBar2PcieBar | ( | XAxiPcie * | InstancePtr, |
u8 | BarNumber, | ||
XAxiPcie_BarAddr * | BarAddrPtr | ||
) |
Read PCIe address translation vector that corresponds to one of AXI local bus bars passed by the caller.
InstancePtr | is the XAxiPcie instance to operate on. |
BarNumber | is AXI bar number (0 - 5) passed by caller. |
BarAddrPtr | is a pointer to a variable where the driver will . pass back translation vector. |
References XAxiPcie_Config::BaseAddress, XAxiPcie::Config, XAxiPcie_Config::IncludeBarOffsetReg, XAxiPcie_BarAddr::LowerAddr, XAxiPcie_BarAddr::UpperAddr, XAXIPCIE_AXIBAR2PCIBAR_0L_OFFSET, XAXIPCIE_AXIBAR2PCIBAR_0U_OFFSET, and XAxiPcie_ReadReg.
Referenced by PcieInitRootComplex().
void XAxiPcie_GetPendingInterrupts | ( | XAxiPcie * | InstancePtr, |
u32 * | PendingMaskPtr | ||
) |
Get the currently pending interrupt bits of the IP and pass them back to the caller into "PendingMask".
InstancePtr | is the XAxiPcie instance to operate on. |
PendingMaskPtr | is a pointer to a variable where the driver will pass back the pending interrupt bits after reading them from IP. |
References XAxiPcie_Config::BaseAddress, XAxiPcie::Config, XAxiPcie::IsReady, XAXIPCIE_ID_OFFSET, and XAxiPcie_ReadReg.
Referenced by PCIeEndPointInitialize(), and PcieInitRootComplex().
void XAxiPcie_GetPhyStatusCtrl | ( | XAxiPcie * | InstancePtr, |
u32 * | PhyState | ||
) |
This API is used to read the Phy Status/Control Register.
InstancePtr | is the XAxiPcie instance to operate on. |
PhyState | is a pointer to a variable where the driver will pass back Current physical status. |
References XAxiPcie_Config::BaseAddress, XAxiPcie::Config, XAxiPcie::IsReady, XAXIPCIE_PHYSC_OFFSET, and XAxiPcie_ReadReg.
void XAxiPcie_GetRequesterId | ( | XAxiPcie * | InstancePtr, |
u8 * | BusNumPtr, | ||
u8 * | DevNumPtr, | ||
u8 * | FunNumPtr, | ||
u8 * | PortNumPtr | ||
) |
Read the Bus Location register.
InstancePtr | is the XAxiPcie instance to operate on. |
BusNumPtr | is a pointer to a variable where the driver will pass back the bus number of requester ID assigned to IP. |
DevNumPtr | is a pointer to a variable where the driver will pass back the device number of requester ID assigned to IP. |
FunNumPtr | is a pointer to a variable where the driver will pass back the function number of requester ID assigned to IP. |
PortNumPtr | is a pointer to a variable where the driver will pass back the Port number of requester ID assigned to IP. |
References XAxiPcie_Config::BaseAddress, XAxiPcie::Config, XAxiPcie::IsReady, XAXIPCIE_BL_BUS_MASK, XAXIPCIE_BL_BUS_SHIFT, XAXIPCIE_BL_DEV_MASK, XAXIPCIE_BL_DEV_SHIFT, XAXIPCIE_BL_FUNC_MASK, XAXIPCIE_BL_OFFSET, XAXIPCIE_BL_PORT_MASK, XAXIPCIE_BL_PORT_SHIFT, and XAxiPcie_ReadReg.
Referenced by PCIeEndPointInitialize(), and PcieInitRootComplex().
void XAxiPcie_GetRootPortErrFIFOMsg | ( | XAxiPcie * | InstancePtr, |
u16 * | ReqIdPtr, | ||
u8 * | ErrType, | ||
u8 * | ErrValid | ||
) |
Read Root Port Error FIFO Message.
InstancePtr | is the PCIe component to operate on. |
ReqIdPtr | is a variable where the driver will pass back the requester Id of error message. |
ErrType | is a variable where the driver will pass back the type of error message |
ErrValid | is a variable where the driver will pass back the status of read operation of error message. |
References XAxiPcie_Config::BaseAddress, XAxiPcie::Config, XAxiPcie_Config::IncludeRootComplex, XAxiPcie::IsReady, XAxiPcie_ReadReg, XAXIPCIE_RPEFR_ERR_TYPE_MASK, XAXIPCIE_RPEFR_ERR_TYPE_SHIFT, XAXIPCIE_RPEFR_ERR_VALID_MASK, XAXIPCIE_RPEFR_ERR_VALID_SHIFT, XAXIPCIE_RPEFR_OFFSET, and XAXIPCIE_RPEFR_REQ_ID_MASK.
int XAxiPcie_GetRootPortIntFIFOReg | ( | XAxiPcie * | InstancePtr, |
u16 * | ReqIdPtr, | ||
u16 * | MsiAddr, | ||
u8 * | MsiInt, | ||
u8 * | IntValid, | ||
u16 * | MsiMsgData | ||
) |
Read Root Port Interrupt FIFO message Register 1 & 2.
InstancePtr | is the PCIe component to operate on. |
ReqIdPtr | is a variable where the driver will pass back the requester Id of error message. |
MsiAddr | is a variable where the driver will pass back the MSI address for which interrupt message received. |
MsiInt | is a variable where the driver will pass back the type of interrupt message received (MSI/INTx). |
IntValid | is a variable where the driver will pass back the status of read operation of interrupt message. |
MsiMsgData | is a variable where the driver will pass back the MSI data received. |
References XAxiPcie_Config::BaseAddress, XAxiPcie::Config, XAxiPcie_Config::IncludeRootComplex, XAxiPcie::IsReady, XAxiPcie_ReadReg, XAXIPCIE_RPIFR1_INTR_VALID_MASK, XAXIPCIE_RPIFR1_INTR_VALID_SHIFT, XAXIPCIE_RPIFR1_MSI_ADDR_MASK, XAXIPCIE_RPIFR1_MSI_ADDR_SHIFT, XAXIPCIE_RPIFR1_MSIINTR_VALID_MASK, XAXIPCIE_RPIFR1_MSIINTR_VALID_SHIFT, XAXIPCIE_RPIFR1_OFFSET, XAXIPCIE_RPIFR1_REQ_ID_MASK, XAXIPCIE_RPIFR2_MSG_DATA_MASK, and XAXIPCIE_RPIFR2_OFFSET.
void XAxiPcie_GetRootPortStatusCtrl | ( | XAxiPcie * | InstancePtr, |
u32 * | StatusPtr | ||
) |
Read Root Port Status/Control Register.
InstancePtr | is the PCIe component to operate on. |
StatusPtr | is a pointer to a variable where the driver will pass back the root port status. |
References XAxiPcie_Config::BaseAddress, XAxiPcie::Config, XAxiPcie_Config::IncludeRootComplex, XAxiPcie::IsReady, XAxiPcie_ReadReg, and XAXIPCIE_RPSC_OFFSET.
Referenced by PCIeEnumerateFabric().
void XAxiPcie_GetVsecCapability | ( | XAxiPcie * | InstancePtr, |
u8 | VsecNum, | ||
u16 * | VsecIdPtr, | ||
u8 * | VersionPtr, | ||
u16 * | NextCapPtr | ||
) |
This API is used to read the VSEC Capability Register.
InstancePtr | is the XAxiPcie instance to operate on. |
VsecNum | is a VSEC register number as there are two registers. Possible values are.
|
VsecIdPtr | is a pointer to a variable where the driver will pass back the Vendor Specific Enhanced Capability ID. |
VersionPtr | is a pointer to a variable where the driver will . pass back the Version of VSEC. |
NextCapPtr | is a pointer to a variable where the driver will pass back the Next Capability offset. |
References XAxiPcie_Config::BaseAddress, XAxiPcie::Config, XAxiPcie::IsReady, XAxiPcie_ReadReg, XAXIPCIE_VSECC_ID_MASK, XAXIPCIE_VSECC_NEXT_MASK, XAXIPCIE_VSECC_NEXT_SHIFT, XAXIPCIE_VSECC_OFFSET, XAXIPCIE_VSECC_VER_MASK, and XAXIPCIE_VSECC_VER_SHIFT.
void XAxiPcie_GetVsecHeader | ( | XAxiPcie * | InstancePtr, |
u8 | VsecNum, | ||
u16 * | VsecIdPtr, | ||
u8 * | RevisionPtr, | ||
u16 * | LengthPtr | ||
) |
This API is used to read the VSEC Header Register.
InstancePtr | is the XAxiPcie instance to operate on. |
VsecNum | is a VSEC register number as there are two registers. Possible values are.
|
VsecIdPtr | is a pointer to a variable where the driver will pass back the VSEC header structure Id. |
RevisionPtr | is a pointer to a variable where the driver will pass back the Revision of VSEC capability Structure. |
LengthPtr | is a pointer to a variable where the driver will pass . back the length of the VSEC capability structure. |
References XAxiPcie_Config::BaseAddress, XAxiPcie::Config, XAxiPcie::IsReady, XAxiPcie_ReadReg, XAXIPCIE_VSECH_ID_MASK, XAXIPCIE_VSECH_LEN_MASK, XAXIPCIE_VSECH_LEN_SHIFT, XAXIPCIE_VSECH_OFFSET, XAXIPCIE_VSECH_REV_MASK, and XAXIPCIE_VSECH_REV_SHIFT.
XAxiPcie_Config* XAxiPcie_LookupConfig | ( | u16 | DeviceId | ) |
Lookup the device configuration based on the unique device ID.
The table ConfigTable contains the configuration info for each device in the system.
DeviceId | is the device identifier to lookup. |
Referenced by PCIeEndPointInitialize(), and PcieInitRootComplex().
void XAxiPcie_ReadLocalConfigSpace | ( | XAxiPcie * | InstancePtr, |
u16 | Offset, | ||
u32 * | DataPtr | ||
) |
Read 32-bit value from one of this IP own configuration space.
Location is identified by its offset from the beginning of the configuration space.
InstancePtr | is the XAxiPcie instance to operate on. |
Offset | from beginning of IP own configuration space. |
DataPtr | is a pointer to a variable where the driver will pass back the value read from the specified location. |
References XAxiPcie_Config::BaseAddress, XAxiPcie::Config, XAxiPcie::IsReady, XAXIPCIE_PCIE_CORE_OFFSET, and XAxiPcie_ReadReg.
Referenced by PCIeEndPointInitialize(), and PcieInitRootComplex().
void XAxiPcie_ReadRemoteConfigSpace | ( | XAxiPcie * | InstancePtr, |
u8 | Bus, | ||
u8 | Device, | ||
u8 | Function, | ||
u16 | Offset, | ||
u32 * | DataPtr | ||
) |
Read 32-bit value from external PCIe Function's configuration space.
External PCIe function is identified by its Requester ID (Bus#, Device#, Function#). Location is identified by its offset from the beginning of the configuration space.
InstancePtr | is the PCIe component to operate on. |
Bus | is the external PCIe function's Bus number. |
Device | is the external PCIe function's Device number. |
Function | is the external PCIe function's Function number. |
Offset | from beggininng of PCIe function's configuration space. |
DataPtr | is a pointer to a variable where the driver will pass back the value read from the specified location. |
References XAxiPcie_Config::BaseAddress, XAxiPcie::Config, XAxiPcie_Config::IncludeRootComplex, XAxiPcie::IsReady, XAxiPcie::MaxNumOfBuses, XAxiPcie_IsEcamBusy, and XAxiPcie_ReadReg.
Referenced by PCIeEnumerateFabric().
void XAxiPcie_SetLocalBusBar2PcieBar | ( | XAxiPcie * | InstancePtr, |
u8 | BarNumber, | ||
XAxiPcie_BarAddr * | BarAddrPtr | ||
) |
Write PCIe address translation vector that corresponds to one of AXI local bus bars passed by the caller.
InstancePtr | is the XAxiPcie instance to operate on. |
BarNumber | is AXI bar number (0 - 5) passed by caller. |
BarAddrPtr | is a pointer to a variable where the driver will pass back translation vector. |
References XAxiPcie_Config::BaseAddress, XAxiPcie::Config, XAxiPcie_Config::IncludeBarOffsetReg, XAxiPcie_BarAddr::LowerAddr, XAxiPcie_BarAddr::UpperAddr, XAXIPCIE_AXIBAR2PCIBAR_0L_OFFSET, XAXIPCIE_AXIBAR2PCIBAR_0U_OFFSET, and XAxiPcie_WriteReg.
Referenced by PcieInitRootComplex().
int XAxiPcie_SetRootPortMSIBase | ( | XAxiPcie * | InstancePtr, |
unsigned long long | MsiBase | ||
) |
Write MSI Base Address to Root Port MSI Base Address Register.
InstancePtr | is the PCIe component to operate on. |
MsiBase | is 64 bit base address for MSI.This address should be 4kB aligned always. |
References XAxiPcie_Config::BaseAddress, XAxiPcie::Config, XAxiPcie_Config::IncludeRootComplex, XAxiPcie::IsReady, XAXIPCIE_RPMSIB_LOWER_MASK, XAXIPCIE_RPMSIB_LOWER_OFFSET, XAXIPCIE_RPMSIB_UPPER_MASK, XAXIPCIE_RPMSIB_UPPER_OFFSET, and XAxiPcie_WriteReg.
void XAxiPcie_SetRootPortStatusCtrl | ( | XAxiPcie * | InstancePtr, |
u32 | StatusData | ||
) |
Write Value in Root Port Status/Control Register.
InstancePtr | is the PCIe component to operate on. |
StatusData | is data to set. |
References XAxiPcie_Config::BaseAddress, XAxiPcie::Config, XAxiPcie_Config::IncludeRootComplex, XAxiPcie::IsReady, XAXIPCIE_RPSC_MASK, XAXIPCIE_RPSC_OFFSET, and XAxiPcie_WriteReg.
Referenced by PCIeEnumerateFabric().
void XAxiPcie_WriteLocalConfigSpace | ( | XAxiPcie * | InstancePtr, |
u16 | Offset, | ||
u32 | Data | ||
) |
Write 32-bit value to one of this IP own configuration space.
Location is identified by its offset from the beginning of the configuration space.
InstancePtr | is the PCIe component to operate on. |
Offset | from begininng of IP own configuration space. |
Data | to be written to the specified location. |
References XAxiPcie_Config::BaseAddress, XAxiPcie::Config, XAxiPcie_Config::IncludeRootComplex, XAxiPcie::IsReady, XAXIPCIE_PCIE_CORE_OFFSET, and XAxiPcie_WriteReg.
Referenced by PcieInitRootComplex().
void XAxiPcie_WriteRemoteConfigSpace | ( | XAxiPcie * | InstancePtr, |
u8 | Bus, | ||
u8 | Device, | ||
u8 | Function, | ||
u16 | Offset, | ||
u32 | Data | ||
) |
Write 32-bit value to external PCIe function's configuration space.
External PCIe function is identified by its Requester ID (Bus#, Device#, Function#). Location is identified by its offset from the beginning of the configuration space.
InstancePtr | is the PCIe component to operate on. |
Bus | is the external PCIe function's Bus number. |
Device | is the external PCIe function's Device number. |
Function | is the external PCIe function's Function number. |
Offset | from beggininng of PCIe function's configuration space. |
Data | to be written to the specified location. |
References XAxiPcie_Config::BaseAddress, XAxiPcie::Config, XAxiPcie_Config::IncludeRootComplex, XAxiPcie::IsReady, XAxiPcie::MaxNumOfBuses, XAxiPcie_IsEcamBusy, XAxiPcie_ReadReg, and XAxiPcie_WriteReg.
Referenced by PCIeEnumerateFabric().