bram
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XBram_Config Struct Reference

This typedef contains configuration information for the device. More...

#include <xbram.h>

Data Fields

char * Name
 Name of the device. More...
 
UINTPTR BaseAddress
 Device register base address. More...
 
u32 DataWidth
 BRAM data width. More...
 
int EccPresent
 Is ECC supported in H/W. More...
 
int FaultInjectionPresent
 Is Fault Injection supported in H/W. More...
 
int CorrectableFailingRegisters
 Is Correctable Failing Registers supported in H/W. More...
 
int CorrectableFailingDataRegs
 Is Correctable Failing Data Registers supported in H/W. More...
 
int UncorrectableFailingRegisters
 Is Un-correctable Failing Registers supported in H/W. More...
 
int UncorrectableFailingDataRegs
 Is Un-correctable Failing Data Registers supported in H/W. More...
 
int EccStatusInterruptPresent
 Are ECC status and interrupts supported in H/W. More...
 
int CorrectableCounterBits
 Number of bits in the Correctable Error Counter. More...
 
int EccOnOffRegister
 Is ECC on/off register supported in h/w. More...
 
int EccOnOffResetValue
 Reset value of the ECC on/off register in h/w. More...
 
int WriteAccess
 Is write access enabled in h/w. More...
 
UINTPTR MemBaseAddress
 Device memory base address. More...
 
UINTPTR MemHighAddress
 Device memory high address. More...
 
UINTPTR CtrlBaseAddress
 Device register base address. More...
 
UINTPTR CtrlHighAddress
 Device register base address. More...
 
u32 IntId
 Interrupt ID on GIC. More...
 
UINTPTR IntrParent
 Bit[0] Interrupt parent type Bit[64/32:1] Parent base address. More...
 

Detailed Description

This typedef contains configuration information for the device.

Field Documentation

UINTPTR XBram_Config::BaseAddress

Device register base address.

int XBram_Config::CorrectableCounterBits

Number of bits in the Correctable Error Counter.

Referenced by XBram_CfgInitialize(), and XBram_SelfTest().

int XBram_Config::CorrectableFailingDataRegs

Is Correctable Failing Data Registers supported in H/W.

Referenced by XBram_CfgInitialize(), and XBram_SelfTest().

int XBram_Config::CorrectableFailingRegisters

Is Correctable Failing Registers supported in H/W.

Referenced by XBram_CfgInitialize(), and XBram_SelfTest().

UINTPTR XBram_Config::CtrlHighAddress

Device register base address.

u32 XBram_Config::DataWidth

BRAM data width.

Referenced by XBram_CfgInitialize(), and XBram_SelfTest().

int XBram_Config::EccOnOffRegister

Is ECC on/off register supported in h/w.

int XBram_Config::EccOnOffResetValue

Reset value of the ECC on/off register in h/w.

int XBram_Config::EccPresent

Is ECC supported in H/W.

Referenced by XBram_CfgInitialize(), and XBram_SelfTest().

int XBram_Config::EccStatusInterruptPresent

Are ECC status and interrupts supported in H/W.

Referenced by BramIntrExample(), XBram_CfgInitialize(), and XBram_SelfTest().

int XBram_Config::FaultInjectionPresent

Is Fault Injection supported in H/W.

Referenced by BramIntrExample(), XBram_CfgInitialize(), and XBram_SelfTest().

u32 XBram_Config::IntId

Interrupt ID on GIC.

Referenced by BramIntrExample(), and XBram_CfgInitialize().

UINTPTR XBram_Config::IntrParent

Bit[0] Interrupt parent type Bit[64/32:1] Parent base address.

Referenced by BramIntrExample(), and XBram_CfgInitialize().

UINTPTR XBram_Config::MemBaseAddress

Device memory base address.

Referenced by XBram_CfgInitialize(), and XBram_SelfTest().

UINTPTR XBram_Config::MemHighAddress

Device memory high address.

Referenced by XBram_CfgInitialize(), and XBram_SelfTest().

char* XBram_Config::Name

Name of the device.

Referenced by XBram_LookupConfig().

int XBram_Config::UncorrectableFailingDataRegs

Is Un-correctable Failing Data Registers supported in H/W.

Referenced by BramIntrExample(), XBram_CfgInitialize(), and XBram_SelfTest().

int XBram_Config::UncorrectableFailingRegisters

Is Un-correctable Failing Registers supported in H/W.

Referenced by XBram_CfgInitialize(), and XBram_SelfTest().

int XBram_Config::WriteAccess

Is write access enabled in h/w.

Referenced by XBram_CfgInitialize(), and XBram_SelfTest().