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clk_wiz
Vitis Drivers API Documentation
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clk_wiz
Vitis Drivers API Documentation
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The configuration structure for CLK_WIZ Controller This structure passes the hardware building information to the driver. More...
Data Fields | |
| u32 | DeviceId |
| Device Id. More... | |
| UINTPTR | BaseAddr |
| Base address of CLK_WIZ Controller. More... | |
| u32 | EnableClkMon |
| It enables the Clock Monitor. More... | |
| u32 | EnableUserClkWiz0 |
| Enable user clk 0. More... | |
| u32 | EnableUserClkWiz1 |
| Enable user clk 1. More... | |
| u32 | EnableUserClkWiz2 |
| Enable user clk 2. More... | |
| u32 | EnableUserClkWiz3 |
| Enable user clk 3. More... | |
| double | RefClkFreq |
| Frequency of Reference Clock. More... | |
| double | UserClkFreq0 |
| Hold the user clock frequency0. More... | |
| double | UserClkFreq1 |
| Hold the user clock frequency1. More... | |
| double | UserClkFreq2 |
| Hold the user clock frequency2. More... | |
| double | UserClkFreq3 |
| Hold the user clock frequency3. More... | |
| double | Precision |
| Holds the value of precision. More... | |
| u8 | EnablePll0 |
specify if this user clock is going as input to the PLL/MMCM More... | |
| u8 | EnablePll1 |
specify if this user clock is going as input to the PLL/MMCM More... | |
| double | PrimInClkFreq |
| Input Clock. More... | |
| u32 | NumClocks |
| Number of clocks. More... | |
The configuration structure for CLK_WIZ Controller This structure passes the hardware building information to the driver.
| UINTPTR XClk_Wiz_Config::BaseAddr |
Base address of CLK_WIZ Controller.
Referenced by Clk_Wiz_Reconfig(), ClkWiz_Example(), ClkWiz_IntrExample(), Wait_For_Lock(), XClk_WaitForLock(), XClk_Wiz_CfgInitialize(), XClk_Wiz_DisableClock(), XClk_Wiz_EnableClock(), XClk_Wiz_SetRate(), and XClk_Wiz_SetRateHz().
| u32 XClk_Wiz_Config::DeviceId |
Device Id.
| u32 XClk_Wiz_Config::EnableClkMon |
It enables the Clock Monitor.
Referenced by ClkWiz_IntrExample().
| u8 XClk_Wiz_Config::EnablePll0 |
specify if this user clock is
going as input to the PLL/MMCM
| u8 XClk_Wiz_Config::EnablePll1 |
specify if this user clock is
going as input to the PLL/MMCM
| u32 XClk_Wiz_Config::EnableUserClkWiz0 |
Enable user clk 0.
| u32 XClk_Wiz_Config::EnableUserClkWiz1 |
Enable user clk 1.
| u32 XClk_Wiz_Config::EnableUserClkWiz2 |
Enable user clk 2.
| u32 XClk_Wiz_Config::EnableUserClkWiz3 |
Enable user clk 3.
| u32 XClk_Wiz_Config::NumClocks |
Number of clocks.
Referenced by XClk_Wiz_SetRate(), and XClk_Wiz_SetRateHz().
| double XClk_Wiz_Config::Precision |
Holds the value of precision.
| double XClk_Wiz_Config::PrimInClkFreq |
Input Clock.
Referenced by XClk_Wiz_SetInputRate().
| double XClk_Wiz_Config::RefClkFreq |
Frequency of Reference Clock.
| double XClk_Wiz_Config::UserClkFreq0 |
Hold the user clock frequency0.
| double XClk_Wiz_Config::UserClkFreq1 |
Hold the user clock frequency1.
| double XClk_Wiz_Config::UserClkFreq2 |
Hold the user clock frequency2.
| double XClk_Wiz_Config::UserClkFreq3 |
Hold the user clock frequency3.