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gpiops
Vitis Drivers API Documentation
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gpiops
Vitis Drivers API Documentation
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Macros | |
| #define | XGPIOPS_HW_H |
| by using protection macros More... | |
| #define | XGPIOPS_BYPM_MASK_OFFSET (u32)0x40 |
| Mask for backward support. More... | |
| #define | XGPIOPS_PS_GPIO_BASEADDR 0xFF0B0000U |
| Flag for Base Address for PS_GPIO in Versal. More... | |
| #define | XGPIOPS_ZERO 0U |
| Flag for 0 Value. More... | |
| #define | XGPIOPS_ONE 1U |
| Flag for 1 Value. More... | |
| #define | XGPIOPS_TWO 2U |
| Flag for 2 Value. More... | |
| #define | XGPIOPS_THREE 3U |
| Flag for 3 Value. More... | |
| #define | XGPIOPS_FOUR 4U |
| Flag for 4 Value. More... | |
| #define | XGPIOPS_SIX 6U |
| Flag for 6 Value. More... | |
| #define | XGpioPs_ReadReg(BaseAddr, RegOffset) Xil_In32((BaseAddr) + (u32)(RegOffset)) |
| This macro reads the given register. More... | |
| #define | XGpioPs_WriteReg(BaseAddr, RegOffset, Data) Xil_Out32((BaseAddr) + (u32)(RegOffset), (u32)(Data)) |
| This macro writes to the given register. More... | |
Register offsets for the GPIO. Each register is 32 bits. | |
| #define | XGPIOPS_DATA_LSW_OFFSET 0x00000000U |
| Mask and Data Register LSW, WO. More... | |
| #define | XGPIOPS_DATA_MSW_OFFSET 0x00000004U |
| Mask and Data Register MSW, WO. More... | |
| #define | XGPIOPS_DATA_OFFSET 0x00000040U |
| Data Register, RW. More... | |
| #define | XGPIOPS_DATA_RO_OFFSET 0x00000060U |
| Data Register - Input, RO. More... | |
| #define | XGPIOPS_DIRM_OFFSET 0x00000204U |
| Direction Mode Register, RW. More... | |
| #define | XGPIOPS_OUTEN_OFFSET 0x00000208U |
| Output Enable Register, RW. More... | |
| #define | XGPIOPS_INTMASK_OFFSET 0x0000020CU |
| Interrupt Mask Register, RO. More... | |
| #define | XGPIOPS_INTEN_OFFSET 0x00000210U |
| Interrupt Enable Register, WO. More... | |
| #define | XGPIOPS_INTDIS_OFFSET 0x00000214U |
| Interrupt Disable Register, WO. More... | |
| #define | XGPIOPS_INTSTS_OFFSET 0x00000218U |
| Interrupt Status Register, RO. More... | |
| #define | XGPIOPS_INTTYPE_OFFSET 0x0000021CU |
| Interrupt Type Register, RW. More... | |
| #define | XGPIOPS_INTPOL_OFFSET 0x00000220U |
| Interrupt Polarity Register, RW. More... | |
| #define | XGPIOPS_INTANY_OFFSET 0x00000224U |
| Interrupt On Any Register, RW. More... | |
Register offsets for each Bank. | |
| #define | XGPIOPS_DATA_MASK_OFFSET 0x00000008U |
| Data/Mask Registers offset. More... | |
| #define | XGPIOPS_DATA_BANK_OFFSET 0x00000004U |
| Data Registers offset. More... | |
| #define | XGPIOPS_REG_MASK_OFFSET 0x00000040U |
| Registers offset. More... | |
Interrupt type reset values for each bank | |
| #define | XGPIOPS_INTTYPE_BANK0_RESET 0xFFFFFFFFU |
| Resets specific to Zynq. More... | |
| #define | XGPIOPS_INTTYPE_BANK1_RESET 0x003FFFFFU |
| Resets specific to Zynq. More... | |
| #define | XGPIOPS_INTTYPE_BANK2_RESET 0xFFFFFFFFU |
| Resets specific to Zynq. More... | |
| #define | XGPIOPS_INTTYPE_BANK3_RESET 0xFFFFFFFFU |
| Reset common to both platforms. More... | |
| #define | XGPIOPS_INTTYPE_BANK4_RESET 0xFFFFFFFFU |
| Resets specific to Zynq Ultrascale+ MP. More... | |
| #define | XGPIOPS_INTTYPE_BANK5_RESET 0xFFFFFFFFU |
| Resets specific to Zynq Ultrascale+ MP. More... | |
Functions | |
| void | XGpioPs_ResetHw (UINTPTR BaseAddress) |
| This function resets the GPIO module by writing reset values to all registers. More... | |